[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
#else
#define pdebug(fmt, ...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    int it_shift;
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;
    int dir;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);

        if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
            if (val & PARA_CTR_DIR) {
                dir = 1;
            } else {
                dir = 0;
            }
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
            parm &= ~PARA_CTR_DIR;
        }

        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 7;
    pdebug("wecp%d=%02x\n", addr, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;
    addr &= 7;
    pdebug("recp%d:%02x\n", addr, ret);
    return ret;
}

static void parallel_reset(void *opaque)
{
    ParallelState *s = opaque;

    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq_pending = 0;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    s->irq = irq;
    s->chr = chr;
    parallel_reset(s);
    qemu_register_reset(parallel_reset, s);

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    if (s->hw_driver) {
        register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
        register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
        register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
        register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
        register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
        register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
        register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
        register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return s;
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}

static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
    &parallel_mm_readb,
    &parallel_mm_readw,
    &parallel_mm_readl,
};

static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
    &parallel_mm_writeb,
    &parallel_mm_writew,
    &parallel_mm_writel,
};

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    int io_sw;

    s = qemu_mallocz(sizeof(ParallelState));
    s->irq = irq;
    s->chr = chr;
    s->it_shift = it_shift;
    parallel_reset(s);
    qemu_register_reset(parallel_reset, s);

    io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
    cpu_register_physical_memory(base, 8 << it_shift, io_sw);
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
	26	#include "qemu-char.h"
	27	#include "isa.h"
	28	#include "pc.h"
6508fe59 FB	29
	30	//#define DEBUG_PARALLEL
	31
5867c88a	32	#ifdef DEBUG_PARALLEL
001faf32	33	#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
5867c88a	34	#else
001faf32	35	#define pdebug(fmt, ...) ((void)0)
5867c88a TS	36	#endif
	37
	38	#define PARA_REG_DATA 0
	39	#define PARA_REG_STS 1
	40	#define PARA_REG_CTR 2
	41	#define PARA_REG_EPP_ADDR 3
	42	#define PARA_REG_EPP_DATA 4
	43
6508fe59 FB	44	/*
	45	* These are the definitions for the Printer Status Register
	46	*/
	47	#define PARA_STS_BUSY 0x80 /* Busy complement */
	48	#define PARA_STS_ACK 0x40 /* Acknowledge */
	49	#define PARA_STS_PAPER 0x20 /* Out of paper */
	50	#define PARA_STS_ONLINE 0x10 /* Online */
	51	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	52	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	53
	54	/*
	55	* These are the definitions for the Printer Control Register
	56	*/
5867c88a	57	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	58	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	59	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	60	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	61	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	62	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	63
5867c88a TS	64	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	65
6508fe59	66	struct ParallelState {
5867c88a TS	67	uint8_t dataw;
	68	uint8_t datar;
	69	uint8_t status;
6508fe59	70	uint8_t control;
d537cf6c	71	qemu_irq irq;
6508fe59 FB	72	int irq_pending;
6508fe59 FB	73	CharDriverState *chr;
e57a8c0e	74	int hw_driver;
5867c88a TS	75	int epp_timeout;
5867c88a TS	76	uint32_t last_read_offset; /* For debugging */
d60532ca	77	/* Memory-mapped interface */
d60532ca	78	int it_shift;
6508fe59 FB	79	};
	80
	81	static void parallel_update_irq(ParallelState *s)
	82	{
	83	if (s->irq_pending)
d537cf6c	84	qemu_irq_raise(s->irq);
6508fe59	85	else
d537cf6c	86	qemu_irq_lower(s->irq);
6508fe59 FB	87	}
6508fe59 FB	88
5867c88a TS	89	static void
5867c88a TS	90	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	91	{
6508fe59 FB	92	ParallelState *s = opaque;
3b46e624	93
5867c88a TS	94	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	95
	96	addr &= 7;
	97	switch(addr) {
	98	case PARA_REG_DATA:
0fa7f157 TS	99	s->dataw = val;
0fa7f157 TS	100	parallel_update_irq(s);
5867c88a TS	101	break;
5867c88a TS	102	case PARA_REG_CTR:
52ccc5e0	103	val \|= 0xc0;
0fa7f157 TS	104	if ((val & PARA_CTR_INIT) == 0 ) {
	105	s->status = PARA_STS_BUSY;
	106	s->status \|= PARA_STS_ACK;
	107	s->status \|= PARA_STS_ONLINE;
	108	s->status \|= PARA_STS_ERROR;
	109	}
	110	else if (val & PARA_CTR_SELECT) {
	111	if (val & PARA_CTR_STROBE) {
	112	s->status &= ~PARA_STS_BUSY;
	113	if ((s->control & PARA_CTR_STROBE) == 0)
	114	qemu_chr_write(s->chr, &s->dataw, 1);
	115	} else {
	116	if (s->control & PARA_CTR_INTEN) {
	117	s->irq_pending = 1;
	118	}
	119	}
	120	}
	121	parallel_update_irq(s);
	122	s->control = val;
5867c88a TS	123	break;
	124	}
	125	}
	126
	127	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	128	{
	129	ParallelState *s = opaque;
	130	uint8_t parm = val;
563e3c6e	131	int dir;
5867c88a TS	132
	133	/* Sometimes programs do several writes for timing purposes on old
	134	HW. Take care not to waste time on writes that do nothing. */
	135
	136	s->last_read_offset = ~0U;
	137
6508fe59	138	addr &= 7;
6508fe59	139	switch(addr) {
5867c88a TS	140	case PARA_REG_DATA:
5867c88a TS	141	if (s->dataw == val)
0fa7f157 TS	142	return;
	143	pdebug("wd%02x\n", val);
	144	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	145	s->dataw = val;
6508fe59	146	break;
5867c88a	147	case PARA_REG_STS:
0fa7f157 TS	148	pdebug("ws%02x\n", val);
	149	if (val & PARA_STS_TMOUT)
	150	s->epp_timeout = 0;
	151	break;
5867c88a TS	152	case PARA_REG_CTR:
	153	val \|= 0xc0;
	154	if (s->control == val)
0fa7f157 TS	155	return;
0fa7f157 TS	156	pdebug("wc%02x\n", val);
563e3c6e AJ	157
	158	if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
	159	if (val & PARA_CTR_DIR) {
	160	dir = 1;
	161	} else {
	162	dir = 0;
	163	}
	164	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
	165	parm &= ~PARA_CTR_DIR;
	166	}
	167
0fa7f157 TS	168	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
0fa7f157 TS	169	s->control = val;
6508fe59	170	break;
5867c88a	171	case PARA_REG_EPP_ADDR:
0fa7f157 TS	172	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	173	/* Controls not correct for EPP address cycle, so do nothing */
	174	pdebug("wa%02x s\n", val);
	175	else {
	176	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	177	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	178	s->epp_timeout = 1;
	179	pdebug("wa%02x t\n", val);
	180	}
	181	else
	182	pdebug("wa%02x\n", val);
	183	}
	184	break;
5867c88a	185	case PARA_REG_EPP_DATA:
0fa7f157 TS	186	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	187	/* Controls not correct for EPP data cycle, so do nothing */
	188	pdebug("we%02x s\n", val);
	189	else {
	190	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	191	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	192	s->epp_timeout = 1;
	193	pdebug("we%02x t\n", val);
	194	}
	195	else
	196	pdebug("we%02x\n", val);
	197	}
	198	break;
5867c88a TS	199	}
	200	}
	201
	202	static void
	203	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	204	{
	205	ParallelState *s = opaque;
	206	uint16_t eppdata = cpu_to_le16(val);
	207	int err;
	208	struct ParallelIOArg ioarg = {
0fa7f157	209	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	210	};
5867c88a TS	211	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	212	/* Controls not correct for EPP data cycle, so do nothing */
	213	pdebug("we%04x s\n", val);
	214	return;
5867c88a TS	215	}
	216	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	217	if (err) {
0fa7f157 TS	218	s->epp_timeout = 1;
0fa7f157 TS	219	pdebug("we%04x t\n", val);
5867c88a TS	220	}
5867c88a TS	221	else
0fa7f157	222	pdebug("we%04x\n", val);
5867c88a TS	223	}
	224
	225	static void
	226	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	227	{
	228	ParallelState *s = opaque;
	229	uint32_t eppdata = cpu_to_le32(val);
	230	int err;
	231	struct ParallelIOArg ioarg = {
0fa7f157	232	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	233	};
5867c88a TS	234	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	235	/* Controls not correct for EPP data cycle, so do nothing */
	236	pdebug("we%08x s\n", val);
	237	return;
5867c88a TS	238	}
	239	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	240	if (err) {
0fa7f157 TS	241	s->epp_timeout = 1;
0fa7f157 TS	242	pdebug("we%08x t\n", val);
6508fe59	243	}
5867c88a	244	else
0fa7f157	245	pdebug("we%08x\n", val);
6508fe59 FB	246	}
6508fe59 FB	247
5867c88a	248	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	249	{
	250	ParallelState *s = opaque;
	251	uint32_t ret = 0xff;
	252
	253	addr &= 7;
	254	switch(addr) {
5867c88a	255	case PARA_REG_DATA:
0fa7f157 TS	256	if (s->control & PARA_CTR_DIR)
	257	ret = s->datar;
	258	else
	259	ret = s->dataw;
6508fe59	260	break;
5867c88a	261	case PARA_REG_STS:
0fa7f157 TS	262	ret = s->status;
	263	s->irq_pending = 0;
	264	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	265	/* XXX Fixme: wait 5 microseconds */
	266	if (s->status & PARA_STS_ACK)
	267	s->status &= ~PARA_STS_ACK;
	268	else {
	269	/* XXX Fixme: wait 5 microseconds */
	270	s->status \|= PARA_STS_ACK;
	271	s->status \|= PARA_STS_BUSY;
	272	}
	273	}
	274	parallel_update_irq(s);
6508fe59	275	break;
5867c88a	276	case PARA_REG_CTR:
6508fe59 FB	277	ret = s->control;
	278	break;
	279	}
5867c88a TS	280	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	281	return ret;
	282	}
	283
	284	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	285	{
	286	ParallelState *s = opaque;
	287	uint8_t ret = 0xff;
	288	addr &= 7;
	289	switch(addr) {
	290	case PARA_REG_DATA:
0fa7f157 TS	291	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	292	if (s->last_read_offset != addr \|\| s->datar != ret)
	293	pdebug("rd%02x\n", ret);
5867c88a TS	294	s->datar = ret;
	295	break;
	296	case PARA_REG_STS:
0fa7f157 TS	297	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	298	ret &= ~PARA_STS_TMOUT;
	299	if (s->epp_timeout)
	300	ret \|= PARA_STS_TMOUT;
	301	if (s->last_read_offset != addr \|\| s->status != ret)
	302	pdebug("rs%02x\n", ret);
	303	s->status = ret;
5867c88a TS	304	break;
	305	case PARA_REG_CTR:
	306	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	307	it has not been yet written to. */
	308	if (s->control == 0) {
	309	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	310	if (s->last_read_offset != addr)
	311	pdebug("rc%02x\n", ret);
	312	s->control = ret;
	313	}
	314	else {
	315	ret = s->control;
	316	if (s->last_read_offset != addr)
	317	pdebug("rc%02x\n", ret);
	318	}
5867c88a TS	319	break;
5867c88a TS	320	case PARA_REG_EPP_ADDR:
0fa7f157 TS	321	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	322	/* Controls not correct for EPP addr cycle, so do nothing */
	323	pdebug("ra%02x s\n", ret);
	324	else {
	325	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	326	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	327	s->epp_timeout = 1;
	328	pdebug("ra%02x t\n", ret);
	329	}
	330	else
	331	pdebug("ra%02x\n", ret);
	332	}
	333	break;
5867c88a	334	case PARA_REG_EPP_DATA:
0fa7f157 TS	335	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	336	/* Controls not correct for EPP data cycle, so do nothing */
	337	pdebug("re%02x s\n", ret);
	338	else {
	339	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	340	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	341	s->epp_timeout = 1;
	342	pdebug("re%02x t\n", ret);
	343	}
	344	else
	345	pdebug("re%02x\n", ret);
	346	}
	347	break;
5867c88a TS	348	}
	349	s->last_read_offset = addr;
	350	return ret;
	351	}
	352
	353	static uint32_t
	354	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	355	{
	356	ParallelState *s = opaque;
	357	uint32_t ret;
	358	uint16_t eppdata = ~0;
	359	int err;
	360	struct ParallelIOArg ioarg = {
0fa7f157	361	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	362	};
5867c88a TS	363	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	364	/* Controls not correct for EPP data cycle, so do nothing */
	365	pdebug("re%04x s\n", eppdata);
	366	return eppdata;
5867c88a TS	367	}
	368	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	369	ret = le16_to_cpu(eppdata);
	370
	371	if (err) {
0fa7f157 TS	372	s->epp_timeout = 1;
0fa7f157 TS	373	pdebug("re%04x t\n", ret);
5867c88a TS	374	}
5867c88a TS	375	else
0fa7f157	376	pdebug("re%04x\n", ret);
5867c88a TS	377	return ret;
	378	}
	379
	380	static uint32_t
	381	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	382	{
	383	ParallelState *s = opaque;
	384	uint32_t ret;
	385	uint32_t eppdata = ~0U;
	386	int err;
	387	struct ParallelIOArg ioarg = {
0fa7f157	388	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	389	};
5867c88a TS	390	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	391	/* Controls not correct for EPP data cycle, so do nothing */
	392	pdebug("re%08x s\n", eppdata);
	393	return eppdata;
5867c88a TS	394	}
	395	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	396	ret = le32_to_cpu(eppdata);
	397
	398	if (err) {
0fa7f157 TS	399	s->epp_timeout = 1;
0fa7f157 TS	400	pdebug("re%08x t\n", ret);
5867c88a TS	401	}
5867c88a TS	402	else
0fa7f157	403	pdebug("re%08x\n", ret);
5867c88a TS	404	return ret;
	405	}
	406
	407	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	408	{
	409	addr &= 7;
	410	pdebug("wecp%d=%02x\n", addr, val);
	411	}
	412
	413	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	414	{
	415	uint8_t ret = 0xff;
	416	addr &= 7;
	417	pdebug("recp%d:%02x\n", addr, ret);
6508fe59 FB	418	return ret;
	419	}
	420
33093a0a	421	static void parallel_reset(void *opaque)
6508fe59	422	{
33093a0a AJ	423	ParallelState *s = opaque;
33093a0a AJ	424
5867c88a TS	425	s->datar = ~0;
5867c88a TS	426	s->dataw = ~0;
6508fe59 FB	427	s->status = PARA_STS_BUSY;
	428	s->status \|= PARA_STS_ACK;
	429	s->status \|= PARA_STS_ONLINE;
	430	s->status \|= PARA_STS_ERROR;
52ccc5e0	431	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	432	s->control = PARA_CTR_SELECT;
6508fe59 FB	433	s->control \|= PARA_CTR_INIT;
52ccc5e0	434	s->control \|= 0xc0;
5867c88a	435	s->irq_pending = 0;
5867c88a TS	436	s->hw_driver = 0;
	437	s->epp_timeout = 0;
	438	s->last_read_offset = ~0U;
d60532ca TS	439	}
	440
	441	/* If fd is zero, it means that the parallel device uses the console */
	442	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr)
	443	{
	444	ParallelState *s;
	445	uint8_t dummy;
	446
	447	s = qemu_mallocz(sizeof(ParallelState));
33093a0a AJ	448	s->irq = irq;
	449	s->chr = chr;
	450	parallel_reset(s);
a08d4367	451	qemu_register_reset(parallel_reset, s);
6508fe59	452
5867c88a TS	453	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a TS	454	s->hw_driver = 1;
0fa7f157	455	s->status = dummy;
5867c88a TS	456	}
	457
	458	if (s->hw_driver) {
0fa7f157 TS	459	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	460	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	461	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	462	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	463	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	464	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	465	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	466	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a TS	467	}
5867c88a TS	468	else {
0fa7f157 TS	469	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
0fa7f157 TS	470	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a	471	}
6508fe59 FB	472	return s;
6508fe59 FB	473	}
d60532ca TS	474
d60532ca TS	475	/* Memory mapped interface */
c227f099	476	static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca TS	477	{
	478	ParallelState *s = opaque;
	479
8da3ff18	480	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
d60532ca TS	481	}
d60532ca TS	482
9596ebb7	483	static void parallel_mm_writeb (void *opaque,
c227f099	484	target_phys_addr_t addr, uint32_t value)
d60532ca TS	485	{
	486	ParallelState *s = opaque;
	487
8da3ff18	488	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
d60532ca TS	489	}
d60532ca TS	490
c227f099	491	static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca TS	492	{
	493	ParallelState *s = opaque;
	494
8da3ff18	495	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
d60532ca TS	496	}
d60532ca TS	497
9596ebb7	498	static void parallel_mm_writew (void *opaque,
c227f099	499	target_phys_addr_t addr, uint32_t value)
d60532ca TS	500	{
	501	ParallelState *s = opaque;
	502
8da3ff18	503	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
d60532ca TS	504	}
d60532ca TS	505
c227f099	506	static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca TS	507	{
	508	ParallelState *s = opaque;
	509
8da3ff18	510	return parallel_ioport_read_sw(s, addr >> s->it_shift);
d60532ca TS	511	}
d60532ca TS	512
9596ebb7	513	static void parallel_mm_writel (void *opaque,
c227f099	514	target_phys_addr_t addr, uint32_t value)
d60532ca TS	515	{
	516	ParallelState *s = opaque;
	517
8da3ff18	518	parallel_ioport_write_sw(s, addr >> s->it_shift, value);
d60532ca TS	519	}
d60532ca TS	520
d60efc6b	521	static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
d60532ca TS	522	&parallel_mm_readb,
	523	&parallel_mm_readw,
	524	&parallel_mm_readl,
	525	};
	526
d60efc6b	527	static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
d60532ca TS	528	&parallel_mm_writeb,
	529	&parallel_mm_writew,
	530	&parallel_mm_writel,
	531	};
	532
	533	/* If fd is zero, it means that the parallel device uses the console */
c227f099	534	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr)
d60532ca TS	535	{
	536	ParallelState *s;
	537	int io_sw;
	538
	539	s = qemu_mallocz(sizeof(ParallelState));
33093a0a AJ	540	s->irq = irq;
33093a0a AJ	541	s->chr = chr;
d60532ca	542	s->it_shift = it_shift;
33093a0a	543	parallel_reset(s);
a08d4367	544	qemu_register_reset(parallel_reset, s);
d60532ca	545
1eed09cb	546	io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
d60532ca TS	547	cpu_register_physical_memory(base, 8 << it_shift, io_sw);
	548	return s;
	549	}