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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
488cb996 | 26 | #include "serial.h" |
aa28b9bf | 27 | #include "apic.h" |
87ecb68b | 28 | #include "fdc.h" |
c0897e0c | 29 | #include "ide.h" |
87ecb68b | 30 | #include "pci.h" |
376253ec | 31 | #include "monitor.h" |
3cce6243 | 32 | #include "fw_cfg.h" |
16b29ae1 | 33 | #include "hpet_emul.h" |
b6f6e3d3 | 34 | #include "smbios.h" |
ca20cf32 BS |
35 | #include "loader.h" |
36 | #include "elf.h" | |
52001445 | 37 | #include "multiboot.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
302fe51b | 40 | #include "pcspk.h" |
60ba3cc2 | 41 | #include "msi.h" |
822557eb | 42 | #include "sysbus.h" |
666daa68 | 43 | #include "sysemu.h" |
9b5b76d4 | 44 | #include "kvm.h" |
1d31f66b | 45 | #include "kvm_i386.h" |
9468e9c4 | 46 | #include "xen.h" |
2446333c | 47 | #include "blockdev.h" |
2b584959 | 48 | #include "hw/block-common.h" |
a19cbfb3 | 49 | #include "ui/qemu-spice.h" |
00cb2a99 | 50 | #include "memory.h" |
be20f9e9 | 51 | #include "exec-memory.h" |
c2d8d311 | 52 | #include "arch_init.h" |
ee785fed | 53 | #include "bitmap.h" |
80cabfad | 54 | |
471fd342 BS |
55 | /* debug PC/ISA interrupts */ |
56 | //#define DEBUG_IRQ | |
57 | ||
58 | #ifdef DEBUG_IRQ | |
59 | #define DPRINTF(fmt, ...) \ | |
60 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
61 | #else | |
62 | #define DPRINTF(fmt, ...) | |
63 | #endif | |
64 | ||
a80274c3 PB |
65 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
66 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 67 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 68 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 69 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 70 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 71 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 72 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 73 | |
4c5b10b7 JS |
74 | #define E820_NR_ENTRIES 16 |
75 | ||
76 | struct e820_entry { | |
77 | uint64_t address; | |
78 | uint64_t length; | |
79 | uint32_t type; | |
541dc0d4 | 80 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
81 | |
82 | struct e820_table { | |
83 | uint32_t count; | |
84 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 85 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
86 | |
87 | static struct e820_table e820_table; | |
dd703b99 | 88 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 89 | |
b881fbe9 | 90 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 91 | { |
b881fbe9 | 92 | GSIState *s = opaque; |
1452411b | 93 | |
b881fbe9 JK |
94 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
95 | if (n < ISA_NUM_IRQS) { | |
96 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 97 | } |
b881fbe9 | 98 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 99 | } |
1452411b | 100 | |
b41a2cd1 | 101 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
102 | { |
103 | } | |
104 | ||
f929aad6 | 105 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 106 | static qemu_irq ferr_irq; |
8e78eb28 IY |
107 | |
108 | void pc_register_ferr_irq(qemu_irq irq) | |
109 | { | |
110 | ferr_irq = irq; | |
111 | } | |
112 | ||
f929aad6 FB |
113 | /* XXX: add IGNNE support */ |
114 | void cpu_set_ferr(CPUX86State *s) | |
115 | { | |
d537cf6c | 116 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
117 | } |
118 | ||
119 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
120 | { | |
d537cf6c | 121 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
122 | } |
123 | ||
28ab0e2e | 124 | /* TSC handling */ |
28ab0e2e FB |
125 | uint64_t cpu_get_tsc(CPUX86State *env) |
126 | { | |
4a1418e0 | 127 | return cpu_get_ticks(); |
28ab0e2e FB |
128 | } |
129 | ||
a5954d5c | 130 | /* SMM support */ |
f885f1ea IY |
131 | |
132 | static cpu_set_smm_t smm_set; | |
133 | static void *smm_arg; | |
134 | ||
135 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
136 | { | |
137 | assert(smm_set == NULL); | |
138 | assert(smm_arg == NULL); | |
139 | smm_set = callback; | |
140 | smm_arg = arg; | |
141 | } | |
142 | ||
4a8fa5dc | 143 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 144 | { |
f885f1ea IY |
145 | if (smm_set && smm_arg && env == first_cpu) |
146 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
147 | } |
148 | ||
149 | ||
3de388f6 | 150 | /* IRQ handling */ |
4a8fa5dc | 151 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 FB |
152 | { |
153 | int intno; | |
154 | ||
cf6d64bf | 155 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 | 156 | if (intno >= 0) { |
3de388f6 FB |
157 | return intno; |
158 | } | |
3de388f6 | 159 | /* read the irq from the PIC */ |
cf6d64bf | 160 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 161 | return -1; |
cf6d64bf | 162 | } |
0e21e12b | 163 | |
3de388f6 FB |
164 | intno = pic_read_irq(isa_pic); |
165 | return intno; | |
166 | } | |
167 | ||
d537cf6c | 168 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 169 | { |
4a8fa5dc | 170 | CPUX86State *env = first_cpu; |
a5b38b51 | 171 | |
471fd342 | 172 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
173 | if (env->apic_state) { |
174 | while (env) { | |
cf6d64bf BS |
175 | if (apic_accept_pic_intr(env->apic_state)) { |
176 | apic_deliver_pic_intr(env->apic_state, level); | |
177 | } | |
d5529471 AJ |
178 | env = env->next_cpu; |
179 | } | |
180 | } else { | |
b614106a AJ |
181 | if (level) |
182 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
183 | else | |
184 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 185 | } |
3de388f6 FB |
186 | } |
187 | ||
b0a21b53 FB |
188 | /* PC cmos mappings */ |
189 | ||
80cabfad FB |
190 | #define REG_EQUIPMENT_BYTE 0x14 |
191 | ||
d288c7ba | 192 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
193 | { |
194 | int val; | |
195 | ||
196 | switch (fd0) { | |
d288c7ba | 197 | case FDRIVE_DRV_144: |
777428f2 FB |
198 | /* 1.44 Mb 3"5 drive */ |
199 | val = 4; | |
200 | break; | |
d288c7ba | 201 | case FDRIVE_DRV_288: |
777428f2 FB |
202 | /* 2.88 Mb 3"5 drive */ |
203 | val = 5; | |
204 | break; | |
d288c7ba | 205 | case FDRIVE_DRV_120: |
777428f2 FB |
206 | /* 1.2 Mb 5"5 drive */ |
207 | val = 2; | |
208 | break; | |
d288c7ba | 209 | case FDRIVE_DRV_NONE: |
777428f2 FB |
210 | default: |
211 | val = 0; | |
212 | break; | |
213 | } | |
214 | return val; | |
215 | } | |
216 | ||
9139046c MA |
217 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
218 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 219 | { |
ba6c2377 FB |
220 | rtc_set_memory(s, type_ofs, 47); |
221 | rtc_set_memory(s, info_ofs, cylinders); | |
222 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
223 | rtc_set_memory(s, info_ofs + 2, heads); | |
224 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
225 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
226 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
227 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
228 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
229 | rtc_set_memory(s, info_ofs + 8, sectors); | |
230 | } | |
231 | ||
6ac0e82d AZ |
232 | /* convert boot_device letter to something recognizable by the bios */ |
233 | static int boot_device2nibble(char boot_device) | |
234 | { | |
235 | switch(boot_device) { | |
236 | case 'a': | |
237 | case 'b': | |
238 | return 0x01; /* floppy boot */ | |
239 | case 'c': | |
240 | return 0x02; /* hard drive boot */ | |
241 | case 'd': | |
242 | return 0x03; /* CD-ROM boot */ | |
243 | case 'n': | |
244 | return 0x04; /* Network boot */ | |
245 | } | |
246 | return 0; | |
247 | } | |
248 | ||
1d914fa0 | 249 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
250 | { |
251 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
252 | int nbds, bds[3] = { 0, }; |
253 | int i; | |
254 | ||
255 | nbds = strlen(boot_device); | |
256 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 257 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
258 | return(1); |
259 | } | |
260 | for (i = 0; i < nbds; i++) { | |
261 | bds[i] = boot_device2nibble(boot_device[i]); | |
262 | if (bds[i] == 0) { | |
1ecda02b MA |
263 | error_report("Invalid boot device for PC: '%c'", |
264 | boot_device[i]); | |
0ecdffbb AJ |
265 | return(1); |
266 | } | |
267 | } | |
268 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 269 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
270 | return(0); |
271 | } | |
272 | ||
d9346e81 MA |
273 | static int pc_boot_set(void *opaque, const char *boot_device) |
274 | { | |
275 | return set_boot_dev(opaque, boot_device, 0); | |
276 | } | |
277 | ||
c0897e0c MA |
278 | typedef struct pc_cmos_init_late_arg { |
279 | ISADevice *rtc_state; | |
9139046c | 280 | BusState *idebus[2]; |
c0897e0c MA |
281 | } pc_cmos_init_late_arg; |
282 | ||
283 | static void pc_cmos_init_late(void *opaque) | |
284 | { | |
285 | pc_cmos_init_late_arg *arg = opaque; | |
286 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
287 | int16_t cylinders; |
288 | int8_t heads, sectors; | |
c0897e0c | 289 | int val; |
2adc99b2 | 290 | int i, trans; |
c0897e0c | 291 | |
9139046c MA |
292 | val = 0; |
293 | if (ide_get_geometry(arg->idebus[0], 0, | |
294 | &cylinders, &heads, §ors) >= 0) { | |
295 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
296 | val |= 0xf0; | |
297 | } | |
298 | if (ide_get_geometry(arg->idebus[0], 1, | |
299 | &cylinders, &heads, §ors) >= 0) { | |
300 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
301 | val |= 0x0f; | |
302 | } | |
303 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
304 | |
305 | val = 0; | |
306 | for (i = 0; i < 4; i++) { | |
9139046c MA |
307 | /* NOTE: ide_get_geometry() returns the physical |
308 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
309 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
310 | geometry can be different if a translation is done. */ | |
311 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
312 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
313 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
314 | assert((trans & ~3) == 0); | |
315 | val |= trans << (i * 2); | |
c0897e0c MA |
316 | } |
317 | } | |
318 | rtc_set_memory(s, 0x39, val); | |
319 | ||
320 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
321 | } | |
322 | ||
845773ab | 323 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 324 | const char *boot_device, |
34d4260e | 325 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 326 | ISADevice *s) |
80cabfad | 327 | { |
61a8d649 | 328 | int val, nb, i; |
980bda8b | 329 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 330 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 331 | |
b0a21b53 | 332 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
333 | |
334 | /* memory size */ | |
e89001f7 MA |
335 | /* base memory (first MiB) */ |
336 | val = MIN(ram_size / 1024, 640); | |
333190eb FB |
337 | rtc_set_memory(s, 0x15, val); |
338 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 MA |
339 | /* extended memory (next 64MiB) */ |
340 | if (ram_size > 1024 * 1024) { | |
341 | val = (ram_size - 1024 * 1024) / 1024; | |
342 | } else { | |
343 | val = 0; | |
344 | } | |
80cabfad FB |
345 | if (val > 65535) |
346 | val = 65535; | |
b0a21b53 FB |
347 | rtc_set_memory(s, 0x17, val); |
348 | rtc_set_memory(s, 0x18, val >> 8); | |
349 | rtc_set_memory(s, 0x30, val); | |
350 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 MA |
351 | /* memory between 16MiB and 4GiB */ |
352 | if (ram_size > 16 * 1024 * 1024) { | |
353 | val = (ram_size - 16 * 1024 * 1024) / 65536; | |
354 | } else { | |
9da98861 | 355 | val = 0; |
e89001f7 | 356 | } |
80cabfad FB |
357 | if (val > 65535) |
358 | val = 65535; | |
b0a21b53 FB |
359 | rtc_set_memory(s, 0x34, val); |
360 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 MA |
361 | /* memory above 4GiB */ |
362 | val = above_4g_mem_size / 65536; | |
363 | rtc_set_memory(s, 0x5b, val); | |
364 | rtc_set_memory(s, 0x5c, val >> 8); | |
365 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 366 | |
298e01b6 AJ |
367 | /* set the number of CPU */ |
368 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
369 | ||
6ac0e82d | 370 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 371 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
372 | exit(1); |
373 | } | |
80cabfad | 374 | |
b41a2cd1 | 375 | /* floppy type */ |
34d4260e | 376 | if (floppy) { |
34d4260e | 377 | for (i = 0; i < 2; i++) { |
61a8d649 | 378 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
379 | } |
380 | } | |
381 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
382 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 383 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 384 | |
b0a21b53 | 385 | val = 0; |
b41a2cd1 | 386 | nb = 0; |
63ffb564 | 387 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 388 | nb++; |
d288c7ba | 389 | } |
63ffb564 | 390 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 391 | nb++; |
d288c7ba | 392 | } |
80cabfad FB |
393 | switch (nb) { |
394 | case 0: | |
395 | break; | |
396 | case 1: | |
b0a21b53 | 397 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
398 | break; |
399 | case 2: | |
b0a21b53 | 400 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
401 | break; |
402 | } | |
b0a21b53 FB |
403 | val |= 0x02; /* FPU is there */ |
404 | val |= 0x04; /* PS/2 mouse installed */ | |
405 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
406 | ||
ba6c2377 | 407 | /* hard drives */ |
c0897e0c | 408 | arg.rtc_state = s; |
9139046c MA |
409 | arg.idebus[0] = idebus0; |
410 | arg.idebus[1] = idebus1; | |
c0897e0c | 411 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
412 | } |
413 | ||
4b78a802 BS |
414 | /* port 92 stuff: could be split off */ |
415 | typedef struct Port92State { | |
416 | ISADevice dev; | |
23af670e | 417 | MemoryRegion io; |
4b78a802 BS |
418 | uint8_t outport; |
419 | qemu_irq *a20_out; | |
420 | } Port92State; | |
421 | ||
93ef4192 AG |
422 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
423 | unsigned size) | |
4b78a802 BS |
424 | { |
425 | Port92State *s = opaque; | |
426 | ||
427 | DPRINTF("port92: write 0x%02x\n", val); | |
428 | s->outport = val; | |
429 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
430 | if (val & 1) { | |
431 | qemu_system_reset_request(); | |
432 | } | |
433 | } | |
434 | ||
93ef4192 AG |
435 | static uint64_t port92_read(void *opaque, hwaddr addr, |
436 | unsigned size) | |
4b78a802 BS |
437 | { |
438 | Port92State *s = opaque; | |
439 | uint32_t ret; | |
440 | ||
441 | ret = s->outport; | |
442 | DPRINTF("port92: read 0x%02x\n", ret); | |
443 | return ret; | |
444 | } | |
445 | ||
446 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
447 | { | |
448 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
449 | ||
450 | s->a20_out = a20_out; | |
451 | } | |
452 | ||
453 | static const VMStateDescription vmstate_port92_isa = { | |
454 | .name = "port92", | |
455 | .version_id = 1, | |
456 | .minimum_version_id = 1, | |
457 | .minimum_version_id_old = 1, | |
458 | .fields = (VMStateField []) { | |
459 | VMSTATE_UINT8(outport, Port92State), | |
460 | VMSTATE_END_OF_LIST() | |
461 | } | |
462 | }; | |
463 | ||
464 | static void port92_reset(DeviceState *d) | |
465 | { | |
466 | Port92State *s = container_of(d, Port92State, dev.qdev); | |
467 | ||
468 | s->outport &= ~1; | |
469 | } | |
470 | ||
23af670e | 471 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
472 | .read = port92_read, |
473 | .write = port92_write, | |
474 | .impl = { | |
475 | .min_access_size = 1, | |
476 | .max_access_size = 1, | |
477 | }, | |
478 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
479 | }; |
480 | ||
4b78a802 BS |
481 | static int port92_initfn(ISADevice *dev) |
482 | { | |
483 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
484 | ||
23af670e RH |
485 | memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
486 | isa_register_ioport(dev, &s->io, 0x92); | |
487 | ||
4b78a802 BS |
488 | s->outport = 0; |
489 | return 0; | |
490 | } | |
491 | ||
8f04ee08 AL |
492 | static void port92_class_initfn(ObjectClass *klass, void *data) |
493 | { | |
39bffca2 | 494 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
495 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
496 | ic->init = port92_initfn; | |
39bffca2 AL |
497 | dc->no_user = 1; |
498 | dc->reset = port92_reset; | |
499 | dc->vmsd = &vmstate_port92_isa; | |
8f04ee08 AL |
500 | } |
501 | ||
39bffca2 AL |
502 | static TypeInfo port92_info = { |
503 | .name = "port92", | |
504 | .parent = TYPE_ISA_DEVICE, | |
505 | .instance_size = sizeof(Port92State), | |
506 | .class_init = port92_class_initfn, | |
4b78a802 BS |
507 | }; |
508 | ||
83f7d43a | 509 | static void port92_register_types(void) |
4b78a802 | 510 | { |
39bffca2 | 511 | type_register_static(&port92_info); |
4b78a802 | 512 | } |
83f7d43a AF |
513 | |
514 | type_init(port92_register_types) | |
4b78a802 | 515 | |
956a3e6b | 516 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 517 | { |
4a8fa5dc | 518 | CPUX86State *cpu = opaque; |
e1a23744 | 519 | |
956a3e6b | 520 | /* XXX: send to all CPUs ? */ |
4b78a802 | 521 | /* XXX: add logic to handle multiple A20 line sources */ |
956a3e6b | 522 | cpu_x86_set_a20(cpu, level); |
e1a23744 FB |
523 | } |
524 | ||
80cabfad FB |
525 | /***********************************************************/ |
526 | /* Bochs BIOS debug ports */ | |
527 | ||
9596ebb7 | 528 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 529 | { |
a2f659ee FB |
530 | static const char shutdown_str[8] = "Shutdown"; |
531 | static int shutdown_index = 0; | |
3b46e624 | 532 | |
80cabfad | 533 | switch(addr) { |
a2f659ee FB |
534 | case 0x8900: |
535 | /* same as Bochs power off */ | |
536 | if (val == shutdown_str[shutdown_index]) { | |
537 | shutdown_index++; | |
538 | if (shutdown_index == 8) { | |
539 | shutdown_index = 0; | |
540 | qemu_system_shutdown_request(); | |
541 | } | |
542 | } else { | |
543 | shutdown_index = 0; | |
544 | } | |
545 | break; | |
80cabfad | 546 | |
80cabfad FB |
547 | case 0x501: |
548 | case 0x502: | |
4333979e | 549 | exit((val << 1) | 1); |
80cabfad FB |
550 | } |
551 | } | |
552 | ||
4c5b10b7 JS |
553 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
554 | { | |
8ca209ad | 555 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
556 | struct e820_entry *entry; |
557 | ||
558 | if (index >= E820_NR_ENTRIES) | |
559 | return -EBUSY; | |
8ca209ad | 560 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 561 | |
8ca209ad AW |
562 | entry->address = cpu_to_le64(address); |
563 | entry->length = cpu_to_le64(length); | |
564 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 565 | |
8ca209ad AW |
566 | e820_table.count = cpu_to_le32(index); |
567 | return index; | |
4c5b10b7 JS |
568 | } |
569 | ||
bf483392 | 570 | static void *bochs_bios_init(void) |
80cabfad | 571 | { |
3cce6243 | 572 | void *fw_cfg; |
b6f6e3d3 AL |
573 | uint8_t *smbios_table; |
574 | size_t smbios_len; | |
11c2fd3e AL |
575 | uint64_t *numa_fw_cfg; |
576 | int i, j; | |
3cce6243 | 577 | |
a2f659ee | 578 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 | 579 | |
4333979e | 580 | register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
581 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
582 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
3cce6243 BS |
583 | |
584 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 585 | |
3cce6243 | 586 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 587 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
588 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
589 | acpi_tables_len); | |
9b5b76d4 | 590 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 AL |
591 | |
592 | smbios_table = smbios_get_table(&smbios_len); | |
593 | if (smbios_table) | |
594 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
595 | smbios_table, smbios_len); | |
4c5b10b7 JS |
596 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
597 | sizeof(struct e820_table)); | |
11c2fd3e | 598 | |
40ac17cd GN |
599 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
600 | sizeof(struct hpet_fw_config)); | |
11c2fd3e AL |
601 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
602 | * of nodes, one word for each VCPU->node and one word for each node to | |
603 | * hold the amount of memory. | |
604 | */ | |
991dfefd | 605 | numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); |
11c2fd3e | 606 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 607 | for (i = 0; i < max_cpus; i++) { |
11c2fd3e | 608 | for (j = 0; j < nb_numa_nodes; j++) { |
ee785fed | 609 | if (test_bit(i, node_cpumask[j])) { |
11c2fd3e AL |
610 | numa_fw_cfg[i + 1] = cpu_to_le64(j); |
611 | break; | |
612 | } | |
613 | } | |
614 | } | |
615 | for (i = 0; i < nb_numa_nodes; i++) { | |
991dfefd | 616 | numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); |
11c2fd3e AL |
617 | } |
618 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
991dfefd | 619 | (1 + max_cpus + nb_numa_nodes) * 8); |
bf483392 AG |
620 | |
621 | return fw_cfg; | |
80cabfad FB |
622 | } |
623 | ||
642a4f96 TS |
624 | static long get_file_size(FILE *f) |
625 | { | |
626 | long where, size; | |
627 | ||
628 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
629 | ||
630 | where = ftell(f); | |
631 | fseek(f, 0, SEEK_END); | |
632 | size = ftell(f); | |
633 | fseek(f, where, SEEK_SET); | |
634 | ||
635 | return size; | |
636 | } | |
637 | ||
f16408df | 638 | static void load_linux(void *fw_cfg, |
4fc9af53 | 639 | const char *kernel_filename, |
642a4f96 | 640 | const char *initrd_filename, |
e6ade764 | 641 | const char *kernel_cmdline, |
a8170e5e | 642 | hwaddr max_ram_size) |
642a4f96 TS |
643 | { |
644 | uint16_t protocol; | |
5cea8590 | 645 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 646 | uint32_t initrd_max; |
57a46d05 | 647 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 648 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 649 | FILE *f; |
bf4e5d92 | 650 | char *vmode; |
642a4f96 TS |
651 | |
652 | /* Align to 16 bytes as a paranoia measure */ | |
653 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
654 | ||
655 | /* load the kernel header */ | |
656 | f = fopen(kernel_filename, "rb"); | |
657 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
658 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
659 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
660 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
661 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
662 | exit(1); |
663 | } | |
664 | ||
665 | /* kernel protocol version */ | |
bc4edd79 | 666 | #if 0 |
642a4f96 | 667 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 668 | #endif |
642a4f96 TS |
669 | if (ldl_p(header+0x202) == 0x53726448) |
670 | protocol = lduw_p(header+0x206); | |
f16408df AG |
671 | else { |
672 | /* This looks like a multiboot kernel. If it is, let's stop | |
673 | treating it like a Linux kernel. */ | |
52001445 AL |
674 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
675 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 676 | return; |
642a4f96 | 677 | protocol = 0; |
f16408df | 678 | } |
642a4f96 TS |
679 | |
680 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
681 | /* Low kernel */ | |
a37af289 BS |
682 | real_addr = 0x90000; |
683 | cmdline_addr = 0x9a000 - cmdline_size; | |
684 | prot_addr = 0x10000; | |
642a4f96 TS |
685 | } else if (protocol < 0x202) { |
686 | /* High but ancient kernel */ | |
a37af289 BS |
687 | real_addr = 0x90000; |
688 | cmdline_addr = 0x9a000 - cmdline_size; | |
689 | prot_addr = 0x100000; | |
642a4f96 TS |
690 | } else { |
691 | /* High and recent kernel */ | |
a37af289 BS |
692 | real_addr = 0x10000; |
693 | cmdline_addr = 0x20000; | |
694 | prot_addr = 0x100000; | |
642a4f96 TS |
695 | } |
696 | ||
bc4edd79 | 697 | #if 0 |
642a4f96 | 698 | fprintf(stderr, |
526ccb7a AZ |
699 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
700 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
701 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
702 | real_addr, |
703 | cmdline_addr, | |
704 | prot_addr); | |
bc4edd79 | 705 | #endif |
642a4f96 TS |
706 | |
707 | /* highest address for loading the initrd */ | |
708 | if (protocol >= 0x203) | |
709 | initrd_max = ldl_p(header+0x22c); | |
710 | else | |
711 | initrd_max = 0x37ffffff; | |
712 | ||
e6ade764 GC |
713 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
714 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 715 | |
57a46d05 AG |
716 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
717 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
718 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
719 | (uint8_t*)strdup(kernel_cmdline), | |
720 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
721 | |
722 | if (protocol >= 0x202) { | |
a37af289 | 723 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
724 | } else { |
725 | stw_p(header+0x20, 0xA33F); | |
726 | stw_p(header+0x22, cmdline_addr-real_addr); | |
727 | } | |
728 | ||
bf4e5d92 PT |
729 | /* handle vga= parameter */ |
730 | vmode = strstr(kernel_cmdline, "vga="); | |
731 | if (vmode) { | |
732 | unsigned int video_mode; | |
733 | /* skip "vga=" */ | |
734 | vmode += 4; | |
735 | if (!strncmp(vmode, "normal", 6)) { | |
736 | video_mode = 0xffff; | |
737 | } else if (!strncmp(vmode, "ext", 3)) { | |
738 | video_mode = 0xfffe; | |
739 | } else if (!strncmp(vmode, "ask", 3)) { | |
740 | video_mode = 0xfffd; | |
741 | } else { | |
742 | video_mode = strtol(vmode, NULL, 0); | |
743 | } | |
744 | stw_p(header+0x1fa, video_mode); | |
745 | } | |
746 | ||
642a4f96 | 747 | /* loader type */ |
5cbdb3a3 | 748 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
749 | If this code is substantially changed, you may want to consider |
750 | incrementing the revision. */ | |
751 | if (protocol >= 0x200) | |
752 | header[0x210] = 0xB0; | |
753 | ||
754 | /* heap */ | |
755 | if (protocol >= 0x201) { | |
756 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
757 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
758 | } | |
759 | ||
760 | /* load initrd */ | |
761 | if (initrd_filename) { | |
762 | if (protocol < 0x200) { | |
763 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
764 | exit(1); | |
765 | } | |
766 | ||
45a50b16 | 767 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
768 | if (initrd_size < 0) { |
769 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
770 | initrd_filename); | |
771 | exit(1); | |
772 | } | |
773 | ||
45a50b16 | 774 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 775 | |
7267c094 | 776 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
777 | load_image(initrd_filename, initrd_data); |
778 | ||
779 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
780 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
781 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 782 | |
a37af289 | 783 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
784 | stl_p(header+0x21c, initrd_size); |
785 | } | |
786 | ||
45a50b16 | 787 | /* load kernel and setup */ |
642a4f96 TS |
788 | setup_size = header[0x1f1]; |
789 | if (setup_size == 0) | |
790 | setup_size = 4; | |
642a4f96 | 791 | setup_size = (setup_size+1)*512; |
45a50b16 | 792 | kernel_size -= setup_size; |
642a4f96 | 793 | |
7267c094 AL |
794 | setup = g_malloc(setup_size); |
795 | kernel = g_malloc(kernel_size); | |
45a50b16 | 796 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
797 | if (fread(setup, 1, setup_size, f) != setup_size) { |
798 | fprintf(stderr, "fread() failed\n"); | |
799 | exit(1); | |
800 | } | |
801 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
802 | fprintf(stderr, "fread() failed\n"); | |
803 | exit(1); | |
804 | } | |
642a4f96 | 805 | fclose(f); |
45a50b16 | 806 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
807 | |
808 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
809 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
810 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
811 | ||
812 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
813 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
814 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
815 | ||
2e55e842 GN |
816 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
817 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 818 | nb_option_roms++; |
642a4f96 TS |
819 | } |
820 | ||
b41a2cd1 FB |
821 | #define NE2000_NB_MAX 6 |
822 | ||
675d6f82 BS |
823 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
824 | 0x280, 0x380 }; | |
825 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 826 | |
675d6f82 BS |
827 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
828 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 829 | |
48a18b3c | 830 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
831 | { |
832 | static int nb_ne2k = 0; | |
833 | ||
834 | if (nb_ne2k == NE2000_NB_MAX) | |
835 | return; | |
48a18b3c | 836 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 837 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
838 | nb_ne2k++; |
839 | } | |
840 | ||
92a16d7a | 841 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
842 | { |
843 | if (cpu_single_env) { | |
844 | return cpu_single_env->apic_state; | |
845 | } else { | |
846 | return NULL; | |
847 | } | |
848 | } | |
849 | ||
845773ab | 850 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 851 | { |
4a8fa5dc | 852 | CPUX86State *s = opaque; |
53b67b30 BS |
853 | |
854 | if (level) { | |
855 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
856 | } | |
857 | } | |
858 | ||
845773ab | 859 | void pc_cpus_init(const char *cpu_model) |
70166477 IY |
860 | { |
861 | int i; | |
862 | ||
863 | /* init CPUs */ | |
864 | if (cpu_model == NULL) { | |
865 | #ifdef TARGET_X86_64 | |
866 | cpu_model = "qemu64"; | |
867 | #else | |
868 | cpu_model = "qemu32"; | |
869 | #endif | |
870 | } | |
871 | ||
bdeec802 IM |
872 | for (i = 0; i < smp_cpus; i++) { |
873 | if (!cpu_x86_init(cpu_model)) { | |
874 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
875 | exit(1); | |
876 | } | |
70166477 IY |
877 | } |
878 | } | |
879 | ||
459ae5ea | 880 | void *pc_memory_init(MemoryRegion *system_memory, |
4aa63af1 | 881 | const char *kernel_filename, |
845773ab IY |
882 | const char *kernel_cmdline, |
883 | const char *initrd_filename, | |
e0e7e67b | 884 | ram_addr_t below_4g_mem_size, |
ae0a5466 | 885 | ram_addr_t above_4g_mem_size, |
4463aee6 | 886 | MemoryRegion *rom_memory, |
ae0a5466 | 887 | MemoryRegion **ram_memory) |
80cabfad | 888 | { |
cbc5b5f3 JJ |
889 | int linux_boot, i; |
890 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 891 | MemoryRegion *ram_below_4g, *ram_above_4g; |
81a204e4 | 892 | void *fw_cfg; |
d592d303 | 893 | |
80cabfad FB |
894 | linux_boot = (kernel_filename != NULL); |
895 | ||
00cb2a99 | 896 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 897 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
898 | * with older qemus that used qemu_ram_alloc(). |
899 | */ | |
7267c094 | 900 | ram = g_malloc(sizeof(*ram)); |
c5705a77 | 901 | memory_region_init_ram(ram, "pc.ram", |
00cb2a99 | 902 | below_4g_mem_size + above_4g_mem_size); |
c5705a77 | 903 | vmstate_register_ram_global(ram); |
ae0a5466 | 904 | *ram_memory = ram; |
7267c094 | 905 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
00cb2a99 AK |
906 | memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, |
907 | 0, below_4g_mem_size); | |
908 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
bbe80adf | 909 | if (above_4g_mem_size > 0) { |
7267c094 | 910 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
00cb2a99 AK |
911 | memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, |
912 | below_4g_mem_size, above_4g_mem_size); | |
913 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
914 | ram_above_4g); | |
bbe80adf | 915 | } |
82b36dc3 | 916 | |
cbc5b5f3 JJ |
917 | |
918 | /* Initialize PC system firmware */ | |
919 | pc_system_firmware_init(rom_memory); | |
00cb2a99 | 920 | |
7267c094 | 921 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
c5705a77 AK |
922 | memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); |
923 | vmstate_register_ram_global(option_rom_mr); | |
4463aee6 | 924 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
925 | PC_ROM_MIN_VGA, |
926 | option_rom_mr, | |
927 | 1); | |
f753ff16 | 928 | |
bf483392 | 929 | fw_cfg = bochs_bios_init(); |
8832cb80 | 930 | rom_set_fw(fw_cfg); |
1d108d97 | 931 | |
f753ff16 | 932 | if (linux_boot) { |
81a204e4 | 933 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
934 | } |
935 | ||
936 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 937 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 938 | } |
459ae5ea | 939 | return fw_cfg; |
3d53f5c3 IY |
940 | } |
941 | ||
845773ab IY |
942 | qemu_irq *pc_allocate_cpu_irq(void) |
943 | { | |
944 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
945 | } | |
946 | ||
48a18b3c | 947 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 948 | { |
ad6d45fa AL |
949 | DeviceState *dev = NULL; |
950 | ||
16094b75 AJ |
951 | if (pci_bus) { |
952 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
953 | dev = pcidev ? &pcidev->qdev : NULL; | |
954 | } else if (isa_bus) { | |
955 | ISADevice *isadev = isa_vga_init(isa_bus); | |
956 | dev = isadev ? &isadev->qdev : NULL; | |
765d7908 | 957 | } |
ad6d45fa | 958 | return dev; |
765d7908 IY |
959 | } |
960 | ||
4556bd8b BS |
961 | static void cpu_request_exit(void *opaque, int irq, int level) |
962 | { | |
4a8fa5dc | 963 | CPUX86State *env = cpu_single_env; |
4556bd8b BS |
964 | |
965 | if (env && level) { | |
966 | cpu_exit(env); | |
967 | } | |
968 | } | |
969 | ||
48a18b3c | 970 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 971 | ISADevice **rtc_state, |
34d4260e | 972 | ISADevice **floppy, |
1611977c | 973 | bool no_vmport) |
ffe513da IY |
974 | { |
975 | int i; | |
976 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
977 | DeviceState *hpet = NULL; |
978 | int pit_isa_irq = 0; | |
979 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 980 | qemu_irq rtc_irq = NULL; |
956a3e6b | 981 | qemu_irq *a20_line; |
c2d8d311 | 982 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 983 | qemu_irq *cpu_exit_irq; |
ffe513da IY |
984 | |
985 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
986 | ||
987 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
988 | ||
5d17c0d2 JK |
989 | /* |
990 | * Check if an HPET shall be created. | |
991 | * | |
992 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
993 | * when the HPET wants to take over. Thus we have to disable the latter. | |
994 | */ | |
995 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
ce967e2f | 996 | hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
822557eb | 997 | |
dd703b99 | 998 | if (hpet) { |
b881fbe9 JK |
999 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1000 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); | |
dd703b99 | 1001 | } |
ce967e2f JK |
1002 | pit_isa_irq = -1; |
1003 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1004 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1005 | } |
ffe513da | 1006 | } |
48a18b3c | 1007 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1008 | |
1009 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1010 | ||
c2d8d311 SS |
1011 | if (!xen_enabled()) { |
1012 | if (kvm_irqchip_in_kernel()) { | |
1013 | pit = kvm_pit_init(isa_bus, 0x40); | |
1014 | } else { | |
1015 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1016 | } | |
1017 | if (hpet) { | |
1018 | /* connect PIT to output control line of the HPET */ | |
1019 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); | |
1020 | } | |
1021 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1022 | } |
ffe513da IY |
1023 | |
1024 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1025 | if (serial_hds[i]) { | |
48a18b3c | 1026 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1027 | } |
1028 | } | |
1029 | ||
1030 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1031 | if (parallel_hds[i]) { | |
48a18b3c | 1032 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1033 | } |
1034 | } | |
1035 | ||
4b78a802 | 1036 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1037 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1038 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1039 | if (!no_vmport) { |
48a18b3c HP |
1040 | vmport_init(isa_bus); |
1041 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1042 | } else { |
1043 | vmmouse = NULL; | |
1044 | } | |
86d86414 BS |
1045 | if (vmmouse) { |
1046 | qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); | |
43f20196 | 1047 | qdev_init_nofail(&vmmouse->qdev); |
86d86414 | 1048 | } |
48a18b3c | 1049 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1050 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1051 | |
4556bd8b BS |
1052 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1053 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1054 | |
1055 | for(i = 0; i < MAX_FD; i++) { | |
1056 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1057 | } | |
48a18b3c | 1058 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1059 | } |
1060 | ||
9011a1a7 IY |
1061 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1062 | { | |
1063 | int i; | |
1064 | ||
1065 | for (i = 0; i < nb_nics; i++) { | |
1066 | NICInfo *nd = &nd_table[i]; | |
1067 | ||
1068 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1069 | pc_init_ne2k_isa(isa_bus, nd); | |
1070 | } else { | |
1071 | pci_nic_init_nofail(nd, "e1000", NULL); | |
1072 | } | |
1073 | } | |
1074 | } | |
1075 | ||
845773ab | 1076 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1077 | { |
1078 | int max_bus; | |
1079 | int bus; | |
1080 | ||
1081 | max_bus = drive_get_max_bus(IF_SCSI); | |
1082 | for (bus = 0; bus <= max_bus; bus++) { | |
1083 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1084 | } | |
1085 | } | |
a39e3564 JB |
1086 | |
1087 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1088 | { | |
1089 | DeviceState *dev; | |
1090 | SysBusDevice *d; | |
1091 | unsigned int i; | |
1092 | ||
1093 | if (kvm_irqchip_in_kernel()) { | |
1094 | dev = qdev_create(NULL, "kvm-ioapic"); | |
1095 | } else { | |
1096 | dev = qdev_create(NULL, "ioapic"); | |
1097 | } | |
1098 | if (parent_name) { | |
1099 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1100 | "ioapic", OBJECT(dev), NULL); | |
1101 | } | |
1102 | qdev_init_nofail(dev); | |
1103 | d = sysbus_from_qdev(dev); | |
1104 | sysbus_mmio_map(d, 0, 0xfec00000); | |
1105 | ||
1106 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1107 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1108 | } | |
1109 | } |