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80cabfad
FB
1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB
24#include "hw.h"
25#include "pc.h"
26#include "fdc.h"
27#include "pci.h"
18e08a55
MT
28#include "vmware_vga.h"
29#include "usb-uhci.h"
30#include "usb-ohci.h"
31#include "prep_pci.h"
32#include "apb_pci.h"
87ecb68b
PB
33#include "block.h"
34#include "sysemu.h"
35#include "audio/audio.h"
36#include "net.h"
37#include "smbus.h"
38#include "boards.h"
376253ec 39#include "monitor.h"
3cce6243 40#include "fw_cfg.h"
16b29ae1 41#include "hpet_emul.h"
9dd986cc 42#include "watchdog.h"
b6f6e3d3 43#include "smbios.h"
ec82026c 44#include "ide.h"
ca20cf32
BS
45#include "loader.h"
46#include "elf.h"
80cabfad 47
b41a2cd1
FB
48/* output Bochs bios info messages */
49//#define DEBUG_BIOS
50
f16408df
AG
51/* Show multiboot debug output */
52//#define DEBUG_MULTIBOOT
53
80cabfad 54#define BIOS_FILENAME "bios.bin"
80cabfad 55
7fb4fdcf
AZ
56#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
57
a80274c3
PB
58/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
59#define ACPI_DATA_SIZE 0x10000
3cce6243 60#define BIOS_CFG_IOPORT 0x510
8a92ea2f 61#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
b6f6e3d3 62#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
6b35e7bf 63#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
80cabfad 64
e4bcb14c
TS
65#define MAX_IDE_BUS 2
66
c227f099 67static fdctrl_t *floppy_controller;
b0a21b53 68static RTCState *rtc_state;
ec844b96 69static PITState *pit;
0a3bacf3 70static PCII440FXState *i440fx_state;
80cabfad 71
1452411b
AK
72typedef struct isa_irq_state {
73 qemu_irq *i8259;
1632dc6a 74 qemu_irq *ioapic;
1452411b
AK
75} IsaIrqState;
76
77static void isa_irq_handler(void *opaque, int n, int level)
78{
79 IsaIrqState *isa = (IsaIrqState *)opaque;
80
1632dc6a
AK
81 if (n < 16) {
82 qemu_set_irq(isa->i8259[n], level);
83 }
2c8d9340
GH
84 if (isa->ioapic)
85 qemu_set_irq(isa->ioapic[n], level);
1632dc6a 86};
1452411b 87
b41a2cd1 88static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
80cabfad
FB
89{
90}
91
f929aad6 92/* MSDOS compatibility mode FPU exception support */
d537cf6c 93static qemu_irq ferr_irq;
f929aad6
FB
94/* XXX: add IGNNE support */
95void cpu_set_ferr(CPUX86State *s)
96{
d537cf6c 97 qemu_irq_raise(ferr_irq);
f929aad6
FB
98}
99
100static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
101{
d537cf6c 102 qemu_irq_lower(ferr_irq);
f929aad6
FB
103}
104
28ab0e2e 105/* TSC handling */
28ab0e2e
FB
106uint64_t cpu_get_tsc(CPUX86State *env)
107{
4a1418e0 108 return cpu_get_ticks();
28ab0e2e
FB
109}
110
a5954d5c
FB
111/* SMM support */
112void cpu_smm_update(CPUState *env)
113{
114 if (i440fx_state && env == first_cpu)
115 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
116}
117
118
3de388f6
FB
119/* IRQ handling */
120int cpu_get_pic_interrupt(CPUState *env)
121{
122 int intno;
123
3de388f6
FB
124 intno = apic_get_interrupt(env);
125 if (intno >= 0) {
126 /* set irq request if a PIC irq is still pending */
127 /* XXX: improve that */
5fafdf24 128 pic_update_irq(isa_pic);
3de388f6
FB
129 return intno;
130 }
3de388f6 131 /* read the irq from the PIC */
0e21e12b
TS
132 if (!apic_accept_pic_intr(env))
133 return -1;
134
3de388f6
FB
135 intno = pic_read_irq(isa_pic);
136 return intno;
137}
138
d537cf6c 139static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 140{
a5b38b51
AJ
141 CPUState *env = first_cpu;
142
d5529471
AJ
143 if (env->apic_state) {
144 while (env) {
145 if (apic_accept_pic_intr(env))
1a7de94a 146 apic_deliver_pic_intr(env, level);
d5529471
AJ
147 env = env->next_cpu;
148 }
149 } else {
b614106a
AJ
150 if (level)
151 cpu_interrupt(env, CPU_INTERRUPT_HARD);
152 else
153 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
a5b38b51 154 }
3de388f6
FB
155}
156
b0a21b53
FB
157/* PC cmos mappings */
158
80cabfad
FB
159#define REG_EQUIPMENT_BYTE 0x14
160
777428f2
FB
161static int cmos_get_fd_drive_type(int fd0)
162{
163 int val;
164
165 switch (fd0) {
166 case 0:
167 /* 1.44 Mb 3"5 drive */
168 val = 4;
169 break;
170 case 1:
171 /* 2.88 Mb 3"5 drive */
172 val = 5;
173 break;
174 case 2:
175 /* 1.2 Mb 5"5 drive */
176 val = 2;
177 break;
178 default:
179 val = 0;
180 break;
181 }
182 return val;
183}
184
5fafdf24 185static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
ba6c2377
FB
186{
187 RTCState *s = rtc_state;
188 int cylinders, heads, sectors;
189 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
190 rtc_set_memory(s, type_ofs, 47);
191 rtc_set_memory(s, info_ofs, cylinders);
192 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
193 rtc_set_memory(s, info_ofs + 2, heads);
194 rtc_set_memory(s, info_ofs + 3, 0xff);
195 rtc_set_memory(s, info_ofs + 4, 0xff);
196 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
197 rtc_set_memory(s, info_ofs + 6, cylinders);
198 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
199 rtc_set_memory(s, info_ofs + 8, sectors);
200}
201
6ac0e82d
AZ
202/* convert boot_device letter to something recognizable by the bios */
203static int boot_device2nibble(char boot_device)
204{
205 switch(boot_device) {
206 case 'a':
207 case 'b':
208 return 0x01; /* floppy boot */
209 case 'c':
210 return 0x02; /* hard drive boot */
211 case 'd':
212 return 0x03; /* CD-ROM boot */
213 case 'n':
214 return 0x04; /* Network boot */
215 }
216 return 0;
217}
218
0ecdffbb
AJ
219/* copy/pasted from cmos_init, should be made a general function
220 and used there as well */
3b4366de 221static int pc_boot_set(void *opaque, const char *boot_device)
0ecdffbb 222{
376253ec 223 Monitor *mon = cur_mon;
0ecdffbb 224#define PC_MAX_BOOT_DEVICES 3
3b4366de 225 RTCState *s = (RTCState *)opaque;
0ecdffbb
AJ
226 int nbds, bds[3] = { 0, };
227 int i;
228
229 nbds = strlen(boot_device);
230 if (nbds > PC_MAX_BOOT_DEVICES) {
376253ec 231 monitor_printf(mon, "Too many boot devices for PC\n");
0ecdffbb
AJ
232 return(1);
233 }
234 for (i = 0; i < nbds; i++) {
235 bds[i] = boot_device2nibble(boot_device[i]);
236 if (bds[i] == 0) {
376253ec
AL
237 monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
238 boot_device[i]);
0ecdffbb
AJ
239 return(1);
240 }
241 }
242 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
243 rtc_set_memory(s, 0x38, (bds[2] << 4));
244 return(0);
245}
246
ba6c2377 247/* hd_table must contain 4 block drivers */
c227f099 248static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
f455e98c 249 const char *boot_device, DriveInfo **hd_table)
80cabfad 250{
b0a21b53 251 RTCState *s = rtc_state;
28c5af54 252 int nbds, bds[3] = { 0, };
80cabfad 253 int val;
b41a2cd1 254 int fd0, fd1, nb;
ba6c2377 255 int i;
b0a21b53 256
b0a21b53 257 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB
258
259 /* memory size */
333190eb
FB
260 val = 640; /* base memory in K */
261 rtc_set_memory(s, 0x15, val);
262 rtc_set_memory(s, 0x16, val >> 8);
263
80cabfad
FB
264 val = (ram_size / 1024) - 1024;
265 if (val > 65535)
266 val = 65535;
b0a21b53
FB
267 rtc_set_memory(s, 0x17, val);
268 rtc_set_memory(s, 0x18, val >> 8);
269 rtc_set_memory(s, 0x30, val);
270 rtc_set_memory(s, 0x31, val >> 8);
80cabfad 271
00f82b8a
AJ
272 if (above_4g_mem_size) {
273 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
274 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
275 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
276 }
277
9da98861
FB
278 if (ram_size > (16 * 1024 * 1024))
279 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
280 else
281 val = 0;
80cabfad
FB
282 if (val > 65535)
283 val = 65535;
b0a21b53
FB
284 rtc_set_memory(s, 0x34, val);
285 rtc_set_memory(s, 0x35, val >> 8);
3b46e624 286
298e01b6
AJ
287 /* set the number of CPU */
288 rtc_set_memory(s, 0x5f, smp_cpus - 1);
289
6ac0e82d 290 /* set boot devices, and disable floppy signature check if requested */
28c5af54
JM
291#define PC_MAX_BOOT_DEVICES 3
292 nbds = strlen(boot_device);
293 if (nbds > PC_MAX_BOOT_DEVICES) {
294 fprintf(stderr, "Too many boot devices for PC\n");
295 exit(1);
296 }
297 for (i = 0; i < nbds; i++) {
298 bds[i] = boot_device2nibble(boot_device[i]);
299 if (bds[i] == 0) {
300 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
301 boot_device[i]);
302 exit(1);
303 }
304 }
305 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
306 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
80cabfad 307
b41a2cd1
FB
308 /* floppy type */
309
baca51fa
FB
310 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
311 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
80cabfad 312
777428f2 313 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
b0a21b53 314 rtc_set_memory(s, 0x10, val);
3b46e624 315
b0a21b53 316 val = 0;
b41a2cd1 317 nb = 0;
80cabfad
FB
318 if (fd0 < 3)
319 nb++;
320 if (fd1 < 3)
321 nb++;
322 switch (nb) {
323 case 0:
324 break;
325 case 1:
b0a21b53 326 val |= 0x01; /* 1 drive, ready for boot */
80cabfad
FB
327 break;
328 case 2:
b0a21b53 329 val |= 0x41; /* 2 drives, ready for boot */
80cabfad
FB
330 break;
331 }
b0a21b53
FB
332 val |= 0x02; /* FPU is there */
333 val |= 0x04; /* PS/2 mouse installed */
334 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
335
ba6c2377
FB
336 /* hard drives */
337
338 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
339 if (hd_table[0])
f455e98c 340 cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
5fafdf24 341 if (hd_table[1])
f455e98c 342 cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
ba6c2377
FB
343
344 val = 0;
40b6ecc6 345 for (i = 0; i < 4; i++) {
ba6c2377 346 if (hd_table[i]) {
46d4767d
FB
347 int cylinders, heads, sectors, translation;
348 /* NOTE: bdrv_get_geometry_hint() returns the physical
349 geometry. It is always such that: 1 <= sects <= 63, 1
350 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
351 geometry can be different if a translation is done. */
f455e98c 352 translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
46d4767d 353 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
f455e98c 354 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
46d4767d
FB
355 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
356 /* No translation. */
357 translation = 0;
358 } else {
359 /* LBA translation. */
360 translation = 1;
361 }
40b6ecc6 362 } else {
46d4767d 363 translation--;
ba6c2377 364 }
ba6c2377
FB
365 val |= translation << (i * 2);
366 }
40b6ecc6 367 }
ba6c2377 368 rtc_set_memory(s, 0x39, val);
80cabfad
FB
369}
370
59b8ad81
FB
371void ioport_set_a20(int enable)
372{
373 /* XXX: send to all CPUs ? */
374 cpu_x86_set_a20(first_cpu, enable);
375}
376
377int ioport_get_a20(void)
378{
379 return ((first_cpu->a20_mask >> 20) & 1);
380}
381
e1a23744
FB
382static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
383{
59b8ad81 384 ioport_set_a20((val >> 1) & 1);
e1a23744
FB
385 /* XXX: bit 0 is fast reset */
386}
387
388static uint32_t ioport92_read(void *opaque, uint32_t addr)
389{
59b8ad81 390 return ioport_get_a20() << 1;
e1a23744
FB
391}
392
80cabfad
FB
393/***********************************************************/
394/* Bochs BIOS debug ports */
395
9596ebb7 396static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad 397{
a2f659ee
FB
398 static const char shutdown_str[8] = "Shutdown";
399 static int shutdown_index = 0;
3b46e624 400
80cabfad
FB
401 switch(addr) {
402 /* Bochs BIOS messages */
403 case 0x400:
404 case 0x401:
405 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
406 exit(1);
407 case 0x402:
408 case 0x403:
409#ifdef DEBUG_BIOS
410 fprintf(stderr, "%c", val);
411#endif
412 break;
a2f659ee
FB
413 case 0x8900:
414 /* same as Bochs power off */
415 if (val == shutdown_str[shutdown_index]) {
416 shutdown_index++;
417 if (shutdown_index == 8) {
418 shutdown_index = 0;
419 qemu_system_shutdown_request();
420 }
421 } else {
422 shutdown_index = 0;
423 }
424 break;
80cabfad
FB
425
426 /* LGPL'ed VGA BIOS messages */
427 case 0x501:
428 case 0x502:
429 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
430 exit(1);
431 case 0x500:
432 case 0x503:
433#ifdef DEBUG_BIOS
434 fprintf(stderr, "%c", val);
435#endif
436 break;
437 }
438}
439
bf483392 440static void *bochs_bios_init(void)
80cabfad 441{
3cce6243 442 void *fw_cfg;
b6f6e3d3
AL
443 uint8_t *smbios_table;
444 size_t smbios_len;
11c2fd3e
AL
445 uint64_t *numa_fw_cfg;
446 int i, j;
3cce6243 447
b41a2cd1
FB
448 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
449 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
450 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
451 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
a2f659ee 452 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
b41a2cd1
FB
453
454 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
455 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
456 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
457 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
3cce6243
BS
458
459 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
bf483392 460
3cce6243 461 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
905fdcb5 462 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
80deece2
BS
463 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
464 acpi_tables_len);
6b35e7bf 465 fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
b6f6e3d3
AL
466
467 smbios_table = smbios_get_table(&smbios_len);
468 if (smbios_table)
469 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
470 smbios_table, smbios_len);
11c2fd3e
AL
471
472 /* allocate memory for the NUMA channel: one (64bit) word for the number
473 * of nodes, one word for each VCPU->node and one word for each node to
474 * hold the amount of memory.
475 */
476 numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
477 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
478 for (i = 0; i < smp_cpus; i++) {
479 for (j = 0; j < nb_numa_nodes; j++) {
480 if (node_cpumask[j] & (1 << i)) {
481 numa_fw_cfg[i + 1] = cpu_to_le64(j);
482 break;
483 }
484 }
485 }
486 for (i = 0; i < nb_numa_nodes; i++) {
487 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
488 }
489 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
490 (1 + smp_cpus + nb_numa_nodes) * 8);
bf483392
AG
491
492 return fw_cfg;
80cabfad
FB
493}
494
642a4f96
TS
495static long get_file_size(FILE *f)
496{
497 long where, size;
498
499 /* XXX: on Unix systems, using fstat() probably makes more sense */
500
501 where = ftell(f);
502 fseek(f, 0, SEEK_END);
503 size = ftell(f);
504 fseek(f, where, SEEK_SET);
505
506 return size;
507}
508
f16408df
AG
509#define MULTIBOOT_STRUCT_ADDR 0x9000
510
511#if MULTIBOOT_STRUCT_ADDR > 0xf0000
512#error multiboot struct needs to fit in 16 bit real mode
513#endif
514
515static int load_multiboot(void *fw_cfg,
516 FILE *f,
517 const char *kernel_filename,
518 const char *initrd_filename,
519 const char *kernel_cmdline,
520 uint8_t *header)
521{
45a50b16 522 int i, is_multiboot = 0;
f16408df
AG
523 uint32_t flags = 0;
524 uint32_t mh_entry_addr;
525 uint32_t mh_load_addr;
526 uint32_t mb_kernel_size;
527 uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
528 uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
f16408df 529 uint32_t mb_mod_end;
45a50b16
GH
530 uint8_t bootinfo[0x500];
531 uint32_t cmdline = 0x200;
77873196
AG
532 uint8_t *mb_kernel_data;
533 uint8_t *mb_bootinfo_data;
f16408df
AG
534
535 /* Ok, let's see if it is a multiboot image.
536 The header is 12x32bit long, so the latest entry may be 8192 - 48. */
537 for (i = 0; i < (8192 - 48); i += 4) {
538 if (ldl_p(header+i) == 0x1BADB002) {
539 uint32_t checksum = ldl_p(header+i+8);
540 flags = ldl_p(header+i+4);
541 checksum += flags;
542 checksum += (uint32_t)0x1BADB002;
543 if (!checksum) {
544 is_multiboot = 1;
545 break;
546 }
547 }
548 }
549
550 if (!is_multiboot)
551 return 0; /* no multiboot */
552
553#ifdef DEBUG_MULTIBOOT
554 fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
555#endif
45a50b16 556 memset(bootinfo, 0, sizeof(bootinfo));
f16408df
AG
557
558 if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
559 fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
560 }
561 if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
562 uint64_t elf_entry;
092493be 563 uint64_t elf_low, elf_high;
f16408df
AG
564 int kernel_size;
565 fclose(f);
092493be 566 kernel_size = load_elf(kernel_filename, 0, &elf_entry, &elf_low, &elf_high,
ca20cf32 567 0, ELF_MACHINE, 0);
f16408df
AG
568 if (kernel_size < 0) {
569 fprintf(stderr, "Error while loading elf kernel\n");
570 exit(1);
571 }
092493be
KW
572 mh_load_addr = elf_low;
573 mb_kernel_size = elf_high - elf_low;
574 mh_entry_addr = elf_entry;
f16408df 575
77873196 576 mb_kernel_data = qemu_malloc(mb_kernel_size);
092493be 577 if (rom_copy(mb_kernel_data, mh_load_addr, mb_kernel_size) != mb_kernel_size) {
77873196
AG
578 fprintf(stderr, "Error while fetching elf kernel from rom\n");
579 exit(1);
580 }
581
f16408df
AG
582#ifdef DEBUG_MULTIBOOT
583 fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
584 mb_kernel_size, (size_t)mh_entry_addr);
585#endif
586 } else {
587 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
588 uint32_t mh_header_addr = ldl_p(header+i+12);
589 mh_load_addr = ldl_p(header+i+16);
590#ifdef DEBUG_MULTIBOOT
591 uint32_t mh_load_end_addr = ldl_p(header+i+20);
592 uint32_t mh_bss_end_addr = ldl_p(header+i+24);
593#endif
594 uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
595
596 mh_entry_addr = ldl_p(header+i+28);
597 mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
598
599 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
600 uint32_t mh_mode_type = ldl_p(header+i+32);
601 uint32_t mh_width = ldl_p(header+i+36);
602 uint32_t mh_height = ldl_p(header+i+40);
603 uint32_t mh_depth = ldl_p(header+i+44); */
604
605#ifdef DEBUG_MULTIBOOT
606 fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
607 fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
608 fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
609 fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
f16408df
AG
610 fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
611 mb_kernel_size, mh_load_addr);
612#endif
613
77873196 614 mb_kernel_data = qemu_malloc(mb_kernel_size);
45a50b16 615 fseek(f, mb_kernel_text_offset, SEEK_SET);
77873196 616 fread(mb_kernel_data, 1, mb_kernel_size, f);
f16408df
AG
617 fclose(f);
618 }
619
620 /* blob size is only the kernel for now */
621 mb_mod_end = mh_load_addr + mb_kernel_size;
622
623 /* load modules */
45a50b16 624 stl_p(bootinfo + 20, 0x0); /* mods_count */
f16408df 625 if (initrd_filename) {
45a50b16
GH
626 uint32_t mb_mod_info = 0x100;
627 uint32_t mb_mod_cmdline = 0x300;
f16408df
AG
628 uint32_t mb_mod_start = mh_load_addr;
629 uint32_t mb_mod_length = mb_kernel_size;
630 char *next_initrd;
631 char *next_space;
632 int mb_mod_count = 0;
633
634 do {
bf854d65
AL
635 if (mb_mod_info + 16 > mb_mod_cmdline) {
636 printf("WARNING: Too many modules loaded, aborting.\n");
637 break;
638 }
5f370b14 639
f16408df
AG
640 next_initrd = strchr(initrd_filename, ',');
641 if (next_initrd)
642 *next_initrd = '\0';
643 /* if a space comes after the module filename, treat everything
644 after that as parameters */
45a50b16
GH
645 pstrcpy((char*)bootinfo + mb_mod_cmdline,
646 sizeof(bootinfo) - mb_mod_cmdline,
647 initrd_filename);
3f3d583e 648 stl_p(bootinfo + mb_mod_info + 8, mb_bootinfo + mb_mod_cmdline); /* string */
f16408df 649 mb_mod_cmdline += strlen(initrd_filename) + 1;
bf854d65 650 if (mb_mod_cmdline > sizeof(bootinfo)) {
45a50b16 651 mb_mod_cmdline = sizeof(bootinfo);
bf854d65
AL
652 printf("WARNING: Too many module cmdlines loaded, aborting.\n");
653 break;
654 }
f16408df
AG
655 if ((next_space = strchr(initrd_filename, ' ')))
656 *next_space = '\0';
657#ifdef DEBUG_MULTIBOOT
82663ee2 658 printf("multiboot loading module: %s\n", initrd_filename);
f16408df 659#endif
45a50b16
GH
660 mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
661 & (TARGET_PAGE_MASK);
662 mb_mod_length = get_image_size(initrd_filename);
663 if (mb_mod_length < 0) {
664 fprintf(stderr, "failed to get %s image size\n", initrd_filename);
665 exit(1);
666 }
667 mb_mod_end = mb_mod_start + mb_mod_length;
45a50b16 668 mb_mod_count++;
77873196
AG
669
670 /* append module data at the end of last module */
671 mb_kernel_data = qemu_realloc(mb_kernel_data,
53ea95de 672 mb_mod_end - mh_load_addr);
77873196
AG
673 load_image(initrd_filename,
674 mb_kernel_data + mb_mod_start - mh_load_addr);
675
45a50b16
GH
676 stl_p(bootinfo + mb_mod_info + 0, mb_mod_start);
677 stl_p(bootinfo + mb_mod_info + 4, mb_mod_start + mb_mod_length);
678 stl_p(bootinfo + mb_mod_info + 12, 0x0); /* reserved */
f16408df 679#ifdef DEBUG_MULTIBOOT
45a50b16
GH
680 printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
681 mb_mod_start + mb_mod_length);
f16408df 682#endif
f16408df
AG
683 initrd_filename = next_initrd+1;
684 mb_mod_info += 16;
685 } while (next_initrd);
45a50b16
GH
686 stl_p(bootinfo + 20, mb_mod_count); /* mods_count */
687 stl_p(bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
f16408df
AG
688 }
689
f16408df 690 /* Commandline support */
45a50b16
GH
691 stl_p(bootinfo + 16, mb_bootinfo + cmdline);
692 snprintf((char*)bootinfo + cmdline, 0x100, "%s %s",
693 kernel_filename, kernel_cmdline);
f16408df
AG
694
695 /* the kernel is where we want it to be now */
f16408df
AG
696#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
697#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
698#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
699#define MULTIBOOT_FLAGS_MODULES (1 << 3)
700#define MULTIBOOT_FLAGS_MMAP (1 << 6)
45a50b16
GH
701 stl_p(bootinfo, MULTIBOOT_FLAGS_MEMORY
702 | MULTIBOOT_FLAGS_BOOT_DEVICE
703 | MULTIBOOT_FLAGS_CMDLINE
704 | MULTIBOOT_FLAGS_MODULES
705 | MULTIBOOT_FLAGS_MMAP);
706 stl_p(bootinfo + 4, 640); /* mem_lower */
707 stl_p(bootinfo + 8, ram_size / 1024); /* mem_upper */
708 stl_p(bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
709 stl_p(bootinfo + 48, mmap_addr); /* mmap_addr */
f16408df
AG
710
711#ifdef DEBUG_MULTIBOOT
712 fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
713#endif
714
77873196
AG
715 /* save bootinfo off the stack */
716 mb_bootinfo_data = qemu_malloc(sizeof(bootinfo));
717 memcpy(mb_bootinfo_data, bootinfo, sizeof(bootinfo));
718
f16408df 719 /* Pass variables to option rom */
77873196
AG
720 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, mh_entry_addr);
721 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
722 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, mb_mod_end - mh_load_addr);
723 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, mb_kernel_data,
724 mb_mod_end - mh_load_addr);
f16408df 725
77873196
AG
726 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
727 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, sizeof(bootinfo));
728 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, mb_bootinfo_data,
729 sizeof(bootinfo));
f16408df
AG
730
731 option_rom[nb_option_roms] = "multiboot.bin";
732 nb_option_roms++;
733
734 return 1; /* yes, we are multiboot */
735}
736
737static void load_linux(void *fw_cfg,
4fc9af53 738 const char *kernel_filename,
642a4f96 739 const char *initrd_filename,
e6ade764 740 const char *kernel_cmdline,
45a50b16 741 target_phys_addr_t max_ram_size)
642a4f96
TS
742{
743 uint16_t protocol;
5cea8590 744 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
642a4f96 745 uint32_t initrd_max;
57a46d05 746 uint8_t header[8192], *setup, *kernel, *initrd_data;
c227f099 747 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 748 FILE *f;
bf4e5d92 749 char *vmode;
642a4f96
TS
750
751 /* Align to 16 bytes as a paranoia measure */
752 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
753
754 /* load the kernel header */
755 f = fopen(kernel_filename, "rb");
756 if (!f || !(kernel_size = get_file_size(f)) ||
f16408df
AG
757 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
758 MIN(ARRAY_SIZE(header), kernel_size)) {
850810d0
JF
759 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
760 kernel_filename, strerror(errno));
642a4f96
TS
761 exit(1);
762 }
763
764 /* kernel protocol version */
bc4edd79 765#if 0
642a4f96 766 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 767#endif
642a4f96
TS
768 if (ldl_p(header+0x202) == 0x53726448)
769 protocol = lduw_p(header+0x206);
f16408df
AG
770 else {
771 /* This looks like a multiboot kernel. If it is, let's stop
772 treating it like a Linux kernel. */
773 if (load_multiboot(fw_cfg, f, kernel_filename,
774 initrd_filename, kernel_cmdline, header))
82663ee2 775 return;
642a4f96 776 protocol = 0;
f16408df 777 }
642a4f96
TS
778
779 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
780 /* Low kernel */
a37af289
BS
781 real_addr = 0x90000;
782 cmdline_addr = 0x9a000 - cmdline_size;
783 prot_addr = 0x10000;
642a4f96
TS
784 } else if (protocol < 0x202) {
785 /* High but ancient kernel */
a37af289
BS
786 real_addr = 0x90000;
787 cmdline_addr = 0x9a000 - cmdline_size;
788 prot_addr = 0x100000;
642a4f96
TS
789 } else {
790 /* High and recent kernel */
a37af289
BS
791 real_addr = 0x10000;
792 cmdline_addr = 0x20000;
793 prot_addr = 0x100000;
642a4f96
TS
794 }
795
bc4edd79 796#if 0
642a4f96 797 fprintf(stderr,
526ccb7a
AZ
798 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
799 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
800 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
a37af289
BS
801 real_addr,
802 cmdline_addr,
803 prot_addr);
bc4edd79 804#endif
642a4f96
TS
805
806 /* highest address for loading the initrd */
807 if (protocol >= 0x203)
808 initrd_max = ldl_p(header+0x22c);
809 else
810 initrd_max = 0x37ffffff;
811
e6ade764
GC
812 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
813 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
642a4f96 814
57a46d05
AG
815 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
816 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
817 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
818 (uint8_t*)strdup(kernel_cmdline),
819 strlen(kernel_cmdline)+1);
642a4f96
TS
820
821 if (protocol >= 0x202) {
a37af289 822 stl_p(header+0x228, cmdline_addr);
642a4f96
TS
823 } else {
824 stw_p(header+0x20, 0xA33F);
825 stw_p(header+0x22, cmdline_addr-real_addr);
826 }
827
bf4e5d92
PT
828 /* handle vga= parameter */
829 vmode = strstr(kernel_cmdline, "vga=");
830 if (vmode) {
831 unsigned int video_mode;
832 /* skip "vga=" */
833 vmode += 4;
834 if (!strncmp(vmode, "normal", 6)) {
835 video_mode = 0xffff;
836 } else if (!strncmp(vmode, "ext", 3)) {
837 video_mode = 0xfffe;
838 } else if (!strncmp(vmode, "ask", 3)) {
839 video_mode = 0xfffd;
840 } else {
841 video_mode = strtol(vmode, NULL, 0);
842 }
843 stw_p(header+0x1fa, video_mode);
844 }
845
642a4f96
TS
846 /* loader type */
847 /* High nybble = B reserved for Qemu; low nybble is revision number.
848 If this code is substantially changed, you may want to consider
849 incrementing the revision. */
850 if (protocol >= 0x200)
851 header[0x210] = 0xB0;
852
853 /* heap */
854 if (protocol >= 0x201) {
855 header[0x211] |= 0x80; /* CAN_USE_HEAP */
856 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
857 }
858
859 /* load initrd */
860 if (initrd_filename) {
861 if (protocol < 0x200) {
862 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
863 exit(1);
864 }
865
45a50b16
GH
866 initrd_size = get_image_size(initrd_filename);
867 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05
AG
868
869 initrd_data = qemu_malloc(initrd_size);
870 load_image(initrd_filename, initrd_data);
871
872 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
873 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
874 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 875
a37af289 876 stl_p(header+0x218, initrd_addr);
642a4f96
TS
877 stl_p(header+0x21c, initrd_size);
878 }
879
45a50b16 880 /* load kernel and setup */
642a4f96
TS
881 setup_size = header[0x1f1];
882 if (setup_size == 0)
883 setup_size = 4;
642a4f96 884 setup_size = (setup_size+1)*512;
45a50b16 885 kernel_size -= setup_size;
642a4f96 886
45a50b16
GH
887 setup = qemu_malloc(setup_size);
888 kernel = qemu_malloc(kernel_size);
889 fseek(f, 0, SEEK_SET);
890 fread(setup, 1, setup_size, f);
891 fread(kernel, 1, kernel_size, f);
642a4f96 892 fclose(f);
45a50b16 893 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG
894
895 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
896 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
897 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
898
899 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
900 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
901 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
902
903 option_rom[nb_option_roms] = "linuxboot.bin";
904 nb_option_roms++;
642a4f96
TS
905}
906
b41a2cd1
FB
907static const int ide_iobase[2] = { 0x1f0, 0x170 };
908static const int ide_iobase2[2] = { 0x3f6, 0x376 };
909static const int ide_irq[2] = { 14, 15 };
910
911#define NE2000_NB_MAX 6
912
675d6f82
BS
913static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
914 0x280, 0x380 };
915static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 916
675d6f82
BS
917static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
918static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
6508fe59 919
6a36d84e 920#ifdef HAS_AUDIO
d537cf6c 921static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
6a36d84e
FB
922{
923 struct soundhw *c;
6a36d84e 924
3a8bae3e 925 for (c = soundhw; c->name; ++c) {
926 if (c->enabled) {
927 if (c->isa) {
928 c->init.init_isa(pic);
929 } else {
930 if (pci_bus) {
931 c->init.init_pci(pci_bus);
6a36d84e
FB
932 }
933 }
934 }
935 }
936}
937#endif
938
3a38d437 939static void pc_init_ne2k_isa(NICInfo *nd)
a41b2ff2
PB
940{
941 static int nb_ne2k = 0;
942
943 if (nb_ne2k == NE2000_NB_MAX)
944 return;
3a38d437 945 isa_ne2000_init(ne2000_io[nb_ne2k],
9453c5bc 946 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB
947 nb_ne2k++;
948}
949
678e12cc
GN
950int cpu_is_bsp(CPUState *env)
951{
82663ee2 952 return env->cpuid_apic_id == 0;
678e12cc
GN
953}
954
3a31f36a
JK
955static CPUState *pc_new_cpu(const char *cpu_model)
956{
957 CPUState *env;
958
959 env = cpu_init(cpu_model);
960 if (!env) {
961 fprintf(stderr, "Unable to find x86 CPU definition\n");
962 exit(1);
963 }
964 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
965 env->cpuid_apic_id = env->cpu_index;
966 /* APIC reset callback resets cpu */
967 apic_init(env);
968 } else {
969 qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
970 }
971 return env;
972}
973
80cabfad 974/* PC hardware initialisation */
c227f099 975static void pc_init1(ram_addr_t ram_size,
3023f332 976 const char *boot_device,
e8b2a1c6
MM
977 const char *kernel_filename,
978 const char *kernel_cmdline,
3dbbdc25 979 const char *initrd_filename,
e8b2a1c6 980 const char *cpu_model,
caea79a9 981 int pci_enabled)
80cabfad 982{
5cea8590 983 char *filename;
642a4f96 984 int ret, linux_boot, i;
c227f099
AL
985 ram_addr_t ram_addr, bios_offset, option_rom_offset;
986 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
45a50b16 987 int bios_size, isa_bios_size;
46e50e9d 988 PCIBus *pci_bus;
b3999638 989 ISADevice *isa_dev;
5c3ff3a7 990 int piix3_devfn = -1;
59b8ad81 991 CPUState *env;
d537cf6c 992 qemu_irq *cpu_irq;
1452411b 993 qemu_irq *isa_irq;
d537cf6c 994 qemu_irq *i8259;
1452411b 995 IsaIrqState *isa_irq_state;
f455e98c 996 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
fd8014e1 997 DriveInfo *fd[MAX_FD];
bf483392 998 void *fw_cfg;
d592d303 999
00f82b8a
AJ
1000 if (ram_size >= 0xe0000000 ) {
1001 above_4g_mem_size = ram_size - 0xe0000000;
1002 below_4g_mem_size = 0xe0000000;
1003 } else {
1004 below_4g_mem_size = ram_size;
1005 }
1006
80cabfad
FB
1007 linux_boot = (kernel_filename != NULL);
1008
59b8ad81 1009 /* init CPUs */
a049de61
FB
1010 if (cpu_model == NULL) {
1011#ifdef TARGET_X86_64
1012 cpu_model = "qemu64";
1013#else
1014 cpu_model = "qemu32";
1015#endif
1016 }
3a31f36a
JK
1017
1018 for (i = 0; i < smp_cpus; i++) {
1019 env = pc_new_cpu(cpu_model);
59b8ad81
FB
1020 }
1021
26fb5e48
AJ
1022 vmport_init();
1023
80cabfad 1024 /* allocate RAM */
82b36dc3
AL
1025 ram_addr = qemu_ram_alloc(0xa0000);
1026 cpu_register_physical_memory(0, 0xa0000, ram_addr);
1027
1028 /* Allocate, even though we won't register, so we don't break the
1029 * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1030 * and some bios areas, which will be registered later
1031 */
1032 ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1033 ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1034 cpu_register_physical_memory(0x100000,
1035 below_4g_mem_size - 0x100000,
1036 ram_addr);
00f82b8a
AJ
1037
1038 /* above 4giga memory allocation */
1039 if (above_4g_mem_size > 0) {
8a637d44
PB
1040#if TARGET_PHYS_ADDR_BITS == 32
1041 hw_error("To much RAM for 32-bit physical address");
1042#else
82b36dc3
AL
1043 ram_addr = qemu_ram_alloc(above_4g_mem_size);
1044 cpu_register_physical_memory(0x100000000ULL,
526ccb7a 1045 above_4g_mem_size,
82b36dc3 1046 ram_addr);
8a637d44 1047#endif
00f82b8a 1048 }
80cabfad 1049
82b36dc3 1050
970ac5a3 1051 /* BIOS load */
1192dad8
JM
1052 if (bios_name == NULL)
1053 bios_name = BIOS_FILENAME;
5cea8590
PB
1054 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1055 if (filename) {
1056 bios_size = get_image_size(filename);
1057 } else {
1058 bios_size = -1;
1059 }
5fafdf24 1060 if (bios_size <= 0 ||
970ac5a3 1061 (bios_size % 65536) != 0) {
7587cf44
FB
1062 goto bios_error;
1063 }
970ac5a3 1064 bios_offset = qemu_ram_alloc(bios_size);
51edd4e6
GH
1065 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
1066 if (ret != 0) {
7587cf44 1067 bios_error:
5cea8590 1068 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
80cabfad
FB
1069 exit(1);
1070 }
5cea8590
PB
1071 if (filename) {
1072 qemu_free(filename);
1073 }
7587cf44
FB
1074 /* map the last 128KB of the BIOS in ISA space */
1075 isa_bios_size = bios_size;
1076 if (isa_bios_size > (128 * 1024))
1077 isa_bios_size = 128 * 1024;
5fafdf24
TS
1078 cpu_register_physical_memory(0x100000 - isa_bios_size,
1079 isa_bios_size,
7587cf44 1080 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
9ae02555 1081
4fc9af53 1082
f753ff16 1083
de2aff17 1084 rom_enable_driver_roms = 1;
45a50b16
GH
1085 option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
1086 cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
f753ff16 1087
1d108d97
AG
1088 /* map all the bios at the top of memory */
1089 cpu_register_physical_memory((uint32_t)(-bios_size),
1090 bios_size, bios_offset | IO_MEM_ROM);
1091
bf483392 1092 fw_cfg = bochs_bios_init();
1d108d97 1093
f753ff16 1094 if (linux_boot) {
45a50b16 1095 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
f753ff16
PB
1096 }
1097
1098 for (i = 0; i < nb_option_roms; i++) {
45a50b16 1099 rom_add_option(option_rom[i]);
406c8df3
GC
1100 }
1101
a5b38b51 1102 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
d537cf6c 1103 i8259 = i8259_init(cpu_irq[0]);
1452411b
AK
1104 isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1105 isa_irq_state->i8259 = i8259;
1632dc6a 1106 isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
d537cf6c 1107
69b91039 1108 if (pci_enabled) {
85a750ca 1109 pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
46e50e9d
FB
1110 } else {
1111 pci_bus = NULL;
2091ba23 1112 isa_bus_new(NULL);
69b91039 1113 }
2091ba23 1114 isa_bus_irqs(isa_irq);
69b91039 1115
3a38d437
JS
1116 ferr_irq = isa_reserve_irq(13);
1117
80cabfad 1118 /* init basic PC hardware */
b41a2cd1 1119 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
80cabfad 1120
f929aad6
FB
1121 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1122
1f04275e
FB
1123 if (cirrus_vga_enabled) {
1124 if (pci_enabled) {
fbe1b595 1125 pci_cirrus_vga_init(pci_bus);
1f04275e 1126 } else {
fbe1b595 1127 isa_cirrus_vga_init();
1f04275e 1128 }
d34cab9f
TS
1129 } else if (vmsvga_enabled) {
1130 if (pci_enabled)
fbe1b595 1131 pci_vmsvga_init(pci_bus);
d34cab9f
TS
1132 else
1133 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
c2b3b41a 1134 } else if (std_vga_enabled) {
89b6b508 1135 if (pci_enabled) {
fbe1b595 1136 pci_vga_init(pci_bus, 0, 0);
89b6b508 1137 } else {
fbe1b595 1138 isa_vga_init();
89b6b508 1139 }
1f04275e 1140 }
80cabfad 1141
32e0c826 1142 rtc_state = rtc_init(2000);
80cabfad 1143
3b4366de
BS
1144 qemu_register_boot_set(pc_boot_set, rtc_state);
1145
e1a23744
FB
1146 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1147 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1148
d592d303 1149 if (pci_enabled) {
1632dc6a 1150 isa_irq_state->ioapic = ioapic_init();
d592d303 1151 }
3a38d437 1152 pit = pit_init(0x40, isa_reserve_irq(0));
fd06c375 1153 pcspk_init(pit);
16b29ae1 1154 if (!no_hpet) {
1452411b 1155 hpet_init(isa_irq);
16b29ae1 1156 }
b41a2cd1 1157
8d11df9e
FB
1158 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1159 if (serial_hds[i]) {
ac0be998 1160 serial_isa_init(i, serial_hds[i]);
8d11df9e
FB
1161 }
1162 }
b41a2cd1 1163
6508fe59
FB
1164 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1165 if (parallel_hds[i]) {
021f0674 1166 parallel_init(i, parallel_hds[i]);
6508fe59
FB
1167 }
1168 }
1169
a41b2ff2 1170 for(i = 0; i < nb_nics; i++) {
cb457d76
AL
1171 NICInfo *nd = &nd_table[i];
1172
1173 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
3a38d437 1174 pc_init_ne2k_isa(nd);
cb457d76 1175 else
07caea31 1176 pci_nic_init_nofail(nd, "e1000", NULL);
a41b2ff2 1177 }
b41a2cd1 1178
e4bcb14c
TS
1179 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1180 fprintf(stderr, "qemu: too many IDE bus\n");
1181 exit(1);
1182 }
1183
1184 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
f455e98c 1185 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
e4bcb14c
TS
1186 }
1187
a41b2ff2 1188 if (pci_enabled) {
ae027ad3 1189 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
a41b2ff2 1190 } else {
e4bcb14c 1191 for(i = 0; i < MAX_IDE_BUS; i++) {
dea21e97 1192 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
e4bcb14c 1193 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
69b91039 1194 }
b41a2cd1 1195 }
69b91039 1196
2e15e23b 1197 isa_dev = isa_create_simple("i8042");
7c29d0c0 1198 DMA_init(0);
6a36d84e 1199#ifdef HAS_AUDIO
1452411b 1200 audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
fb065187 1201#endif
80cabfad 1202
e4bcb14c 1203 for(i = 0; i < MAX_FD; i++) {
fd8014e1 1204 fd[i] = drive_get(IF_FLOPPY, 0, i);
e4bcb14c 1205 }
86c86157 1206 floppy_controller = fdctrl_init_isa(fd);
b41a2cd1 1207
00f82b8a 1208 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
69b91039 1209
bb36d470 1210 if (pci_enabled && usb_enabled) {
afcc3cdf 1211 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
bb36d470
FB
1212 }
1213
6515b203 1214 if (pci_enabled && acpi_enabled) {
3fffc223 1215 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
0ff596d0
PB
1216 i2c_bus *smbus;
1217
1218 /* TODO: Populate SPD eeprom data. */
3a38d437
JS
1219 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1220 isa_reserve_irq(9));
3fffc223 1221 for (i = 0; i < 8; i++) {
1ea96673 1222 DeviceState *eeprom;
02e2da45 1223 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
5b7f5327 1224 qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
ee6847d1 1225 qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
e23a1b33 1226 qdev_init_nofail(eeprom);
3fffc223 1227 }
3f84865a 1228 piix4_acpi_system_hot_add_init(pci_bus);
6515b203 1229 }
3b46e624 1230
a5954d5c
FB
1231 if (i440fx_state) {
1232 i440fx_init_memory_mappings(i440fx_state);
1233 }
e4bcb14c 1234
7d8406be 1235 if (pci_enabled) {
e4bcb14c 1236 int max_bus;
9be5dafe 1237 int bus;
96d30e48 1238
e4bcb14c 1239 max_bus = drive_get_max_bus(IF_SCSI);
e4bcb14c 1240 for (bus = 0; bus <= max_bus; bus++) {
9be5dafe 1241 pci_create_simple(pci_bus, -1, "lsi53c895a");
e4bcb14c 1242 }
7d8406be 1243 }
6e02c38d 1244
a2fa19f9
AL
1245 /* Add virtio console devices */
1246 if (pci_enabled) {
1247 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
0e058a8a 1248 if (virtcon_hds[i]) {
caea79a9 1249 pci_create_simple(pci_bus, -1, "virtio-console-pci");
0e058a8a 1250 }
a2fa19f9
AL
1251 }
1252 }
379526a4
GH
1253
1254 rom_load_fw(fw_cfg);
80cabfad 1255}
b5ff2d6e 1256
c227f099 1257static void pc_init_pci(ram_addr_t ram_size,
3023f332 1258 const char *boot_device,
5fafdf24 1259 const char *kernel_filename,
3dbbdc25 1260 const char *kernel_cmdline,
94fc95cd
JM
1261 const char *initrd_filename,
1262 const char *cpu_model)
3dbbdc25 1263{
fbe1b595 1264 pc_init1(ram_size, boot_device,
3dbbdc25 1265 kernel_filename, kernel_cmdline,
caea79a9 1266 initrd_filename, cpu_model, 1);
3dbbdc25
FB
1267}
1268
c227f099 1269static void pc_init_isa(ram_addr_t ram_size,
3023f332 1270 const char *boot_device,
5fafdf24 1271 const char *kernel_filename,
3dbbdc25 1272 const char *kernel_cmdline,
94fc95cd
JM
1273 const char *initrd_filename,
1274 const char *cpu_model)
3dbbdc25 1275{
679a37af
GH
1276 if (cpu_model == NULL)
1277 cpu_model = "486";
fbe1b595 1278 pc_init1(ram_size, boot_device,
3dbbdc25 1279 kernel_filename, kernel_cmdline,
caea79a9 1280 initrd_filename, cpu_model, 0);
3dbbdc25
FB
1281}
1282
0bacd130
AL
1283/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1284 BIOS will read it and start S3 resume at POST Entry */
1285void cmos_set_s3_resume(void)
1286{
1287 if (rtc_state)
1288 rtc_set_memory(rtc_state, 0xF, 0xFE);
1289}
1290
f80f9ec9 1291static QEMUMachine pc_machine = {
95747581
MM
1292 .name = "pc-0.11",
1293 .alias = "pc",
a245f2e7
AJ
1294 .desc = "Standard PC",
1295 .init = pc_init_pci,
b2097003 1296 .max_cpus = 255,
0c257437 1297 .is_default = 1,
3dbbdc25
FB
1298};
1299
96cc1810
GH
1300static QEMUMachine pc_machine_v0_10 = {
1301 .name = "pc-0.10",
1302 .desc = "Standard PC, qemu 0.10",
1303 .init = pc_init_pci,
1304 .max_cpus = 255,
458fb679 1305 .compat_props = (GlobalProperty[]) {
ab73ff29
GH
1306 {
1307 .driver = "virtio-blk-pci",
1308 .property = "class",
1309 .value = stringify(PCI_CLASS_STORAGE_OTHER),
d6beee99
GH
1310 },{
1311 .driver = "virtio-console-pci",
1312 .property = "class",
1313 .value = stringify(PCI_CLASS_DISPLAY_OTHER),
a1e0fea5
GH
1314 },{
1315 .driver = "virtio-net-pci",
1316 .property = "vectors",
1317 .value = stringify(0),
177539e0
GH
1318 },{
1319 .driver = "virtio-blk-pci",
1320 .property = "vectors",
1321 .value = stringify(0),
ab73ff29 1322 },
96cc1810
GH
1323 { /* end of list */ }
1324 },
1325};
1326
f80f9ec9 1327static QEMUMachine isapc_machine = {
a245f2e7
AJ
1328 .name = "isapc",
1329 .desc = "ISA-only PC",
1330 .init = pc_init_isa,
b2097003 1331 .max_cpus = 1,
b5ff2d6e 1332};
f80f9ec9
AL
1333
1334static void pc_machine_init(void)
1335{
1336 qemu_register_machine(&pc_machine);
96cc1810 1337 qemu_register_machine(&pc_machine_v0_10);
f80f9ec9
AL
1338 qemu_register_machine(&isapc_machine);
1339}
1340
1341machine_init(pc_machine_init);