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Convert linux bootrom to external rom and fw_cfg
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CommitLineData
80cabfad
FB
1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB
24#include "hw.h"
25#include "pc.h"
26#include "fdc.h"
27#include "pci.h"
28#include "block.h"
29#include "sysemu.h"
30#include "audio/audio.h"
31#include "net.h"
32#include "smbus.h"
33#include "boards.h"
376253ec 34#include "monitor.h"
3cce6243 35#include "fw_cfg.h"
16b29ae1 36#include "hpet_emul.h"
9dd986cc 37#include "watchdog.h"
b6f6e3d3 38#include "smbios.h"
ec82026c 39#include "ide.h"
ca20cf32
BS
40#include "loader.h"
41#include "elf.h"
80cabfad 42
b41a2cd1
FB
43/* output Bochs bios info messages */
44//#define DEBUG_BIOS
45
f16408df
AG
46/* Show multiboot debug output */
47//#define DEBUG_MULTIBOOT
48
80cabfad 49#define BIOS_FILENAME "bios.bin"
80cabfad 50
7fb4fdcf
AZ
51#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
52
a80274c3
PB
53/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
54#define ACPI_DATA_SIZE 0x10000
3cce6243 55#define BIOS_CFG_IOPORT 0x510
8a92ea2f 56#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
b6f6e3d3 57#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
6b35e7bf 58#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
80cabfad 59
e4bcb14c
TS
60#define MAX_IDE_BUS 2
61
c227f099 62static fdctrl_t *floppy_controller;
b0a21b53 63static RTCState *rtc_state;
ec844b96 64static PITState *pit;
0a3bacf3 65static PCII440FXState *i440fx_state;
80cabfad 66
1452411b
AK
67typedef struct isa_irq_state {
68 qemu_irq *i8259;
1632dc6a 69 qemu_irq *ioapic;
1452411b
AK
70} IsaIrqState;
71
72static void isa_irq_handler(void *opaque, int n, int level)
73{
74 IsaIrqState *isa = (IsaIrqState *)opaque;
75
1632dc6a
AK
76 if (n < 16) {
77 qemu_set_irq(isa->i8259[n], level);
78 }
2c8d9340
GH
79 if (isa->ioapic)
80 qemu_set_irq(isa->ioapic[n], level);
1632dc6a 81};
1452411b 82
b41a2cd1 83static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
80cabfad
FB
84{
85}
86
f929aad6 87/* MSDOS compatibility mode FPU exception support */
d537cf6c 88static qemu_irq ferr_irq;
f929aad6
FB
89/* XXX: add IGNNE support */
90void cpu_set_ferr(CPUX86State *s)
91{
d537cf6c 92 qemu_irq_raise(ferr_irq);
f929aad6
FB
93}
94
95static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
96{
d537cf6c 97 qemu_irq_lower(ferr_irq);
f929aad6
FB
98}
99
28ab0e2e 100/* TSC handling */
28ab0e2e
FB
101uint64_t cpu_get_tsc(CPUX86State *env)
102{
4a1418e0 103 return cpu_get_ticks();
28ab0e2e
FB
104}
105
a5954d5c
FB
106/* SMM support */
107void cpu_smm_update(CPUState *env)
108{
109 if (i440fx_state && env == first_cpu)
110 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
111}
112
113
3de388f6
FB
114/* IRQ handling */
115int cpu_get_pic_interrupt(CPUState *env)
116{
117 int intno;
118
3de388f6
FB
119 intno = apic_get_interrupt(env);
120 if (intno >= 0) {
121 /* set irq request if a PIC irq is still pending */
122 /* XXX: improve that */
5fafdf24 123 pic_update_irq(isa_pic);
3de388f6
FB
124 return intno;
125 }
3de388f6 126 /* read the irq from the PIC */
0e21e12b
TS
127 if (!apic_accept_pic_intr(env))
128 return -1;
129
3de388f6
FB
130 intno = pic_read_irq(isa_pic);
131 return intno;
132}
133
d537cf6c 134static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 135{
a5b38b51
AJ
136 CPUState *env = first_cpu;
137
d5529471
AJ
138 if (env->apic_state) {
139 while (env) {
140 if (apic_accept_pic_intr(env))
1a7de94a 141 apic_deliver_pic_intr(env, level);
d5529471
AJ
142 env = env->next_cpu;
143 }
144 } else {
b614106a
AJ
145 if (level)
146 cpu_interrupt(env, CPU_INTERRUPT_HARD);
147 else
148 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
a5b38b51 149 }
3de388f6
FB
150}
151
b0a21b53
FB
152/* PC cmos mappings */
153
80cabfad
FB
154#define REG_EQUIPMENT_BYTE 0x14
155
777428f2
FB
156static int cmos_get_fd_drive_type(int fd0)
157{
158 int val;
159
160 switch (fd0) {
161 case 0:
162 /* 1.44 Mb 3"5 drive */
163 val = 4;
164 break;
165 case 1:
166 /* 2.88 Mb 3"5 drive */
167 val = 5;
168 break;
169 case 2:
170 /* 1.2 Mb 5"5 drive */
171 val = 2;
172 break;
173 default:
174 val = 0;
175 break;
176 }
177 return val;
178}
179
5fafdf24 180static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
ba6c2377
FB
181{
182 RTCState *s = rtc_state;
183 int cylinders, heads, sectors;
184 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
185 rtc_set_memory(s, type_ofs, 47);
186 rtc_set_memory(s, info_ofs, cylinders);
187 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
188 rtc_set_memory(s, info_ofs + 2, heads);
189 rtc_set_memory(s, info_ofs + 3, 0xff);
190 rtc_set_memory(s, info_ofs + 4, 0xff);
191 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
192 rtc_set_memory(s, info_ofs + 6, cylinders);
193 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
194 rtc_set_memory(s, info_ofs + 8, sectors);
195}
196
6ac0e82d
AZ
197/* convert boot_device letter to something recognizable by the bios */
198static int boot_device2nibble(char boot_device)
199{
200 switch(boot_device) {
201 case 'a':
202 case 'b':
203 return 0x01; /* floppy boot */
204 case 'c':
205 return 0x02; /* hard drive boot */
206 case 'd':
207 return 0x03; /* CD-ROM boot */
208 case 'n':
209 return 0x04; /* Network boot */
210 }
211 return 0;
212}
213
0ecdffbb
AJ
214/* copy/pasted from cmos_init, should be made a general function
215 and used there as well */
3b4366de 216static int pc_boot_set(void *opaque, const char *boot_device)
0ecdffbb 217{
376253ec 218 Monitor *mon = cur_mon;
0ecdffbb 219#define PC_MAX_BOOT_DEVICES 3
3b4366de 220 RTCState *s = (RTCState *)opaque;
0ecdffbb
AJ
221 int nbds, bds[3] = { 0, };
222 int i;
223
224 nbds = strlen(boot_device);
225 if (nbds > PC_MAX_BOOT_DEVICES) {
376253ec 226 monitor_printf(mon, "Too many boot devices for PC\n");
0ecdffbb
AJ
227 return(1);
228 }
229 for (i = 0; i < nbds; i++) {
230 bds[i] = boot_device2nibble(boot_device[i]);
231 if (bds[i] == 0) {
376253ec
AL
232 monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
233 boot_device[i]);
0ecdffbb
AJ
234 return(1);
235 }
236 }
237 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
238 rtc_set_memory(s, 0x38, (bds[2] << 4));
239 return(0);
240}
241
ba6c2377 242/* hd_table must contain 4 block drivers */
c227f099 243static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
f455e98c 244 const char *boot_device, DriveInfo **hd_table)
80cabfad 245{
b0a21b53 246 RTCState *s = rtc_state;
28c5af54 247 int nbds, bds[3] = { 0, };
80cabfad 248 int val;
b41a2cd1 249 int fd0, fd1, nb;
ba6c2377 250 int i;
b0a21b53 251
b0a21b53 252 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB
253
254 /* memory size */
333190eb
FB
255 val = 640; /* base memory in K */
256 rtc_set_memory(s, 0x15, val);
257 rtc_set_memory(s, 0x16, val >> 8);
258
80cabfad
FB
259 val = (ram_size / 1024) - 1024;
260 if (val > 65535)
261 val = 65535;
b0a21b53
FB
262 rtc_set_memory(s, 0x17, val);
263 rtc_set_memory(s, 0x18, val >> 8);
264 rtc_set_memory(s, 0x30, val);
265 rtc_set_memory(s, 0x31, val >> 8);
80cabfad 266
00f82b8a
AJ
267 if (above_4g_mem_size) {
268 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
269 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
270 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
271 }
272
9da98861
FB
273 if (ram_size > (16 * 1024 * 1024))
274 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
275 else
276 val = 0;
80cabfad
FB
277 if (val > 65535)
278 val = 65535;
b0a21b53
FB
279 rtc_set_memory(s, 0x34, val);
280 rtc_set_memory(s, 0x35, val >> 8);
3b46e624 281
298e01b6
AJ
282 /* set the number of CPU */
283 rtc_set_memory(s, 0x5f, smp_cpus - 1);
284
6ac0e82d 285 /* set boot devices, and disable floppy signature check if requested */
28c5af54
JM
286#define PC_MAX_BOOT_DEVICES 3
287 nbds = strlen(boot_device);
288 if (nbds > PC_MAX_BOOT_DEVICES) {
289 fprintf(stderr, "Too many boot devices for PC\n");
290 exit(1);
291 }
292 for (i = 0; i < nbds; i++) {
293 bds[i] = boot_device2nibble(boot_device[i]);
294 if (bds[i] == 0) {
295 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
296 boot_device[i]);
297 exit(1);
298 }
299 }
300 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
301 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
80cabfad 302
b41a2cd1
FB
303 /* floppy type */
304
baca51fa
FB
305 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
306 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
80cabfad 307
777428f2 308 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
b0a21b53 309 rtc_set_memory(s, 0x10, val);
3b46e624 310
b0a21b53 311 val = 0;
b41a2cd1 312 nb = 0;
80cabfad
FB
313 if (fd0 < 3)
314 nb++;
315 if (fd1 < 3)
316 nb++;
317 switch (nb) {
318 case 0:
319 break;
320 case 1:
b0a21b53 321 val |= 0x01; /* 1 drive, ready for boot */
80cabfad
FB
322 break;
323 case 2:
b0a21b53 324 val |= 0x41; /* 2 drives, ready for boot */
80cabfad
FB
325 break;
326 }
b0a21b53
FB
327 val |= 0x02; /* FPU is there */
328 val |= 0x04; /* PS/2 mouse installed */
329 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
330
ba6c2377
FB
331 /* hard drives */
332
333 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
334 if (hd_table[0])
f455e98c 335 cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
5fafdf24 336 if (hd_table[1])
f455e98c 337 cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
ba6c2377
FB
338
339 val = 0;
40b6ecc6 340 for (i = 0; i < 4; i++) {
ba6c2377 341 if (hd_table[i]) {
46d4767d
FB
342 int cylinders, heads, sectors, translation;
343 /* NOTE: bdrv_get_geometry_hint() returns the physical
344 geometry. It is always such that: 1 <= sects <= 63, 1
345 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
346 geometry can be different if a translation is done. */
f455e98c 347 translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
46d4767d 348 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
f455e98c 349 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
46d4767d
FB
350 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
351 /* No translation. */
352 translation = 0;
353 } else {
354 /* LBA translation. */
355 translation = 1;
356 }
40b6ecc6 357 } else {
46d4767d 358 translation--;
ba6c2377 359 }
ba6c2377
FB
360 val |= translation << (i * 2);
361 }
40b6ecc6 362 }
ba6c2377 363 rtc_set_memory(s, 0x39, val);
80cabfad
FB
364}
365
59b8ad81
FB
366void ioport_set_a20(int enable)
367{
368 /* XXX: send to all CPUs ? */
369 cpu_x86_set_a20(first_cpu, enable);
370}
371
372int ioport_get_a20(void)
373{
374 return ((first_cpu->a20_mask >> 20) & 1);
375}
376
e1a23744
FB
377static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
378{
59b8ad81 379 ioport_set_a20((val >> 1) & 1);
e1a23744
FB
380 /* XXX: bit 0 is fast reset */
381}
382
383static uint32_t ioport92_read(void *opaque, uint32_t addr)
384{
59b8ad81 385 return ioport_get_a20() << 1;
e1a23744
FB
386}
387
80cabfad
FB
388/***********************************************************/
389/* Bochs BIOS debug ports */
390
9596ebb7 391static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad 392{
a2f659ee
FB
393 static const char shutdown_str[8] = "Shutdown";
394 static int shutdown_index = 0;
3b46e624 395
80cabfad
FB
396 switch(addr) {
397 /* Bochs BIOS messages */
398 case 0x400:
399 case 0x401:
400 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
401 exit(1);
402 case 0x402:
403 case 0x403:
404#ifdef DEBUG_BIOS
405 fprintf(stderr, "%c", val);
406#endif
407 break;
a2f659ee
FB
408 case 0x8900:
409 /* same as Bochs power off */
410 if (val == shutdown_str[shutdown_index]) {
411 shutdown_index++;
412 if (shutdown_index == 8) {
413 shutdown_index = 0;
414 qemu_system_shutdown_request();
415 }
416 } else {
417 shutdown_index = 0;
418 }
419 break;
80cabfad
FB
420
421 /* LGPL'ed VGA BIOS messages */
422 case 0x501:
423 case 0x502:
424 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
425 exit(1);
426 case 0x500:
427 case 0x503:
428#ifdef DEBUG_BIOS
429 fprintf(stderr, "%c", val);
430#endif
431 break;
432 }
433}
434
bf483392 435static void *bochs_bios_init(void)
80cabfad 436{
3cce6243 437 void *fw_cfg;
b6f6e3d3
AL
438 uint8_t *smbios_table;
439 size_t smbios_len;
11c2fd3e
AL
440 uint64_t *numa_fw_cfg;
441 int i, j;
3cce6243 442
b41a2cd1
FB
443 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
444 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
445 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
446 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
a2f659ee 447 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
b41a2cd1
FB
448
449 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
450 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
451 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
452 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
3cce6243
BS
453
454 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
bf483392 455
3cce6243 456 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
905fdcb5 457 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
80deece2
BS
458 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
459 acpi_tables_len);
6b35e7bf 460 fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
b6f6e3d3
AL
461
462 smbios_table = smbios_get_table(&smbios_len);
463 if (smbios_table)
464 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
465 smbios_table, smbios_len);
11c2fd3e
AL
466
467 /* allocate memory for the NUMA channel: one (64bit) word for the number
468 * of nodes, one word for each VCPU->node and one word for each node to
469 * hold the amount of memory.
470 */
471 numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
472 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
473 for (i = 0; i < smp_cpus; i++) {
474 for (j = 0; j < nb_numa_nodes; j++) {
475 if (node_cpumask[j] & (1 << i)) {
476 numa_fw_cfg[i + 1] = cpu_to_le64(j);
477 break;
478 }
479 }
480 }
481 for (i = 0; i < nb_numa_nodes; i++) {
482 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
483 }
484 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
485 (1 + smp_cpus + nb_numa_nodes) * 8);
bf483392
AG
486
487 return fw_cfg;
80cabfad
FB
488}
489
642a4f96
TS
490static long get_file_size(FILE *f)
491{
492 long where, size;
493
494 /* XXX: on Unix systems, using fstat() probably makes more sense */
495
496 where = ftell(f);
497 fseek(f, 0, SEEK_END);
498 size = ftell(f);
499 fseek(f, where, SEEK_SET);
500
501 return size;
502}
503
f16408df
AG
504#define MULTIBOOT_STRUCT_ADDR 0x9000
505
506#if MULTIBOOT_STRUCT_ADDR > 0xf0000
507#error multiboot struct needs to fit in 16 bit real mode
508#endif
509
510static int load_multiboot(void *fw_cfg,
511 FILE *f,
512 const char *kernel_filename,
513 const char *initrd_filename,
514 const char *kernel_cmdline,
515 uint8_t *header)
516{
45a50b16 517 int i, is_multiboot = 0;
f16408df
AG
518 uint32_t flags = 0;
519 uint32_t mh_entry_addr;
520 uint32_t mh_load_addr;
521 uint32_t mb_kernel_size;
522 uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
523 uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
f16408df 524 uint32_t mb_mod_end;
45a50b16
GH
525 uint8_t bootinfo[0x500];
526 uint32_t cmdline = 0x200;
77873196
AG
527 uint8_t *mb_kernel_data;
528 uint8_t *mb_bootinfo_data;
f16408df
AG
529
530 /* Ok, let's see if it is a multiboot image.
531 The header is 12x32bit long, so the latest entry may be 8192 - 48. */
532 for (i = 0; i < (8192 - 48); i += 4) {
533 if (ldl_p(header+i) == 0x1BADB002) {
534 uint32_t checksum = ldl_p(header+i+8);
535 flags = ldl_p(header+i+4);
536 checksum += flags;
537 checksum += (uint32_t)0x1BADB002;
538 if (!checksum) {
539 is_multiboot = 1;
540 break;
541 }
542 }
543 }
544
545 if (!is_multiboot)
546 return 0; /* no multiboot */
547
548#ifdef DEBUG_MULTIBOOT
549 fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
550#endif
45a50b16 551 memset(bootinfo, 0, sizeof(bootinfo));
f16408df
AG
552
553 if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
554 fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
555 }
556 if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
557 uint64_t elf_entry;
558 int kernel_size;
559 fclose(f);
ca20cf32
BS
560 kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL,
561 0, ELF_MACHINE, 0);
f16408df
AG
562 if (kernel_size < 0) {
563 fprintf(stderr, "Error while loading elf kernel\n");
564 exit(1);
565 }
566 mh_load_addr = mh_entry_addr = elf_entry;
567 mb_kernel_size = kernel_size;
568
77873196
AG
569 mb_kernel_data = qemu_malloc(mb_kernel_size);
570 if (rom_copy(mb_kernel_data, elf_entry, kernel_size) != kernel_size) {
571 fprintf(stderr, "Error while fetching elf kernel from rom\n");
572 exit(1);
573 }
574
f16408df
AG
575#ifdef DEBUG_MULTIBOOT
576 fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
577 mb_kernel_size, (size_t)mh_entry_addr);
578#endif
579 } else {
580 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
581 uint32_t mh_header_addr = ldl_p(header+i+12);
582 mh_load_addr = ldl_p(header+i+16);
583#ifdef DEBUG_MULTIBOOT
584 uint32_t mh_load_end_addr = ldl_p(header+i+20);
585 uint32_t mh_bss_end_addr = ldl_p(header+i+24);
586#endif
587 uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
588
589 mh_entry_addr = ldl_p(header+i+28);
590 mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
591
592 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
593 uint32_t mh_mode_type = ldl_p(header+i+32);
594 uint32_t mh_width = ldl_p(header+i+36);
595 uint32_t mh_height = ldl_p(header+i+40);
596 uint32_t mh_depth = ldl_p(header+i+44); */
597
598#ifdef DEBUG_MULTIBOOT
599 fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
600 fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
601 fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
602 fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
f16408df
AG
603 fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
604 mb_kernel_size, mh_load_addr);
605#endif
606
77873196 607 mb_kernel_data = qemu_malloc(mb_kernel_size);
45a50b16 608 fseek(f, mb_kernel_text_offset, SEEK_SET);
77873196 609 fread(mb_kernel_data, 1, mb_kernel_size, f);
f16408df
AG
610 fclose(f);
611 }
612
613 /* blob size is only the kernel for now */
614 mb_mod_end = mh_load_addr + mb_kernel_size;
615
616 /* load modules */
45a50b16 617 stl_p(bootinfo + 20, 0x0); /* mods_count */
f16408df 618 if (initrd_filename) {
45a50b16
GH
619 uint32_t mb_mod_info = 0x100;
620 uint32_t mb_mod_cmdline = 0x300;
f16408df
AG
621 uint32_t mb_mod_start = mh_load_addr;
622 uint32_t mb_mod_length = mb_kernel_size;
623 char *next_initrd;
624 char *next_space;
625 int mb_mod_count = 0;
626
627 do {
bf854d65
AL
628 if (mb_mod_info + 16 > mb_mod_cmdline) {
629 printf("WARNING: Too many modules loaded, aborting.\n");
630 break;
631 }
f16408df
AG
632 next_initrd = strchr(initrd_filename, ',');
633 if (next_initrd)
634 *next_initrd = '\0';
635 /* if a space comes after the module filename, treat everything
636 after that as parameters */
45a50b16
GH
637 pstrcpy((char*)bootinfo + mb_mod_cmdline,
638 sizeof(bootinfo) - mb_mod_cmdline,
639 initrd_filename);
3f3d583e 640 stl_p(bootinfo + mb_mod_info + 8, mb_bootinfo + mb_mod_cmdline); /* string */
f16408df 641 mb_mod_cmdline += strlen(initrd_filename) + 1;
bf854d65 642 if (mb_mod_cmdline > sizeof(bootinfo)) {
45a50b16 643 mb_mod_cmdline = sizeof(bootinfo);
bf854d65
AL
644 printf("WARNING: Too many module cmdlines loaded, aborting.\n");
645 break;
646 }
f16408df
AG
647 if ((next_space = strchr(initrd_filename, ' ')))
648 *next_space = '\0';
649#ifdef DEBUG_MULTIBOOT
82663ee2 650 printf("multiboot loading module: %s\n", initrd_filename);
f16408df 651#endif
45a50b16
GH
652 mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
653 & (TARGET_PAGE_MASK);
654 mb_mod_length = get_image_size(initrd_filename);
655 if (mb_mod_length < 0) {
656 fprintf(stderr, "failed to get %s image size\n", initrd_filename);
657 exit(1);
658 }
659 mb_mod_end = mb_mod_start + mb_mod_length;
45a50b16 660 mb_mod_count++;
77873196
AG
661
662 /* append module data at the end of last module */
663 mb_kernel_data = qemu_realloc(mb_kernel_data,
664 mh_load_addr - mb_mod_end);
665 load_image(initrd_filename,
666 mb_kernel_data + mb_mod_start - mh_load_addr);
667
45a50b16
GH
668 stl_p(bootinfo + mb_mod_info + 0, mb_mod_start);
669 stl_p(bootinfo + mb_mod_info + 4, mb_mod_start + mb_mod_length);
670 stl_p(bootinfo + mb_mod_info + 12, 0x0); /* reserved */
f16408df 671#ifdef DEBUG_MULTIBOOT
45a50b16
GH
672 printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
673 mb_mod_start + mb_mod_length);
f16408df 674#endif
f16408df
AG
675 initrd_filename = next_initrd+1;
676 mb_mod_info += 16;
677 } while (next_initrd);
45a50b16
GH
678 stl_p(bootinfo + 20, mb_mod_count); /* mods_count */
679 stl_p(bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
f16408df
AG
680 }
681
f16408df 682 /* Commandline support */
45a50b16
GH
683 stl_p(bootinfo + 16, mb_bootinfo + cmdline);
684 snprintf((char*)bootinfo + cmdline, 0x100, "%s %s",
685 kernel_filename, kernel_cmdline);
f16408df
AG
686
687 /* the kernel is where we want it to be now */
f16408df
AG
688#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
689#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
690#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
691#define MULTIBOOT_FLAGS_MODULES (1 << 3)
692#define MULTIBOOT_FLAGS_MMAP (1 << 6)
45a50b16
GH
693 stl_p(bootinfo, MULTIBOOT_FLAGS_MEMORY
694 | MULTIBOOT_FLAGS_BOOT_DEVICE
695 | MULTIBOOT_FLAGS_CMDLINE
696 | MULTIBOOT_FLAGS_MODULES
697 | MULTIBOOT_FLAGS_MMAP);
698 stl_p(bootinfo + 4, 640); /* mem_lower */
699 stl_p(bootinfo + 8, ram_size / 1024); /* mem_upper */
700 stl_p(bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
701 stl_p(bootinfo + 48, mmap_addr); /* mmap_addr */
f16408df
AG
702
703#ifdef DEBUG_MULTIBOOT
704 fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
705#endif
706
77873196
AG
707 /* save bootinfo off the stack */
708 mb_bootinfo_data = qemu_malloc(sizeof(bootinfo));
709 memcpy(mb_bootinfo_data, bootinfo, sizeof(bootinfo));
710
f16408df 711 /* Pass variables to option rom */
77873196
AG
712 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, mh_entry_addr);
713 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
714 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, mb_mod_end - mh_load_addr);
715 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, mb_kernel_data,
716 mb_mod_end - mh_load_addr);
f16408df 717
77873196
AG
718 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
719 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, sizeof(bootinfo));
720 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, mb_bootinfo_data,
721 sizeof(bootinfo));
f16408df
AG
722
723 option_rom[nb_option_roms] = "multiboot.bin";
724 nb_option_roms++;
725
726 return 1; /* yes, we are multiboot */
727}
728
729static void load_linux(void *fw_cfg,
4fc9af53 730 const char *kernel_filename,
642a4f96 731 const char *initrd_filename,
e6ade764 732 const char *kernel_cmdline,
45a50b16 733 target_phys_addr_t max_ram_size)
642a4f96
TS
734{
735 uint16_t protocol;
5cea8590 736 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
642a4f96 737 uint32_t initrd_max;
57a46d05 738 uint8_t header[8192], *setup, *kernel, *initrd_data;
c227f099 739 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 740 FILE *f;
bf4e5d92 741 char *vmode;
642a4f96
TS
742
743 /* Align to 16 bytes as a paranoia measure */
744 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
745
746 /* load the kernel header */
747 f = fopen(kernel_filename, "rb");
748 if (!f || !(kernel_size = get_file_size(f)) ||
f16408df
AG
749 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
750 MIN(ARRAY_SIZE(header), kernel_size)) {
850810d0
JF
751 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
752 kernel_filename, strerror(errno));
642a4f96
TS
753 exit(1);
754 }
755
756 /* kernel protocol version */
bc4edd79 757#if 0
642a4f96 758 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 759#endif
642a4f96
TS
760 if (ldl_p(header+0x202) == 0x53726448)
761 protocol = lduw_p(header+0x206);
f16408df
AG
762 else {
763 /* This looks like a multiboot kernel. If it is, let's stop
764 treating it like a Linux kernel. */
765 if (load_multiboot(fw_cfg, f, kernel_filename,
766 initrd_filename, kernel_cmdline, header))
82663ee2 767 return;
642a4f96 768 protocol = 0;
f16408df 769 }
642a4f96
TS
770
771 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
772 /* Low kernel */
a37af289
BS
773 real_addr = 0x90000;
774 cmdline_addr = 0x9a000 - cmdline_size;
775 prot_addr = 0x10000;
642a4f96
TS
776 } else if (protocol < 0x202) {
777 /* High but ancient kernel */
a37af289
BS
778 real_addr = 0x90000;
779 cmdline_addr = 0x9a000 - cmdline_size;
780 prot_addr = 0x100000;
642a4f96
TS
781 } else {
782 /* High and recent kernel */
a37af289
BS
783 real_addr = 0x10000;
784 cmdline_addr = 0x20000;
785 prot_addr = 0x100000;
642a4f96
TS
786 }
787
bc4edd79 788#if 0
642a4f96 789 fprintf(stderr,
526ccb7a
AZ
790 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
791 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
792 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
a37af289
BS
793 real_addr,
794 cmdline_addr,
795 prot_addr);
bc4edd79 796#endif
642a4f96
TS
797
798 /* highest address for loading the initrd */
799 if (protocol >= 0x203)
800 initrd_max = ldl_p(header+0x22c);
801 else
802 initrd_max = 0x37ffffff;
803
e6ade764
GC
804 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
805 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
642a4f96 806
57a46d05
AG
807 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
808 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
809 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
810 (uint8_t*)strdup(kernel_cmdline),
811 strlen(kernel_cmdline)+1);
642a4f96
TS
812
813 if (protocol >= 0x202) {
a37af289 814 stl_p(header+0x228, cmdline_addr);
642a4f96
TS
815 } else {
816 stw_p(header+0x20, 0xA33F);
817 stw_p(header+0x22, cmdline_addr-real_addr);
818 }
819
bf4e5d92
PT
820 /* handle vga= parameter */
821 vmode = strstr(kernel_cmdline, "vga=");
822 if (vmode) {
823 unsigned int video_mode;
824 /* skip "vga=" */
825 vmode += 4;
826 if (!strncmp(vmode, "normal", 6)) {
827 video_mode = 0xffff;
828 } else if (!strncmp(vmode, "ext", 3)) {
829 video_mode = 0xfffe;
830 } else if (!strncmp(vmode, "ask", 3)) {
831 video_mode = 0xfffd;
832 } else {
833 video_mode = strtol(vmode, NULL, 0);
834 }
835 stw_p(header+0x1fa, video_mode);
836 }
837
642a4f96
TS
838 /* loader type */
839 /* High nybble = B reserved for Qemu; low nybble is revision number.
840 If this code is substantially changed, you may want to consider
841 incrementing the revision. */
842 if (protocol >= 0x200)
843 header[0x210] = 0xB0;
844
845 /* heap */
846 if (protocol >= 0x201) {
847 header[0x211] |= 0x80; /* CAN_USE_HEAP */
848 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
849 }
850
851 /* load initrd */
852 if (initrd_filename) {
853 if (protocol < 0x200) {
854 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
855 exit(1);
856 }
857
45a50b16
GH
858 initrd_size = get_image_size(initrd_filename);
859 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05
AG
860
861 initrd_data = qemu_malloc(initrd_size);
862 load_image(initrd_filename, initrd_data);
863
864 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
865 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
866 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 867
a37af289 868 stl_p(header+0x218, initrd_addr);
642a4f96
TS
869 stl_p(header+0x21c, initrd_size);
870 }
871
45a50b16 872 /* load kernel and setup */
642a4f96
TS
873 setup_size = header[0x1f1];
874 if (setup_size == 0)
875 setup_size = 4;
642a4f96 876 setup_size = (setup_size+1)*512;
45a50b16 877 kernel_size -= setup_size;
642a4f96 878
45a50b16
GH
879 setup = qemu_malloc(setup_size);
880 kernel = qemu_malloc(kernel_size);
881 fseek(f, 0, SEEK_SET);
882 fread(setup, 1, setup_size, f);
883 fread(kernel, 1, kernel_size, f);
642a4f96 884 fclose(f);
45a50b16 885 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG
886
887 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
888 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
889 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
890
891 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
892 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
893 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
894
895 option_rom[nb_option_roms] = "linuxboot.bin";
896 nb_option_roms++;
642a4f96
TS
897}
898
b41a2cd1
FB
899static const int ide_iobase[2] = { 0x1f0, 0x170 };
900static const int ide_iobase2[2] = { 0x3f6, 0x376 };
901static const int ide_irq[2] = { 14, 15 };
902
903#define NE2000_NB_MAX 6
904
675d6f82
BS
905static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
906 0x280, 0x380 };
907static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 908
675d6f82
BS
909static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
910static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
6508fe59 911
6a36d84e 912#ifdef HAS_AUDIO
d537cf6c 913static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
6a36d84e
FB
914{
915 struct soundhw *c;
6a36d84e 916
3a8bae3e 917 for (c = soundhw; c->name; ++c) {
918 if (c->enabled) {
919 if (c->isa) {
920 c->init.init_isa(pic);
921 } else {
922 if (pci_bus) {
923 c->init.init_pci(pci_bus);
6a36d84e
FB
924 }
925 }
926 }
927 }
928}
929#endif
930
3a38d437 931static void pc_init_ne2k_isa(NICInfo *nd)
a41b2ff2
PB
932{
933 static int nb_ne2k = 0;
934
935 if (nb_ne2k == NE2000_NB_MAX)
936 return;
3a38d437 937 isa_ne2000_init(ne2000_io[nb_ne2k],
9453c5bc 938 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB
939 nb_ne2k++;
940}
941
678e12cc
GN
942int cpu_is_bsp(CPUState *env)
943{
82663ee2 944 return env->cpuid_apic_id == 0;
678e12cc
GN
945}
946
3a31f36a
JK
947static CPUState *pc_new_cpu(const char *cpu_model)
948{
949 CPUState *env;
950
951 env = cpu_init(cpu_model);
952 if (!env) {
953 fprintf(stderr, "Unable to find x86 CPU definition\n");
954 exit(1);
955 }
956 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
957 env->cpuid_apic_id = env->cpu_index;
958 /* APIC reset callback resets cpu */
959 apic_init(env);
960 } else {
961 qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
962 }
963 return env;
964}
965
80cabfad 966/* PC hardware initialisation */
c227f099 967static void pc_init1(ram_addr_t ram_size,
3023f332 968 const char *boot_device,
e8b2a1c6
MM
969 const char *kernel_filename,
970 const char *kernel_cmdline,
3dbbdc25 971 const char *initrd_filename,
e8b2a1c6 972 const char *cpu_model,
caea79a9 973 int pci_enabled)
80cabfad 974{
5cea8590 975 char *filename;
642a4f96 976 int ret, linux_boot, i;
c227f099
AL
977 ram_addr_t ram_addr, bios_offset, option_rom_offset;
978 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
45a50b16 979 int bios_size, isa_bios_size;
46e50e9d 980 PCIBus *pci_bus;
b3999638 981 ISADevice *isa_dev;
5c3ff3a7 982 int piix3_devfn = -1;
59b8ad81 983 CPUState *env;
d537cf6c 984 qemu_irq *cpu_irq;
1452411b 985 qemu_irq *isa_irq;
d537cf6c 986 qemu_irq *i8259;
1452411b 987 IsaIrqState *isa_irq_state;
f455e98c 988 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
fd8014e1 989 DriveInfo *fd[MAX_FD];
bf483392 990 void *fw_cfg;
d592d303 991
00f82b8a
AJ
992 if (ram_size >= 0xe0000000 ) {
993 above_4g_mem_size = ram_size - 0xe0000000;
994 below_4g_mem_size = 0xe0000000;
995 } else {
996 below_4g_mem_size = ram_size;
997 }
998
80cabfad
FB
999 linux_boot = (kernel_filename != NULL);
1000
59b8ad81 1001 /* init CPUs */
a049de61
FB
1002 if (cpu_model == NULL) {
1003#ifdef TARGET_X86_64
1004 cpu_model = "qemu64";
1005#else
1006 cpu_model = "qemu32";
1007#endif
1008 }
3a31f36a
JK
1009
1010 for (i = 0; i < smp_cpus; i++) {
1011 env = pc_new_cpu(cpu_model);
59b8ad81
FB
1012 }
1013
26fb5e48
AJ
1014 vmport_init();
1015
80cabfad 1016 /* allocate RAM */
82b36dc3
AL
1017 ram_addr = qemu_ram_alloc(0xa0000);
1018 cpu_register_physical_memory(0, 0xa0000, ram_addr);
1019
1020 /* Allocate, even though we won't register, so we don't break the
1021 * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1022 * and some bios areas, which will be registered later
1023 */
1024 ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1025 ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1026 cpu_register_physical_memory(0x100000,
1027 below_4g_mem_size - 0x100000,
1028 ram_addr);
00f82b8a
AJ
1029
1030 /* above 4giga memory allocation */
1031 if (above_4g_mem_size > 0) {
8a637d44
PB
1032#if TARGET_PHYS_ADDR_BITS == 32
1033 hw_error("To much RAM for 32-bit physical address");
1034#else
82b36dc3
AL
1035 ram_addr = qemu_ram_alloc(above_4g_mem_size);
1036 cpu_register_physical_memory(0x100000000ULL,
526ccb7a 1037 above_4g_mem_size,
82b36dc3 1038 ram_addr);
8a637d44 1039#endif
00f82b8a 1040 }
80cabfad 1041
82b36dc3 1042
970ac5a3 1043 /* BIOS load */
1192dad8
JM
1044 if (bios_name == NULL)
1045 bios_name = BIOS_FILENAME;
5cea8590
PB
1046 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1047 if (filename) {
1048 bios_size = get_image_size(filename);
1049 } else {
1050 bios_size = -1;
1051 }
5fafdf24 1052 if (bios_size <= 0 ||
970ac5a3 1053 (bios_size % 65536) != 0) {
7587cf44
FB
1054 goto bios_error;
1055 }
970ac5a3 1056 bios_offset = qemu_ram_alloc(bios_size);
51edd4e6
GH
1057 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
1058 if (ret != 0) {
7587cf44 1059 bios_error:
5cea8590 1060 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
80cabfad
FB
1061 exit(1);
1062 }
5cea8590
PB
1063 if (filename) {
1064 qemu_free(filename);
1065 }
7587cf44
FB
1066 /* map the last 128KB of the BIOS in ISA space */
1067 isa_bios_size = bios_size;
1068 if (isa_bios_size > (128 * 1024))
1069 isa_bios_size = 128 * 1024;
5fafdf24
TS
1070 cpu_register_physical_memory(0x100000 - isa_bios_size,
1071 isa_bios_size,
7587cf44 1072 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
9ae02555 1073
4fc9af53 1074
f753ff16 1075
de2aff17 1076 rom_enable_driver_roms = 1;
45a50b16
GH
1077 option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
1078 cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
f753ff16 1079
1d108d97
AG
1080 /* map all the bios at the top of memory */
1081 cpu_register_physical_memory((uint32_t)(-bios_size),
1082 bios_size, bios_offset | IO_MEM_ROM);
1083
bf483392 1084 fw_cfg = bochs_bios_init();
1d108d97 1085
f753ff16 1086 if (linux_boot) {
45a50b16 1087 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
f753ff16
PB
1088 }
1089
1090 for (i = 0; i < nb_option_roms; i++) {
45a50b16 1091 rom_add_option(option_rom[i]);
406c8df3
GC
1092 }
1093
a5b38b51 1094 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
d537cf6c 1095 i8259 = i8259_init(cpu_irq[0]);
1452411b
AK
1096 isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1097 isa_irq_state->i8259 = i8259;
1632dc6a 1098 isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
d537cf6c 1099
69b91039 1100 if (pci_enabled) {
85a750ca 1101 pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
46e50e9d
FB
1102 } else {
1103 pci_bus = NULL;
2091ba23 1104 isa_bus_new(NULL);
69b91039 1105 }
2091ba23 1106 isa_bus_irqs(isa_irq);
69b91039 1107
3a38d437
JS
1108 ferr_irq = isa_reserve_irq(13);
1109
80cabfad 1110 /* init basic PC hardware */
b41a2cd1 1111 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
80cabfad 1112
f929aad6
FB
1113 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1114
1f04275e
FB
1115 if (cirrus_vga_enabled) {
1116 if (pci_enabled) {
fbe1b595 1117 pci_cirrus_vga_init(pci_bus);
1f04275e 1118 } else {
fbe1b595 1119 isa_cirrus_vga_init();
1f04275e 1120 }
d34cab9f
TS
1121 } else if (vmsvga_enabled) {
1122 if (pci_enabled)
fbe1b595 1123 pci_vmsvga_init(pci_bus);
d34cab9f
TS
1124 else
1125 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
c2b3b41a 1126 } else if (std_vga_enabled) {
89b6b508 1127 if (pci_enabled) {
fbe1b595 1128 pci_vga_init(pci_bus, 0, 0);
89b6b508 1129 } else {
fbe1b595 1130 isa_vga_init();
89b6b508 1131 }
1f04275e 1132 }
80cabfad 1133
32e0c826 1134 rtc_state = rtc_init(2000);
80cabfad 1135
3b4366de
BS
1136 qemu_register_boot_set(pc_boot_set, rtc_state);
1137
e1a23744
FB
1138 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1139 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1140
d592d303 1141 if (pci_enabled) {
1632dc6a 1142 isa_irq_state->ioapic = ioapic_init();
d592d303 1143 }
3a38d437 1144 pit = pit_init(0x40, isa_reserve_irq(0));
fd06c375 1145 pcspk_init(pit);
16b29ae1 1146 if (!no_hpet) {
1452411b 1147 hpet_init(isa_irq);
16b29ae1 1148 }
b41a2cd1 1149
8d11df9e
FB
1150 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1151 if (serial_hds[i]) {
ac0be998 1152 serial_isa_init(i, serial_hds[i]);
8d11df9e
FB
1153 }
1154 }
b41a2cd1 1155
6508fe59
FB
1156 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1157 if (parallel_hds[i]) {
021f0674 1158 parallel_init(i, parallel_hds[i]);
6508fe59
FB
1159 }
1160 }
1161
a41b2ff2 1162 for(i = 0; i < nb_nics; i++) {
cb457d76
AL
1163 NICInfo *nd = &nd_table[i];
1164
1165 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
3a38d437 1166 pc_init_ne2k_isa(nd);
cb457d76 1167 else
07caea31 1168 pci_nic_init_nofail(nd, "e1000", NULL);
a41b2ff2 1169 }
b41a2cd1 1170
e4bcb14c
TS
1171 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1172 fprintf(stderr, "qemu: too many IDE bus\n");
1173 exit(1);
1174 }
1175
1176 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
f455e98c 1177 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
e4bcb14c
TS
1178 }
1179
a41b2ff2 1180 if (pci_enabled) {
ae027ad3 1181 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
a41b2ff2 1182 } else {
e4bcb14c 1183 for(i = 0; i < MAX_IDE_BUS; i++) {
dea21e97 1184 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
e4bcb14c 1185 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
69b91039 1186 }
b41a2cd1 1187 }
69b91039 1188
2e15e23b 1189 isa_dev = isa_create_simple("i8042");
7c29d0c0 1190 DMA_init(0);
6a36d84e 1191#ifdef HAS_AUDIO
1452411b 1192 audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
fb065187 1193#endif
80cabfad 1194
e4bcb14c 1195 for(i = 0; i < MAX_FD; i++) {
fd8014e1 1196 fd[i] = drive_get(IF_FLOPPY, 0, i);
e4bcb14c 1197 }
86c86157 1198 floppy_controller = fdctrl_init_isa(fd);
b41a2cd1 1199
00f82b8a 1200 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
69b91039 1201
bb36d470 1202 if (pci_enabled && usb_enabled) {
afcc3cdf 1203 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
bb36d470
FB
1204 }
1205
6515b203 1206 if (pci_enabled && acpi_enabled) {
3fffc223 1207 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
0ff596d0
PB
1208 i2c_bus *smbus;
1209
1210 /* TODO: Populate SPD eeprom data. */
3a38d437
JS
1211 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1212 isa_reserve_irq(9));
3fffc223 1213 for (i = 0; i < 8; i++) {
1ea96673 1214 DeviceState *eeprom;
02e2da45 1215 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
5b7f5327 1216 qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
ee6847d1 1217 qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
e23a1b33 1218 qdev_init_nofail(eeprom);
3fffc223 1219 }
3f84865a 1220 piix4_acpi_system_hot_add_init(pci_bus);
6515b203 1221 }
3b46e624 1222
a5954d5c
FB
1223 if (i440fx_state) {
1224 i440fx_init_memory_mappings(i440fx_state);
1225 }
e4bcb14c 1226
7d8406be 1227 if (pci_enabled) {
e4bcb14c 1228 int max_bus;
9be5dafe 1229 int bus;
96d30e48 1230
e4bcb14c 1231 max_bus = drive_get_max_bus(IF_SCSI);
e4bcb14c 1232 for (bus = 0; bus <= max_bus; bus++) {
9be5dafe 1233 pci_create_simple(pci_bus, -1, "lsi53c895a");
e4bcb14c 1234 }
7d8406be 1235 }
6e02c38d 1236
a2fa19f9
AL
1237 /* Add virtio console devices */
1238 if (pci_enabled) {
1239 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
0e058a8a 1240 if (virtcon_hds[i]) {
caea79a9 1241 pci_create_simple(pci_bus, -1, "virtio-console-pci");
0e058a8a 1242 }
a2fa19f9
AL
1243 }
1244 }
80cabfad 1245}
b5ff2d6e 1246
c227f099 1247static void pc_init_pci(ram_addr_t ram_size,
3023f332 1248 const char *boot_device,
5fafdf24 1249 const char *kernel_filename,
3dbbdc25 1250 const char *kernel_cmdline,
94fc95cd
JM
1251 const char *initrd_filename,
1252 const char *cpu_model)
3dbbdc25 1253{
fbe1b595 1254 pc_init1(ram_size, boot_device,
3dbbdc25 1255 kernel_filename, kernel_cmdline,
caea79a9 1256 initrd_filename, cpu_model, 1);
3dbbdc25
FB
1257}
1258
c227f099 1259static void pc_init_isa(ram_addr_t ram_size,
3023f332 1260 const char *boot_device,
5fafdf24 1261 const char *kernel_filename,
3dbbdc25 1262 const char *kernel_cmdline,
94fc95cd
JM
1263 const char *initrd_filename,
1264 const char *cpu_model)
3dbbdc25 1265{
679a37af
GH
1266 if (cpu_model == NULL)
1267 cpu_model = "486";
fbe1b595 1268 pc_init1(ram_size, boot_device,
3dbbdc25 1269 kernel_filename, kernel_cmdline,
caea79a9 1270 initrd_filename, cpu_model, 0);
3dbbdc25
FB
1271}
1272
0bacd130
AL
1273/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1274 BIOS will read it and start S3 resume at POST Entry */
1275void cmos_set_s3_resume(void)
1276{
1277 if (rtc_state)
1278 rtc_set_memory(rtc_state, 0xF, 0xFE);
1279}
1280
f80f9ec9 1281static QEMUMachine pc_machine = {
95747581
MM
1282 .name = "pc-0.11",
1283 .alias = "pc",
a245f2e7
AJ
1284 .desc = "Standard PC",
1285 .init = pc_init_pci,
b2097003 1286 .max_cpus = 255,
0c257437 1287 .is_default = 1,
3dbbdc25
FB
1288};
1289
96cc1810
GH
1290static QEMUMachine pc_machine_v0_10 = {
1291 .name = "pc-0.10",
1292 .desc = "Standard PC, qemu 0.10",
1293 .init = pc_init_pci,
1294 .max_cpus = 255,
1295 .compat_props = (CompatProperty[]) {
ab73ff29
GH
1296 {
1297 .driver = "virtio-blk-pci",
1298 .property = "class",
1299 .value = stringify(PCI_CLASS_STORAGE_OTHER),
d6beee99
GH
1300 },{
1301 .driver = "virtio-console-pci",
1302 .property = "class",
1303 .value = stringify(PCI_CLASS_DISPLAY_OTHER),
a1e0fea5
GH
1304 },{
1305 .driver = "virtio-net-pci",
1306 .property = "vectors",
1307 .value = stringify(0),
177539e0
GH
1308 },{
1309 .driver = "virtio-blk-pci",
1310 .property = "vectors",
1311 .value = stringify(0),
ab73ff29 1312 },
96cc1810
GH
1313 { /* end of list */ }
1314 },
1315};
1316
f80f9ec9 1317static QEMUMachine isapc_machine = {
a245f2e7
AJ
1318 .name = "isapc",
1319 .desc = "ISA-only PC",
1320 .init = pc_init_isa,
b2097003 1321 .max_cpus = 1,
b5ff2d6e 1322};
f80f9ec9
AL
1323
1324static void pc_machine_init(void)
1325{
1326 qemu_register_machine(&pc_machine);
96cc1810 1327 qemu_register_machine(&pc_machine_v0_10);
f80f9ec9
AL
1328 qemu_register_machine(&isapc_machine);
1329}
1330
1331machine_init(pc_machine_init);