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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b PB |
27 | #include "fdc.h" |
28 | #include "pci.h" | |
18e08a55 MT |
29 | #include "vmware_vga.h" |
30 | #include "usb-uhci.h" | |
31 | #include "usb-ohci.h" | |
32 | #include "prep_pci.h" | |
33 | #include "apb_pci.h" | |
87ecb68b PB |
34 | #include "block.h" |
35 | #include "sysemu.h" | |
36 | #include "audio/audio.h" | |
37 | #include "net.h" | |
38 | #include "smbus.h" | |
39 | #include "boards.h" | |
376253ec | 40 | #include "monitor.h" |
3cce6243 | 41 | #include "fw_cfg.h" |
16b29ae1 | 42 | #include "hpet_emul.h" |
9dd986cc | 43 | #include "watchdog.h" |
b6f6e3d3 | 44 | #include "smbios.h" |
ec82026c | 45 | #include "ide.h" |
ca20cf32 BS |
46 | #include "loader.h" |
47 | #include "elf.h" | |
52001445 | 48 | #include "multiboot.h" |
53b67b30 | 49 | #include "kvm.h" |
80cabfad | 50 | |
b41a2cd1 FB |
51 | /* output Bochs bios info messages */ |
52 | //#define DEBUG_BIOS | |
53 | ||
80cabfad | 54 | #define BIOS_FILENAME "bios.bin" |
80cabfad | 55 | |
7fb4fdcf AZ |
56 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
57 | ||
a80274c3 PB |
58 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
59 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 60 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 61 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 62 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 63 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 64 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
80cabfad | 65 | |
e4bcb14c TS |
66 | #define MAX_IDE_BUS 2 |
67 | ||
4c5b10b7 JS |
68 | #define E820_NR_ENTRIES 16 |
69 | ||
70 | struct e820_entry { | |
71 | uint64_t address; | |
72 | uint64_t length; | |
73 | uint32_t type; | |
74 | }; | |
75 | ||
76 | struct e820_table { | |
77 | uint32_t count; | |
78 | struct e820_entry entry[E820_NR_ENTRIES]; | |
79 | }; | |
80 | ||
81 | static struct e820_table e820_table; | |
82 | ||
1452411b AK |
83 | typedef struct isa_irq_state { |
84 | qemu_irq *i8259; | |
1632dc6a | 85 | qemu_irq *ioapic; |
1452411b AK |
86 | } IsaIrqState; |
87 | ||
88 | static void isa_irq_handler(void *opaque, int n, int level) | |
89 | { | |
90 | IsaIrqState *isa = (IsaIrqState *)opaque; | |
91 | ||
1632dc6a AK |
92 | if (n < 16) { |
93 | qemu_set_irq(isa->i8259[n], level); | |
94 | } | |
2c8d9340 GH |
95 | if (isa->ioapic) |
96 | qemu_set_irq(isa->ioapic[n], level); | |
1632dc6a | 97 | }; |
1452411b | 98 | |
b41a2cd1 | 99 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
100 | { |
101 | } | |
102 | ||
f929aad6 | 103 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 104 | static qemu_irq ferr_irq; |
f929aad6 FB |
105 | /* XXX: add IGNNE support */ |
106 | void cpu_set_ferr(CPUX86State *s) | |
107 | { | |
d537cf6c | 108 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
109 | } |
110 | ||
111 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
112 | { | |
d537cf6c | 113 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
114 | } |
115 | ||
28ab0e2e | 116 | /* TSC handling */ |
28ab0e2e FB |
117 | uint64_t cpu_get_tsc(CPUX86State *env) |
118 | { | |
4a1418e0 | 119 | return cpu_get_ticks(); |
28ab0e2e FB |
120 | } |
121 | ||
a5954d5c | 122 | /* SMM support */ |
f885f1ea IY |
123 | |
124 | static cpu_set_smm_t smm_set; | |
125 | static void *smm_arg; | |
126 | ||
127 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
128 | { | |
129 | assert(smm_set == NULL); | |
130 | assert(smm_arg == NULL); | |
131 | smm_set = callback; | |
132 | smm_arg = arg; | |
133 | } | |
134 | ||
a5954d5c FB |
135 | void cpu_smm_update(CPUState *env) |
136 | { | |
f885f1ea IY |
137 | if (smm_set && smm_arg && env == first_cpu) |
138 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
139 | } |
140 | ||
141 | ||
3de388f6 FB |
142 | /* IRQ handling */ |
143 | int cpu_get_pic_interrupt(CPUState *env) | |
144 | { | |
145 | int intno; | |
146 | ||
3de388f6 FB |
147 | intno = apic_get_interrupt(env); |
148 | if (intno >= 0) { | |
149 | /* set irq request if a PIC irq is still pending */ | |
150 | /* XXX: improve that */ | |
5fafdf24 | 151 | pic_update_irq(isa_pic); |
3de388f6 FB |
152 | return intno; |
153 | } | |
3de388f6 | 154 | /* read the irq from the PIC */ |
0e21e12b TS |
155 | if (!apic_accept_pic_intr(env)) |
156 | return -1; | |
157 | ||
3de388f6 FB |
158 | intno = pic_read_irq(isa_pic); |
159 | return intno; | |
160 | } | |
161 | ||
d537cf6c | 162 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 163 | { |
a5b38b51 AJ |
164 | CPUState *env = first_cpu; |
165 | ||
d5529471 AJ |
166 | if (env->apic_state) { |
167 | while (env) { | |
168 | if (apic_accept_pic_intr(env)) | |
1a7de94a | 169 | apic_deliver_pic_intr(env, level); |
d5529471 AJ |
170 | env = env->next_cpu; |
171 | } | |
172 | } else { | |
b614106a AJ |
173 | if (level) |
174 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
175 | else | |
176 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 177 | } |
3de388f6 FB |
178 | } |
179 | ||
b0a21b53 FB |
180 | /* PC cmos mappings */ |
181 | ||
80cabfad FB |
182 | #define REG_EQUIPMENT_BYTE 0x14 |
183 | ||
777428f2 FB |
184 | static int cmos_get_fd_drive_type(int fd0) |
185 | { | |
186 | int val; | |
187 | ||
188 | switch (fd0) { | |
189 | case 0: | |
190 | /* 1.44 Mb 3"5 drive */ | |
191 | val = 4; | |
192 | break; | |
193 | case 1: | |
194 | /* 2.88 Mb 3"5 drive */ | |
195 | val = 5; | |
196 | break; | |
197 | case 2: | |
198 | /* 1.2 Mb 5"5 drive */ | |
199 | val = 2; | |
200 | break; | |
201 | default: | |
202 | val = 0; | |
203 | break; | |
204 | } | |
205 | return val; | |
206 | } | |
207 | ||
ec2654fb IY |
208 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, |
209 | RTCState *s) | |
ba6c2377 | 210 | { |
ba6c2377 FB |
211 | int cylinders, heads, sectors; |
212 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
213 | rtc_set_memory(s, type_ofs, 47); | |
214 | rtc_set_memory(s, info_ofs, cylinders); | |
215 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
216 | rtc_set_memory(s, info_ofs + 2, heads); | |
217 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
218 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
219 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
220 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
221 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
222 | rtc_set_memory(s, info_ofs + 8, sectors); | |
223 | } | |
224 | ||
6ac0e82d AZ |
225 | /* convert boot_device letter to something recognizable by the bios */ |
226 | static int boot_device2nibble(char boot_device) | |
227 | { | |
228 | switch(boot_device) { | |
229 | case 'a': | |
230 | case 'b': | |
231 | return 0x01; /* floppy boot */ | |
232 | case 'c': | |
233 | return 0x02; /* hard drive boot */ | |
234 | case 'd': | |
235 | return 0x03; /* CD-ROM boot */ | |
236 | case 'n': | |
237 | return 0x04; /* Network boot */ | |
238 | } | |
239 | return 0; | |
240 | } | |
241 | ||
d9346e81 | 242 | static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
243 | { |
244 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
245 | int nbds, bds[3] = { 0, }; |
246 | int i; | |
247 | ||
248 | nbds = strlen(boot_device); | |
249 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 250 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
251 | return(1); |
252 | } | |
253 | for (i = 0; i < nbds; i++) { | |
254 | bds[i] = boot_device2nibble(boot_device[i]); | |
255 | if (bds[i] == 0) { | |
1ecda02b MA |
256 | error_report("Invalid boot device for PC: '%c'", |
257 | boot_device[i]); | |
0ecdffbb AJ |
258 | return(1); |
259 | } | |
260 | } | |
261 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 262 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
263 | return(0); |
264 | } | |
265 | ||
d9346e81 MA |
266 | static int pc_boot_set(void *opaque, const char *boot_device) |
267 | { | |
268 | return set_boot_dev(opaque, boot_device, 0); | |
269 | } | |
270 | ||
ba6c2377 | 271 | /* hd_table must contain 4 block drivers */ |
c227f099 | 272 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
01b9e8c1 | 273 | const char *boot_device, DriveInfo **hd_table, |
ec2654fb | 274 | FDCtrl *floppy_controller, RTCState *s) |
80cabfad | 275 | { |
80cabfad | 276 | int val; |
b41a2cd1 | 277 | int fd0, fd1, nb; |
ba6c2377 | 278 | int i; |
b0a21b53 | 279 | |
b0a21b53 | 280 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
281 | |
282 | /* memory size */ | |
333190eb FB |
283 | val = 640; /* base memory in K */ |
284 | rtc_set_memory(s, 0x15, val); | |
285 | rtc_set_memory(s, 0x16, val >> 8); | |
286 | ||
80cabfad FB |
287 | val = (ram_size / 1024) - 1024; |
288 | if (val > 65535) | |
289 | val = 65535; | |
b0a21b53 FB |
290 | rtc_set_memory(s, 0x17, val); |
291 | rtc_set_memory(s, 0x18, val >> 8); | |
292 | rtc_set_memory(s, 0x30, val); | |
293 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 294 | |
00f82b8a AJ |
295 | if (above_4g_mem_size) { |
296 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
297 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
298 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
299 | } | |
300 | ||
9da98861 FB |
301 | if (ram_size > (16 * 1024 * 1024)) |
302 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
303 | else | |
304 | val = 0; | |
80cabfad FB |
305 | if (val > 65535) |
306 | val = 65535; | |
b0a21b53 FB |
307 | rtc_set_memory(s, 0x34, val); |
308 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 309 | |
298e01b6 AJ |
310 | /* set the number of CPU */ |
311 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
312 | ||
6ac0e82d | 313 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 314 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
315 | exit(1); |
316 | } | |
80cabfad | 317 | |
b41a2cd1 FB |
318 | /* floppy type */ |
319 | ||
baca51fa FB |
320 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
321 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 322 | |
777428f2 | 323 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 324 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 325 | |
b0a21b53 | 326 | val = 0; |
b41a2cd1 | 327 | nb = 0; |
80cabfad FB |
328 | if (fd0 < 3) |
329 | nb++; | |
330 | if (fd1 < 3) | |
331 | nb++; | |
332 | switch (nb) { | |
333 | case 0: | |
334 | break; | |
335 | case 1: | |
b0a21b53 | 336 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
337 | break; |
338 | case 2: | |
b0a21b53 | 339 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
340 | break; |
341 | } | |
b0a21b53 FB |
342 | val |= 0x02; /* FPU is there */ |
343 | val |= 0x04; /* PS/2 mouse installed */ | |
344 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
345 | ||
ba6c2377 FB |
346 | /* hard drives */ |
347 | ||
348 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
349 | if (hd_table[0]) | |
ec2654fb | 350 | cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s); |
5fafdf24 | 351 | if (hd_table[1]) |
ec2654fb | 352 | cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s); |
ba6c2377 FB |
353 | |
354 | val = 0; | |
40b6ecc6 | 355 | for (i = 0; i < 4; i++) { |
ba6c2377 | 356 | if (hd_table[i]) { |
46d4767d FB |
357 | int cylinders, heads, sectors, translation; |
358 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
359 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
360 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
361 | geometry can be different if a translation is done. */ | |
f455e98c | 362 | translation = bdrv_get_translation_hint(hd_table[i]->bdrv); |
46d4767d | 363 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { |
f455e98c | 364 | bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, §ors); |
46d4767d FB |
365 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
366 | /* No translation. */ | |
367 | translation = 0; | |
368 | } else { | |
369 | /* LBA translation. */ | |
370 | translation = 1; | |
371 | } | |
40b6ecc6 | 372 | } else { |
46d4767d | 373 | translation--; |
ba6c2377 | 374 | } |
ba6c2377 FB |
375 | val |= translation << (i * 2); |
376 | } | |
40b6ecc6 | 377 | } |
ba6c2377 | 378 | rtc_set_memory(s, 0x39, val); |
80cabfad FB |
379 | } |
380 | ||
59b8ad81 FB |
381 | void ioport_set_a20(int enable) |
382 | { | |
383 | /* XXX: send to all CPUs ? */ | |
384 | cpu_x86_set_a20(first_cpu, enable); | |
385 | } | |
386 | ||
387 | int ioport_get_a20(void) | |
388 | { | |
389 | return ((first_cpu->a20_mask >> 20) & 1); | |
390 | } | |
391 | ||
e1a23744 FB |
392 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
393 | { | |
59b8ad81 | 394 | ioport_set_a20((val >> 1) & 1); |
e1a23744 FB |
395 | /* XXX: bit 0 is fast reset */ |
396 | } | |
397 | ||
398 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
399 | { | |
59b8ad81 | 400 | return ioport_get_a20() << 1; |
e1a23744 FB |
401 | } |
402 | ||
80cabfad FB |
403 | /***********************************************************/ |
404 | /* Bochs BIOS debug ports */ | |
405 | ||
9596ebb7 | 406 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 407 | { |
a2f659ee FB |
408 | static const char shutdown_str[8] = "Shutdown"; |
409 | static int shutdown_index = 0; | |
3b46e624 | 410 | |
80cabfad FB |
411 | switch(addr) { |
412 | /* Bochs BIOS messages */ | |
413 | case 0x400: | |
414 | case 0x401: | |
415 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
416 | exit(1); | |
417 | case 0x402: | |
418 | case 0x403: | |
419 | #ifdef DEBUG_BIOS | |
420 | fprintf(stderr, "%c", val); | |
421 | #endif | |
422 | break; | |
a2f659ee FB |
423 | case 0x8900: |
424 | /* same as Bochs power off */ | |
425 | if (val == shutdown_str[shutdown_index]) { | |
426 | shutdown_index++; | |
427 | if (shutdown_index == 8) { | |
428 | shutdown_index = 0; | |
429 | qemu_system_shutdown_request(); | |
430 | } | |
431 | } else { | |
432 | shutdown_index = 0; | |
433 | } | |
434 | break; | |
80cabfad FB |
435 | |
436 | /* LGPL'ed VGA BIOS messages */ | |
437 | case 0x501: | |
438 | case 0x502: | |
439 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
440 | exit(1); | |
441 | case 0x500: | |
442 | case 0x503: | |
443 | #ifdef DEBUG_BIOS | |
444 | fprintf(stderr, "%c", val); | |
445 | #endif | |
446 | break; | |
447 | } | |
448 | } | |
449 | ||
4c5b10b7 JS |
450 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
451 | { | |
452 | int index = e820_table.count; | |
453 | struct e820_entry *entry; | |
454 | ||
455 | if (index >= E820_NR_ENTRIES) | |
456 | return -EBUSY; | |
457 | entry = &e820_table.entry[index]; | |
458 | ||
459 | entry->address = address; | |
460 | entry->length = length; | |
461 | entry->type = type; | |
462 | ||
463 | e820_table.count++; | |
464 | return e820_table.count; | |
465 | } | |
466 | ||
bf483392 | 467 | static void *bochs_bios_init(void) |
80cabfad | 468 | { |
3cce6243 | 469 | void *fw_cfg; |
b6f6e3d3 AL |
470 | uint8_t *smbios_table; |
471 | size_t smbios_len; | |
11c2fd3e AL |
472 | uint64_t *numa_fw_cfg; |
473 | int i, j; | |
3cce6243 | 474 | |
b41a2cd1 FB |
475 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
476 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
477 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
478 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 479 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
480 | |
481 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
482 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
483 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
484 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
485 | |
486 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 487 | |
3cce6243 | 488 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 489 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
490 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
491 | acpi_tables_len); | |
6b35e7bf | 492 | fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1); |
b6f6e3d3 AL |
493 | |
494 | smbios_table = smbios_get_table(&smbios_len); | |
495 | if (smbios_table) | |
496 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
497 | smbios_table, smbios_len); | |
4c5b10b7 JS |
498 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
499 | sizeof(struct e820_table)); | |
11c2fd3e AL |
500 | |
501 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
502 | * of nodes, one word for each VCPU->node and one word for each node to | |
503 | * hold the amount of memory. | |
504 | */ | |
505 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
506 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
507 | for (i = 0; i < smp_cpus; i++) { | |
508 | for (j = 0; j < nb_numa_nodes; j++) { | |
509 | if (node_cpumask[j] & (1 << i)) { | |
510 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
511 | break; | |
512 | } | |
513 | } | |
514 | } | |
515 | for (i = 0; i < nb_numa_nodes; i++) { | |
516 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
517 | } | |
518 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
519 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
bf483392 AG |
520 | |
521 | return fw_cfg; | |
80cabfad FB |
522 | } |
523 | ||
642a4f96 TS |
524 | static long get_file_size(FILE *f) |
525 | { | |
526 | long where, size; | |
527 | ||
528 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
529 | ||
530 | where = ftell(f); | |
531 | fseek(f, 0, SEEK_END); | |
532 | size = ftell(f); | |
533 | fseek(f, where, SEEK_SET); | |
534 | ||
535 | return size; | |
536 | } | |
537 | ||
f16408df | 538 | static void load_linux(void *fw_cfg, |
4fc9af53 | 539 | const char *kernel_filename, |
642a4f96 | 540 | const char *initrd_filename, |
e6ade764 | 541 | const char *kernel_cmdline, |
45a50b16 | 542 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
543 | { |
544 | uint16_t protocol; | |
5cea8590 | 545 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 546 | uint32_t initrd_max; |
57a46d05 | 547 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 548 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 549 | FILE *f; |
bf4e5d92 | 550 | char *vmode; |
642a4f96 TS |
551 | |
552 | /* Align to 16 bytes as a paranoia measure */ | |
553 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
554 | ||
555 | /* load the kernel header */ | |
556 | f = fopen(kernel_filename, "rb"); | |
557 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
558 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
559 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
560 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
561 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
562 | exit(1); |
563 | } | |
564 | ||
565 | /* kernel protocol version */ | |
bc4edd79 | 566 | #if 0 |
642a4f96 | 567 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 568 | #endif |
642a4f96 TS |
569 | if (ldl_p(header+0x202) == 0x53726448) |
570 | protocol = lduw_p(header+0x206); | |
f16408df AG |
571 | else { |
572 | /* This looks like a multiboot kernel. If it is, let's stop | |
573 | treating it like a Linux kernel. */ | |
52001445 AL |
574 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
575 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 576 | return; |
642a4f96 | 577 | protocol = 0; |
f16408df | 578 | } |
642a4f96 TS |
579 | |
580 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
581 | /* Low kernel */ | |
a37af289 BS |
582 | real_addr = 0x90000; |
583 | cmdline_addr = 0x9a000 - cmdline_size; | |
584 | prot_addr = 0x10000; | |
642a4f96 TS |
585 | } else if (protocol < 0x202) { |
586 | /* High but ancient kernel */ | |
a37af289 BS |
587 | real_addr = 0x90000; |
588 | cmdline_addr = 0x9a000 - cmdline_size; | |
589 | prot_addr = 0x100000; | |
642a4f96 TS |
590 | } else { |
591 | /* High and recent kernel */ | |
a37af289 BS |
592 | real_addr = 0x10000; |
593 | cmdline_addr = 0x20000; | |
594 | prot_addr = 0x100000; | |
642a4f96 TS |
595 | } |
596 | ||
bc4edd79 | 597 | #if 0 |
642a4f96 | 598 | fprintf(stderr, |
526ccb7a AZ |
599 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
600 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
601 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
602 | real_addr, |
603 | cmdline_addr, | |
604 | prot_addr); | |
bc4edd79 | 605 | #endif |
642a4f96 TS |
606 | |
607 | /* highest address for loading the initrd */ | |
608 | if (protocol >= 0x203) | |
609 | initrd_max = ldl_p(header+0x22c); | |
610 | else | |
611 | initrd_max = 0x37ffffff; | |
612 | ||
e6ade764 GC |
613 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
614 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 615 | |
57a46d05 AG |
616 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
617 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
618 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
619 | (uint8_t*)strdup(kernel_cmdline), | |
620 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
621 | |
622 | if (protocol >= 0x202) { | |
a37af289 | 623 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
624 | } else { |
625 | stw_p(header+0x20, 0xA33F); | |
626 | stw_p(header+0x22, cmdline_addr-real_addr); | |
627 | } | |
628 | ||
bf4e5d92 PT |
629 | /* handle vga= parameter */ |
630 | vmode = strstr(kernel_cmdline, "vga="); | |
631 | if (vmode) { | |
632 | unsigned int video_mode; | |
633 | /* skip "vga=" */ | |
634 | vmode += 4; | |
635 | if (!strncmp(vmode, "normal", 6)) { | |
636 | video_mode = 0xffff; | |
637 | } else if (!strncmp(vmode, "ext", 3)) { | |
638 | video_mode = 0xfffe; | |
639 | } else if (!strncmp(vmode, "ask", 3)) { | |
640 | video_mode = 0xfffd; | |
641 | } else { | |
642 | video_mode = strtol(vmode, NULL, 0); | |
643 | } | |
644 | stw_p(header+0x1fa, video_mode); | |
645 | } | |
646 | ||
642a4f96 TS |
647 | /* loader type */ |
648 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
649 | If this code is substantially changed, you may want to consider | |
650 | incrementing the revision. */ | |
651 | if (protocol >= 0x200) | |
652 | header[0x210] = 0xB0; | |
653 | ||
654 | /* heap */ | |
655 | if (protocol >= 0x201) { | |
656 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
657 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
658 | } | |
659 | ||
660 | /* load initrd */ | |
661 | if (initrd_filename) { | |
662 | if (protocol < 0x200) { | |
663 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
664 | exit(1); | |
665 | } | |
666 | ||
45a50b16 | 667 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
668 | if (initrd_size < 0) { |
669 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
670 | initrd_filename); | |
671 | exit(1); | |
672 | } | |
673 | ||
45a50b16 | 674 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 AG |
675 | |
676 | initrd_data = qemu_malloc(initrd_size); | |
677 | load_image(initrd_filename, initrd_data); | |
678 | ||
679 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
680 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
681 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 682 | |
a37af289 | 683 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
684 | stl_p(header+0x21c, initrd_size); |
685 | } | |
686 | ||
45a50b16 | 687 | /* load kernel and setup */ |
642a4f96 TS |
688 | setup_size = header[0x1f1]; |
689 | if (setup_size == 0) | |
690 | setup_size = 4; | |
642a4f96 | 691 | setup_size = (setup_size+1)*512; |
45a50b16 | 692 | kernel_size -= setup_size; |
642a4f96 | 693 | |
45a50b16 GH |
694 | setup = qemu_malloc(setup_size); |
695 | kernel = qemu_malloc(kernel_size); | |
696 | fseek(f, 0, SEEK_SET); | |
5a41ecc5 KS |
697 | if (fread(setup, 1, setup_size, f) != setup_size) { |
698 | fprintf(stderr, "fread() failed\n"); | |
699 | exit(1); | |
700 | } | |
701 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
702 | fprintf(stderr, "fread() failed\n"); | |
703 | exit(1); | |
704 | } | |
642a4f96 | 705 | fclose(f); |
45a50b16 | 706 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
707 | |
708 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
709 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
710 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
711 | ||
712 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
713 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
714 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
715 | ||
716 | option_rom[nb_option_roms] = "linuxboot.bin"; | |
717 | nb_option_roms++; | |
642a4f96 TS |
718 | } |
719 | ||
b41a2cd1 FB |
720 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
721 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
722 | static const int ide_irq[2] = { 14, 15 }; | |
723 | ||
724 | #define NE2000_NB_MAX 6 | |
725 | ||
675d6f82 BS |
726 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
727 | 0x280, 0x380 }; | |
728 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 729 | |
675d6f82 BS |
730 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
731 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 732 | |
6a36d84e | 733 | #ifdef HAS_AUDIO |
d537cf6c | 734 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
735 | { |
736 | struct soundhw *c; | |
6a36d84e | 737 | |
3a8bae3e | 738 | for (c = soundhw; c->name; ++c) { |
739 | if (c->enabled) { | |
740 | if (c->isa) { | |
741 | c->init.init_isa(pic); | |
742 | } else { | |
743 | if (pci_bus) { | |
744 | c->init.init_pci(pci_bus); | |
6a36d84e FB |
745 | } |
746 | } | |
747 | } | |
748 | } | |
749 | } | |
750 | #endif | |
751 | ||
3a38d437 | 752 | static void pc_init_ne2k_isa(NICInfo *nd) |
a41b2ff2 PB |
753 | { |
754 | static int nb_ne2k = 0; | |
755 | ||
756 | if (nb_ne2k == NE2000_NB_MAX) | |
757 | return; | |
3a38d437 | 758 | isa_ne2000_init(ne2000_io[nb_ne2k], |
9453c5bc | 759 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
760 | nb_ne2k++; |
761 | } | |
762 | ||
678e12cc GN |
763 | int cpu_is_bsp(CPUState *env) |
764 | { | |
6cb2996c JK |
765 | /* We hard-wire the BSP to the first CPU. */ |
766 | return env->cpu_index == 0; | |
678e12cc GN |
767 | } |
768 | ||
53b67b30 BS |
769 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
770 | BIOS will read it and start S3 resume at POST Entry */ | |
771 | static void cmos_set_s3_resume(void *opaque, int irq, int level) | |
772 | { | |
773 | RTCState *s = opaque; | |
774 | ||
775 | if (level) { | |
776 | rtc_set_memory(s, 0xF, 0xFE); | |
777 | } | |
778 | } | |
779 | ||
780 | static void acpi_smi_interrupt(void *opaque, int irq, int level) | |
781 | { | |
782 | CPUState *s = opaque; | |
783 | ||
784 | if (level) { | |
785 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
786 | } | |
787 | } | |
788 | ||
3a31f36a JK |
789 | static CPUState *pc_new_cpu(const char *cpu_model) |
790 | { | |
791 | CPUState *env; | |
792 | ||
793 | env = cpu_init(cpu_model); | |
794 | if (!env) { | |
795 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
796 | exit(1); | |
797 | } | |
798 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
799 | env->cpuid_apic_id = env->cpu_index; | |
800 | /* APIC reset callback resets cpu */ | |
801 | apic_init(env); | |
802 | } else { | |
803 | qemu_register_reset((QEMUResetHandler*)cpu_reset, env); | |
804 | } | |
805 | return env; | |
806 | } | |
807 | ||
6f09e686 IY |
808 | static qemu_irq *pc_allocate_cpu_irq(void) |
809 | { | |
810 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
811 | } | |
812 | ||
80cabfad | 813 | /* PC hardware initialisation */ |
c227f099 | 814 | static void pc_init1(ram_addr_t ram_size, |
3023f332 | 815 | const char *boot_device, |
e8b2a1c6 MM |
816 | const char *kernel_filename, |
817 | const char *kernel_cmdline, | |
3dbbdc25 | 818 | const char *initrd_filename, |
e8b2a1c6 | 819 | const char *cpu_model, |
caea79a9 | 820 | int pci_enabled) |
80cabfad | 821 | { |
5cea8590 | 822 | char *filename; |
642a4f96 | 823 | int ret, linux_boot, i; |
c227f099 AL |
824 | ram_addr_t ram_addr, bios_offset, option_rom_offset; |
825 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
45a50b16 | 826 | int bios_size, isa_bios_size; |
46e50e9d | 827 | PCIBus *pci_bus; |
f885f1ea | 828 | PCII440FXState *i440fx_state; |
5c3ff3a7 | 829 | int piix3_devfn = -1; |
d537cf6c | 830 | qemu_irq *cpu_irq; |
1452411b | 831 | qemu_irq *isa_irq; |
d537cf6c | 832 | qemu_irq *i8259; |
53b67b30 BS |
833 | qemu_irq *cmos_s3; |
834 | qemu_irq *smi_irq; | |
1452411b | 835 | IsaIrqState *isa_irq_state; |
f455e98c | 836 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 837 | DriveInfo *fd[MAX_FD]; |
bf483392 | 838 | void *fw_cfg; |
01b9e8c1 | 839 | FDCtrl *floppy_controller; |
ec2654fb | 840 | RTCState *rtc_state; |
57864959 | 841 | PITState *pit; |
d592d303 | 842 | |
00f82b8a AJ |
843 | if (ram_size >= 0xe0000000 ) { |
844 | above_4g_mem_size = ram_size - 0xe0000000; | |
845 | below_4g_mem_size = 0xe0000000; | |
846 | } else { | |
847 | below_4g_mem_size = ram_size; | |
848 | } | |
849 | ||
80cabfad FB |
850 | linux_boot = (kernel_filename != NULL); |
851 | ||
59b8ad81 | 852 | /* init CPUs */ |
a049de61 FB |
853 | if (cpu_model == NULL) { |
854 | #ifdef TARGET_X86_64 | |
855 | cpu_model = "qemu64"; | |
856 | #else | |
857 | cpu_model = "qemu32"; | |
858 | #endif | |
859 | } | |
3a31f36a JK |
860 | |
861 | for (i = 0; i < smp_cpus; i++) { | |
7f5b7d3e | 862 | pc_new_cpu(cpu_model); |
59b8ad81 FB |
863 | } |
864 | ||
26fb5e48 AJ |
865 | vmport_init(); |
866 | ||
80cabfad | 867 | /* allocate RAM */ |
60e4c631 | 868 | ram_addr = qemu_ram_alloc(below_4g_mem_size); |
82b36dc3 | 869 | cpu_register_physical_memory(0, 0xa0000, ram_addr); |
82b36dc3 AL |
870 | cpu_register_physical_memory(0x100000, |
871 | below_4g_mem_size - 0x100000, | |
60e4c631 | 872 | ram_addr + 0x100000); |
00f82b8a AJ |
873 | |
874 | /* above 4giga memory allocation */ | |
875 | if (above_4g_mem_size > 0) { | |
8a637d44 PB |
876 | #if TARGET_PHYS_ADDR_BITS == 32 |
877 | hw_error("To much RAM for 32-bit physical address"); | |
878 | #else | |
82b36dc3 AL |
879 | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
880 | cpu_register_physical_memory(0x100000000ULL, | |
526ccb7a | 881 | above_4g_mem_size, |
82b36dc3 | 882 | ram_addr); |
8a637d44 | 883 | #endif |
00f82b8a | 884 | } |
80cabfad | 885 | |
82b36dc3 | 886 | |
970ac5a3 | 887 | /* BIOS load */ |
1192dad8 JM |
888 | if (bios_name == NULL) |
889 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
890 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
891 | if (filename) { | |
892 | bios_size = get_image_size(filename); | |
893 | } else { | |
894 | bios_size = -1; | |
895 | } | |
5fafdf24 | 896 | if (bios_size <= 0 || |
970ac5a3 | 897 | (bios_size % 65536) != 0) { |
7587cf44 FB |
898 | goto bios_error; |
899 | } | |
970ac5a3 | 900 | bios_offset = qemu_ram_alloc(bios_size); |
51edd4e6 GH |
901 | ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
902 | if (ret != 0) { | |
7587cf44 | 903 | bios_error: |
5cea8590 | 904 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); |
80cabfad FB |
905 | exit(1); |
906 | } | |
5cea8590 PB |
907 | if (filename) { |
908 | qemu_free(filename); | |
909 | } | |
7587cf44 FB |
910 | /* map the last 128KB of the BIOS in ISA space */ |
911 | isa_bios_size = bios_size; | |
912 | if (isa_bios_size > (128 * 1024)) | |
913 | isa_bios_size = 128 * 1024; | |
5fafdf24 TS |
914 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
915 | isa_bios_size, | |
7587cf44 | 916 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 917 | |
45a50b16 GH |
918 | option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE); |
919 | cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); | |
f753ff16 | 920 | |
1d108d97 AG |
921 | /* map all the bios at the top of memory */ |
922 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
923 | bios_size, bios_offset | IO_MEM_ROM); | |
924 | ||
bf483392 | 925 | fw_cfg = bochs_bios_init(); |
8832cb80 | 926 | rom_set_fw(fw_cfg); |
1d108d97 | 927 | |
f753ff16 | 928 | if (linux_boot) { |
45a50b16 | 929 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
930 | } |
931 | ||
932 | for (i = 0; i < nb_option_roms; i++) { | |
45a50b16 | 933 | rom_add_option(option_rom[i]); |
406c8df3 GC |
934 | } |
935 | ||
6f09e686 | 936 | cpu_irq = pc_allocate_cpu_irq(); |
d537cf6c | 937 | i8259 = i8259_init(cpu_irq[0]); |
1452411b AK |
938 | isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state)); |
939 | isa_irq_state->i8259 = i8259; | |
b8d6f539 IY |
940 | if (pci_enabled) { |
941 | isa_irq_state->ioapic = ioapic_init(); | |
942 | } | |
1632dc6a | 943 | isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); |
d537cf6c | 944 | |
69b91039 | 945 | if (pci_enabled) { |
ec5f92ce | 946 | pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size); |
46e50e9d FB |
947 | } else { |
948 | pci_bus = NULL; | |
2091ba23 | 949 | isa_bus_new(NULL); |
69b91039 | 950 | } |
2091ba23 | 951 | isa_bus_irqs(isa_irq); |
69b91039 | 952 | |
3a38d437 JS |
953 | ferr_irq = isa_reserve_irq(13); |
954 | ||
80cabfad | 955 | /* init basic PC hardware */ |
b41a2cd1 | 956 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
80cabfad | 957 | |
f929aad6 FB |
958 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
959 | ||
1f04275e FB |
960 | if (cirrus_vga_enabled) { |
961 | if (pci_enabled) { | |
fbe1b595 | 962 | pci_cirrus_vga_init(pci_bus); |
1f04275e | 963 | } else { |
fbe1b595 | 964 | isa_cirrus_vga_init(); |
1f04275e | 965 | } |
d34cab9f TS |
966 | } else if (vmsvga_enabled) { |
967 | if (pci_enabled) | |
fbe1b595 | 968 | pci_vmsvga_init(pci_bus); |
d34cab9f TS |
969 | else |
970 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
c2b3b41a | 971 | } else if (std_vga_enabled) { |
89b6b508 | 972 | if (pci_enabled) { |
fbe1b595 | 973 | pci_vga_init(pci_bus, 0, 0); |
89b6b508 | 974 | } else { |
fbe1b595 | 975 | isa_vga_init(); |
89b6b508 | 976 | } |
1f04275e | 977 | } |
80cabfad | 978 | |
32e0c826 | 979 | rtc_state = rtc_init(2000); |
80cabfad | 980 | |
3b4366de BS |
981 | qemu_register_boot_set(pc_boot_set, rtc_state); |
982 | ||
e1a23744 FB |
983 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
984 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
985 | ||
3a38d437 | 986 | pit = pit_init(0x40, isa_reserve_irq(0)); |
fd06c375 | 987 | pcspk_init(pit); |
16b29ae1 | 988 | if (!no_hpet) { |
1452411b | 989 | hpet_init(isa_irq); |
16b29ae1 | 990 | } |
b41a2cd1 | 991 | |
8d11df9e FB |
992 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
993 | if (serial_hds[i]) { | |
ac0be998 | 994 | serial_isa_init(i, serial_hds[i]); |
8d11df9e FB |
995 | } |
996 | } | |
b41a2cd1 | 997 | |
6508fe59 FB |
998 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
999 | if (parallel_hds[i]) { | |
021f0674 | 1000 | parallel_init(i, parallel_hds[i]); |
6508fe59 FB |
1001 | } |
1002 | } | |
1003 | ||
a41b2ff2 | 1004 | for(i = 0; i < nb_nics; i++) { |
cb457d76 AL |
1005 | NICInfo *nd = &nd_table[i]; |
1006 | ||
1007 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
3a38d437 | 1008 | pc_init_ne2k_isa(nd); |
cb457d76 | 1009 | else |
07caea31 | 1010 | pci_nic_init_nofail(nd, "e1000", NULL); |
a41b2ff2 | 1011 | } |
b41a2cd1 | 1012 | |
e4bcb14c TS |
1013 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
1014 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1015 | exit(1); | |
1016 | } | |
1017 | ||
1018 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 1019 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
1020 | } |
1021 | ||
a41b2ff2 | 1022 | if (pci_enabled) { |
ae027ad3 | 1023 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1); |
a41b2ff2 | 1024 | } else { |
e4bcb14c | 1025 | for(i = 0; i < MAX_IDE_BUS; i++) { |
dea21e97 | 1026 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c | 1027 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); |
69b91039 | 1028 | } |
b41a2cd1 | 1029 | } |
69b91039 | 1030 | |
7f5b7d3e | 1031 | isa_create_simple("i8042"); |
7c29d0c0 | 1032 | DMA_init(0); |
6a36d84e | 1033 | #ifdef HAS_AUDIO |
1452411b | 1034 | audio_init(pci_enabled ? pci_bus : NULL, isa_irq); |
fb065187 | 1035 | #endif |
80cabfad | 1036 | |
e4bcb14c | 1037 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 1038 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 1039 | } |
86c86157 | 1040 | floppy_controller = fdctrl_init_isa(fd); |
b41a2cd1 | 1041 | |
01b9e8c1 | 1042 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd, |
ec2654fb | 1043 | floppy_controller, rtc_state); |
69b91039 | 1044 | |
bb36d470 | 1045 | if (pci_enabled && usb_enabled) { |
afcc3cdf | 1046 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); |
bb36d470 FB |
1047 | } |
1048 | ||
6515b203 | 1049 | if (pci_enabled && acpi_enabled) { |
3fffc223 | 1050 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
0ff596d0 PB |
1051 | i2c_bus *smbus; |
1052 | ||
53b67b30 BS |
1053 | cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1); |
1054 | smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1); | |
0ff596d0 | 1055 | /* TODO: Populate SPD eeprom data. */ |
3a38d437 | 1056 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, |
53b67b30 BS |
1057 | isa_reserve_irq(9), *cmos_s3, *smi_irq, |
1058 | kvm_enabled()); | |
3fffc223 | 1059 | for (i = 0; i < 8; i++) { |
1ea96673 | 1060 | DeviceState *eeprom; |
02e2da45 | 1061 | eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); |
5b7f5327 | 1062 | qdev_prop_set_uint8(eeprom, "address", 0x50 + i); |
ee6847d1 | 1063 | qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
e23a1b33 | 1064 | qdev_init_nofail(eeprom); |
3fffc223 | 1065 | } |
3f84865a | 1066 | piix4_acpi_system_hot_add_init(pci_bus); |
6515b203 | 1067 | } |
3b46e624 | 1068 | |
a5954d5c FB |
1069 | if (i440fx_state) { |
1070 | i440fx_init_memory_mappings(i440fx_state); | |
1071 | } | |
e4bcb14c | 1072 | |
7d8406be | 1073 | if (pci_enabled) { |
e4bcb14c | 1074 | int max_bus; |
9be5dafe | 1075 | int bus; |
96d30e48 | 1076 | |
e4bcb14c | 1077 | max_bus = drive_get_max_bus(IF_SCSI); |
e4bcb14c | 1078 | for (bus = 0; bus <= max_bus; bus++) { |
9be5dafe | 1079 | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
e4bcb14c | 1080 | } |
7d8406be | 1081 | } |
80cabfad | 1082 | } |
b5ff2d6e | 1083 | |
c227f099 | 1084 | static void pc_init_pci(ram_addr_t ram_size, |
3023f332 | 1085 | const char *boot_device, |
5fafdf24 | 1086 | const char *kernel_filename, |
3dbbdc25 | 1087 | const char *kernel_cmdline, |
94fc95cd JM |
1088 | const char *initrd_filename, |
1089 | const char *cpu_model) | |
3dbbdc25 | 1090 | { |
fbe1b595 | 1091 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1092 | kernel_filename, kernel_cmdline, |
caea79a9 | 1093 | initrd_filename, cpu_model, 1); |
3dbbdc25 FB |
1094 | } |
1095 | ||
c227f099 | 1096 | static void pc_init_isa(ram_addr_t ram_size, |
3023f332 | 1097 | const char *boot_device, |
5fafdf24 | 1098 | const char *kernel_filename, |
3dbbdc25 | 1099 | const char *kernel_cmdline, |
94fc95cd JM |
1100 | const char *initrd_filename, |
1101 | const char *cpu_model) | |
3dbbdc25 | 1102 | { |
679a37af GH |
1103 | if (cpu_model == NULL) |
1104 | cpu_model = "486"; | |
fbe1b595 | 1105 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1106 | kernel_filename, kernel_cmdline, |
caea79a9 | 1107 | initrd_filename, cpu_model, 0); |
3dbbdc25 FB |
1108 | } |
1109 | ||
f80f9ec9 | 1110 | static QEMUMachine pc_machine = { |
d76fa62d | 1111 | .name = "pc-0.13", |
95747581 | 1112 | .alias = "pc", |
a245f2e7 AJ |
1113 | .desc = "Standard PC", |
1114 | .init = pc_init_pci, | |
b2097003 | 1115 | .max_cpus = 255, |
0c257437 | 1116 | .is_default = 1, |
3dbbdc25 FB |
1117 | }; |
1118 | ||
d76fa62d AS |
1119 | static QEMUMachine pc_machine_v0_12 = { |
1120 | .name = "pc-0.12", | |
1121 | .desc = "Standard PC", | |
1122 | .init = pc_init_pci, | |
1123 | .max_cpus = 255, | |
8bfbde6d AS |
1124 | .compat_props = (GlobalProperty[]) { |
1125 | { | |
1126 | .driver = "virtio-serial-pci", | |
1127 | .property = "max_nr_ports", | |
1128 | .value = stringify(1), | |
1129 | },{ | |
1130 | .driver = "virtio-serial-pci", | |
1131 | .property = "vectors", | |
1132 | .value = stringify(0), | |
1133 | }, | |
1134 | { /* end of list */ } | |
1135 | } | |
d76fa62d AS |
1136 | }; |
1137 | ||
2cae6f5e GH |
1138 | static QEMUMachine pc_machine_v0_11 = { |
1139 | .name = "pc-0.11", | |
1140 | .desc = "Standard PC, qemu 0.11", | |
1141 | .init = pc_init_pci, | |
1142 | .max_cpus = 255, | |
1143 | .compat_props = (GlobalProperty[]) { | |
1144 | { | |
1145 | .driver = "virtio-blk-pci", | |
1146 | .property = "vectors", | |
1147 | .value = stringify(0), | |
8bfbde6d AS |
1148 | },{ |
1149 | .driver = "virtio-serial-pci", | |
1150 | .property = "max_nr_ports", | |
1151 | .value = stringify(1), | |
1152 | },{ | |
1153 | .driver = "virtio-serial-pci", | |
1154 | .property = "vectors", | |
1155 | .value = stringify(0), | |
374ef704 GH |
1156 | },{ |
1157 | .driver = "ide-drive", | |
1158 | .property = "ver", | |
1159 | .value = "0.11", | |
1160 | },{ | |
1161 | .driver = "scsi-disk", | |
1162 | .property = "ver", | |
1163 | .value = "0.11", | |
20a86364 GH |
1164 | },{ |
1165 | .driver = "PCI", | |
1166 | .property = "rombar", | |
1167 | .value = stringify(0), | |
2cae6f5e GH |
1168 | }, |
1169 | { /* end of list */ } | |
1170 | } | |
1171 | }; | |
1172 | ||
96cc1810 GH |
1173 | static QEMUMachine pc_machine_v0_10 = { |
1174 | .name = "pc-0.10", | |
1175 | .desc = "Standard PC, qemu 0.10", | |
1176 | .init = pc_init_pci, | |
1177 | .max_cpus = 255, | |
458fb679 | 1178 | .compat_props = (GlobalProperty[]) { |
ab73ff29 GH |
1179 | { |
1180 | .driver = "virtio-blk-pci", | |
1181 | .property = "class", | |
1182 | .value = stringify(PCI_CLASS_STORAGE_OTHER), | |
d6beee99 | 1183 | },{ |
98b19252 | 1184 | .driver = "virtio-serial-pci", |
d6beee99 GH |
1185 | .property = "class", |
1186 | .value = stringify(PCI_CLASS_DISPLAY_OTHER), | |
8bfbde6d AS |
1187 | },{ |
1188 | .driver = "virtio-serial-pci", | |
1189 | .property = "max_nr_ports", | |
1190 | .value = stringify(1), | |
1191 | },{ | |
1192 | .driver = "virtio-serial-pci", | |
1193 | .property = "vectors", | |
1194 | .value = stringify(0), | |
a1e0fea5 GH |
1195 | },{ |
1196 | .driver = "virtio-net-pci", | |
1197 | .property = "vectors", | |
1198 | .value = stringify(0), | |
177539e0 GH |
1199 | },{ |
1200 | .driver = "virtio-blk-pci", | |
1201 | .property = "vectors", | |
1202 | .value = stringify(0), | |
374ef704 GH |
1203 | },{ |
1204 | .driver = "ide-drive", | |
1205 | .property = "ver", | |
1206 | .value = "0.10", | |
1207 | },{ | |
1208 | .driver = "scsi-disk", | |
1209 | .property = "ver", | |
1210 | .value = "0.10", | |
20a86364 GH |
1211 | },{ |
1212 | .driver = "PCI", | |
1213 | .property = "rombar", | |
1214 | .value = stringify(0), | |
ab73ff29 | 1215 | }, |
96cc1810 GH |
1216 | { /* end of list */ } |
1217 | }, | |
1218 | }; | |
1219 | ||
f80f9ec9 | 1220 | static QEMUMachine isapc_machine = { |
a245f2e7 AJ |
1221 | .name = "isapc", |
1222 | .desc = "ISA-only PC", | |
1223 | .init = pc_init_isa, | |
b2097003 | 1224 | .max_cpus = 1, |
b5ff2d6e | 1225 | }; |
f80f9ec9 AL |
1226 | |
1227 | static void pc_machine_init(void) | |
1228 | { | |
1229 | qemu_register_machine(&pc_machine); | |
d76fa62d | 1230 | qemu_register_machine(&pc_machine_v0_12); |
2cae6f5e | 1231 | qemu_register_machine(&pc_machine_v0_11); |
96cc1810 | 1232 | qemu_register_machine(&pc_machine_v0_10); |
f80f9ec9 AL |
1233 | qemu_register_machine(&isapc_machine); |
1234 | } | |
1235 | ||
1236 | machine_init(pc_machine_init); |