]>
Commit | Line | Data |
---|---|---|
80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b | 27 | #include "fdc.h" |
c0897e0c | 28 | #include "ide.h" |
87ecb68b | 29 | #include "pci.h" |
18e08a55 | 30 | #include "vmware_vga.h" |
376253ec | 31 | #include "monitor.h" |
3cce6243 | 32 | #include "fw_cfg.h" |
16b29ae1 | 33 | #include "hpet_emul.h" |
b6f6e3d3 | 34 | #include "smbios.h" |
ca20cf32 BS |
35 | #include "loader.h" |
36 | #include "elf.h" | |
52001445 | 37 | #include "multiboot.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
b1277b03 | 39 | #include "i8254.h" |
302fe51b | 40 | #include "pcspk.h" |
60ba3cc2 | 41 | #include "msi.h" |
822557eb | 42 | #include "sysbus.h" |
666daa68 | 43 | #include "sysemu.h" |
9b5b76d4 | 44 | #include "kvm.h" |
9468e9c4 | 45 | #include "xen.h" |
2446333c | 46 | #include "blockdev.h" |
a19cbfb3 | 47 | #include "ui/qemu-spice.h" |
00cb2a99 | 48 | #include "memory.h" |
be20f9e9 | 49 | #include "exec-memory.h" |
c2d8d311 | 50 | #include "arch_init.h" |
80cabfad | 51 | |
b41a2cd1 FB |
52 | /* output Bochs bios info messages */ |
53 | //#define DEBUG_BIOS | |
54 | ||
471fd342 BS |
55 | /* debug PC/ISA interrupts */ |
56 | //#define DEBUG_IRQ | |
57 | ||
58 | #ifdef DEBUG_IRQ | |
59 | #define DPRINTF(fmt, ...) \ | |
60 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
61 | #else | |
62 | #define DPRINTF(fmt, ...) | |
63 | #endif | |
64 | ||
a80274c3 PB |
65 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
66 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 67 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 68 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 69 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 70 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 71 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 72 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 73 | |
92a16d7a BS |
74 | #define MSI_ADDR_BASE 0xfee00000 |
75 | ||
4c5b10b7 JS |
76 | #define E820_NR_ENTRIES 16 |
77 | ||
78 | struct e820_entry { | |
79 | uint64_t address; | |
80 | uint64_t length; | |
81 | uint32_t type; | |
541dc0d4 | 82 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
83 | |
84 | struct e820_table { | |
85 | uint32_t count; | |
86 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 87 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
88 | |
89 | static struct e820_table e820_table; | |
dd703b99 | 90 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 91 | |
b881fbe9 | 92 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 93 | { |
b881fbe9 | 94 | GSIState *s = opaque; |
1452411b | 95 | |
b881fbe9 JK |
96 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
97 | if (n < ISA_NUM_IRQS) { | |
98 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 99 | } |
b881fbe9 | 100 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 101 | } |
1452411b | 102 | |
b41a2cd1 | 103 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
104 | { |
105 | } | |
106 | ||
f929aad6 | 107 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 108 | static qemu_irq ferr_irq; |
8e78eb28 IY |
109 | |
110 | void pc_register_ferr_irq(qemu_irq irq) | |
111 | { | |
112 | ferr_irq = irq; | |
113 | } | |
114 | ||
f929aad6 FB |
115 | /* XXX: add IGNNE support */ |
116 | void cpu_set_ferr(CPUX86State *s) | |
117 | { | |
d537cf6c | 118 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
119 | } |
120 | ||
121 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
122 | { | |
d537cf6c | 123 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
124 | } |
125 | ||
28ab0e2e | 126 | /* TSC handling */ |
28ab0e2e FB |
127 | uint64_t cpu_get_tsc(CPUX86State *env) |
128 | { | |
4a1418e0 | 129 | return cpu_get_ticks(); |
28ab0e2e FB |
130 | } |
131 | ||
a5954d5c | 132 | /* SMM support */ |
f885f1ea IY |
133 | |
134 | static cpu_set_smm_t smm_set; | |
135 | static void *smm_arg; | |
136 | ||
137 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
138 | { | |
139 | assert(smm_set == NULL); | |
140 | assert(smm_arg == NULL); | |
141 | smm_set = callback; | |
142 | smm_arg = arg; | |
143 | } | |
144 | ||
4a8fa5dc | 145 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 146 | { |
f885f1ea IY |
147 | if (smm_set && smm_arg && env == first_cpu) |
148 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
149 | } |
150 | ||
151 | ||
3de388f6 | 152 | /* IRQ handling */ |
4a8fa5dc | 153 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 FB |
154 | { |
155 | int intno; | |
156 | ||
cf6d64bf | 157 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 | 158 | if (intno >= 0) { |
3de388f6 FB |
159 | return intno; |
160 | } | |
3de388f6 | 161 | /* read the irq from the PIC */ |
cf6d64bf | 162 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 163 | return -1; |
cf6d64bf | 164 | } |
0e21e12b | 165 | |
3de388f6 FB |
166 | intno = pic_read_irq(isa_pic); |
167 | return intno; | |
168 | } | |
169 | ||
d537cf6c | 170 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 171 | { |
4a8fa5dc | 172 | CPUX86State *env = first_cpu; |
a5b38b51 | 173 | |
471fd342 | 174 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
175 | if (env->apic_state) { |
176 | while (env) { | |
cf6d64bf BS |
177 | if (apic_accept_pic_intr(env->apic_state)) { |
178 | apic_deliver_pic_intr(env->apic_state, level); | |
179 | } | |
d5529471 AJ |
180 | env = env->next_cpu; |
181 | } | |
182 | } else { | |
b614106a AJ |
183 | if (level) |
184 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
185 | else | |
186 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 187 | } |
3de388f6 FB |
188 | } |
189 | ||
b0a21b53 FB |
190 | /* PC cmos mappings */ |
191 | ||
80cabfad FB |
192 | #define REG_EQUIPMENT_BYTE 0x14 |
193 | ||
d288c7ba | 194 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
195 | { |
196 | int val; | |
197 | ||
198 | switch (fd0) { | |
d288c7ba | 199 | case FDRIVE_DRV_144: |
777428f2 FB |
200 | /* 1.44 Mb 3"5 drive */ |
201 | val = 4; | |
202 | break; | |
d288c7ba | 203 | case FDRIVE_DRV_288: |
777428f2 FB |
204 | /* 2.88 Mb 3"5 drive */ |
205 | val = 5; | |
206 | break; | |
d288c7ba | 207 | case FDRIVE_DRV_120: |
777428f2 FB |
208 | /* 1.2 Mb 5"5 drive */ |
209 | val = 2; | |
210 | break; | |
d288c7ba | 211 | case FDRIVE_DRV_NONE: |
777428f2 FB |
212 | default: |
213 | val = 0; | |
214 | break; | |
215 | } | |
216 | return val; | |
217 | } | |
218 | ||
9139046c MA |
219 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
220 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 221 | { |
ba6c2377 FB |
222 | rtc_set_memory(s, type_ofs, 47); |
223 | rtc_set_memory(s, info_ofs, cylinders); | |
224 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
225 | rtc_set_memory(s, info_ofs + 2, heads); | |
226 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
227 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
228 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
229 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
230 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
231 | rtc_set_memory(s, info_ofs + 8, sectors); | |
232 | } | |
233 | ||
6ac0e82d AZ |
234 | /* convert boot_device letter to something recognizable by the bios */ |
235 | static int boot_device2nibble(char boot_device) | |
236 | { | |
237 | switch(boot_device) { | |
238 | case 'a': | |
239 | case 'b': | |
240 | return 0x01; /* floppy boot */ | |
241 | case 'c': | |
242 | return 0x02; /* hard drive boot */ | |
243 | case 'd': | |
244 | return 0x03; /* CD-ROM boot */ | |
245 | case 'n': | |
246 | return 0x04; /* Network boot */ | |
247 | } | |
248 | return 0; | |
249 | } | |
250 | ||
1d914fa0 | 251 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
252 | { |
253 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
254 | int nbds, bds[3] = { 0, }; |
255 | int i; | |
256 | ||
257 | nbds = strlen(boot_device); | |
258 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 259 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
260 | return(1); |
261 | } | |
262 | for (i = 0; i < nbds; i++) { | |
263 | bds[i] = boot_device2nibble(boot_device[i]); | |
264 | if (bds[i] == 0) { | |
1ecda02b MA |
265 | error_report("Invalid boot device for PC: '%c'", |
266 | boot_device[i]); | |
0ecdffbb AJ |
267 | return(1); |
268 | } | |
269 | } | |
270 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 271 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
272 | return(0); |
273 | } | |
274 | ||
d9346e81 MA |
275 | static int pc_boot_set(void *opaque, const char *boot_device) |
276 | { | |
277 | return set_boot_dev(opaque, boot_device, 0); | |
278 | } | |
279 | ||
c0897e0c MA |
280 | typedef struct pc_cmos_init_late_arg { |
281 | ISADevice *rtc_state; | |
9139046c | 282 | BusState *idebus[2]; |
c0897e0c MA |
283 | } pc_cmos_init_late_arg; |
284 | ||
285 | static void pc_cmos_init_late(void *opaque) | |
286 | { | |
287 | pc_cmos_init_late_arg *arg = opaque; | |
288 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
289 | int16_t cylinders; |
290 | int8_t heads, sectors; | |
c0897e0c | 291 | int val; |
c0897e0c MA |
292 | int i; |
293 | ||
9139046c MA |
294 | val = 0; |
295 | if (ide_get_geometry(arg->idebus[0], 0, | |
296 | &cylinders, &heads, §ors) >= 0) { | |
297 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
298 | val |= 0xf0; | |
299 | } | |
300 | if (ide_get_geometry(arg->idebus[0], 1, | |
301 | &cylinders, &heads, §ors) >= 0) { | |
302 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
303 | val |= 0x0f; | |
304 | } | |
305 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
306 | |
307 | val = 0; | |
308 | for (i = 0; i < 4; i++) { | |
9139046c MA |
309 | /* NOTE: ide_get_geometry() returns the physical |
310 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
311 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
312 | geometry can be different if a translation is done. */ | |
313 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
314 | &cylinders, &heads, §ors) >= 0) { | |
315 | int translation = ide_get_bios_chs_trans(arg->idebus[i / 2], | |
316 | i % 2); | |
c0897e0c | 317 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { |
c0897e0c MA |
318 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
319 | /* No translation. */ | |
320 | translation = 0; | |
321 | } else { | |
322 | /* LBA translation. */ | |
323 | translation = 1; | |
324 | } | |
325 | } else { | |
326 | translation--; | |
327 | } | |
328 | val |= translation << (i * 2); | |
329 | } | |
330 | } | |
331 | rtc_set_memory(s, 0x39, val); | |
332 | ||
333 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
334 | } | |
335 | ||
845773ab | 336 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 337 | const char *boot_device, |
34d4260e | 338 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 339 | ISADevice *s) |
80cabfad | 340 | { |
61a8d649 | 341 | int val, nb, i; |
980bda8b | 342 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 343 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 344 | |
b0a21b53 | 345 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
346 | |
347 | /* memory size */ | |
333190eb FB |
348 | val = 640; /* base memory in K */ |
349 | rtc_set_memory(s, 0x15, val); | |
350 | rtc_set_memory(s, 0x16, val >> 8); | |
351 | ||
80cabfad FB |
352 | val = (ram_size / 1024) - 1024; |
353 | if (val > 65535) | |
354 | val = 65535; | |
b0a21b53 FB |
355 | rtc_set_memory(s, 0x17, val); |
356 | rtc_set_memory(s, 0x18, val >> 8); | |
357 | rtc_set_memory(s, 0x30, val); | |
358 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 359 | |
00f82b8a AJ |
360 | if (above_4g_mem_size) { |
361 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
362 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
363 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
364 | } | |
365 | ||
9da98861 FB |
366 | if (ram_size > (16 * 1024 * 1024)) |
367 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
368 | else | |
369 | val = 0; | |
80cabfad FB |
370 | if (val > 65535) |
371 | val = 65535; | |
b0a21b53 FB |
372 | rtc_set_memory(s, 0x34, val); |
373 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 374 | |
298e01b6 AJ |
375 | /* set the number of CPU */ |
376 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
377 | ||
6ac0e82d | 378 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 379 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
380 | exit(1); |
381 | } | |
80cabfad | 382 | |
b41a2cd1 | 383 | /* floppy type */ |
34d4260e | 384 | if (floppy) { |
34d4260e | 385 | for (i = 0; i < 2; i++) { |
61a8d649 | 386 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
387 | } |
388 | } | |
389 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
390 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 391 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 392 | |
b0a21b53 | 393 | val = 0; |
b41a2cd1 | 394 | nb = 0; |
63ffb564 | 395 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 396 | nb++; |
d288c7ba | 397 | } |
63ffb564 | 398 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 399 | nb++; |
d288c7ba | 400 | } |
80cabfad FB |
401 | switch (nb) { |
402 | case 0: | |
403 | break; | |
404 | case 1: | |
b0a21b53 | 405 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
406 | break; |
407 | case 2: | |
b0a21b53 | 408 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
409 | break; |
410 | } | |
b0a21b53 FB |
411 | val |= 0x02; /* FPU is there */ |
412 | val |= 0x04; /* PS/2 mouse installed */ | |
413 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
414 | ||
ba6c2377 | 415 | /* hard drives */ |
c0897e0c | 416 | arg.rtc_state = s; |
9139046c MA |
417 | arg.idebus[0] = idebus0; |
418 | arg.idebus[1] = idebus1; | |
c0897e0c | 419 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
420 | } |
421 | ||
4b78a802 BS |
422 | /* port 92 stuff: could be split off */ |
423 | typedef struct Port92State { | |
424 | ISADevice dev; | |
23af670e | 425 | MemoryRegion io; |
4b78a802 BS |
426 | uint8_t outport; |
427 | qemu_irq *a20_out; | |
428 | } Port92State; | |
429 | ||
430 | static void port92_write(void *opaque, uint32_t addr, uint32_t val) | |
431 | { | |
432 | Port92State *s = opaque; | |
433 | ||
434 | DPRINTF("port92: write 0x%02x\n", val); | |
435 | s->outport = val; | |
436 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
437 | if (val & 1) { | |
438 | qemu_system_reset_request(); | |
439 | } | |
440 | } | |
441 | ||
442 | static uint32_t port92_read(void *opaque, uint32_t addr) | |
443 | { | |
444 | Port92State *s = opaque; | |
445 | uint32_t ret; | |
446 | ||
447 | ret = s->outport; | |
448 | DPRINTF("port92: read 0x%02x\n", ret); | |
449 | return ret; | |
450 | } | |
451 | ||
452 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
453 | { | |
454 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
455 | ||
456 | s->a20_out = a20_out; | |
457 | } | |
458 | ||
459 | static const VMStateDescription vmstate_port92_isa = { | |
460 | .name = "port92", | |
461 | .version_id = 1, | |
462 | .minimum_version_id = 1, | |
463 | .minimum_version_id_old = 1, | |
464 | .fields = (VMStateField []) { | |
465 | VMSTATE_UINT8(outport, Port92State), | |
466 | VMSTATE_END_OF_LIST() | |
467 | } | |
468 | }; | |
469 | ||
470 | static void port92_reset(DeviceState *d) | |
471 | { | |
472 | Port92State *s = container_of(d, Port92State, dev.qdev); | |
473 | ||
474 | s->outport &= ~1; | |
475 | } | |
476 | ||
23af670e RH |
477 | static const MemoryRegionPortio port92_portio[] = { |
478 | { 0, 1, 1, .read = port92_read, .write = port92_write }, | |
479 | PORTIO_END_OF_LIST(), | |
480 | }; | |
481 | ||
482 | static const MemoryRegionOps port92_ops = { | |
483 | .old_portio = port92_portio | |
484 | }; | |
485 | ||
4b78a802 BS |
486 | static int port92_initfn(ISADevice *dev) |
487 | { | |
488 | Port92State *s = DO_UPCAST(Port92State, dev, dev); | |
489 | ||
23af670e RH |
490 | memory_region_init_io(&s->io, &port92_ops, s, "port92", 1); |
491 | isa_register_ioport(dev, &s->io, 0x92); | |
492 | ||
4b78a802 BS |
493 | s->outport = 0; |
494 | return 0; | |
495 | } | |
496 | ||
8f04ee08 AL |
497 | static void port92_class_initfn(ObjectClass *klass, void *data) |
498 | { | |
39bffca2 | 499 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
500 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
501 | ic->init = port92_initfn; | |
39bffca2 AL |
502 | dc->no_user = 1; |
503 | dc->reset = port92_reset; | |
504 | dc->vmsd = &vmstate_port92_isa; | |
8f04ee08 AL |
505 | } |
506 | ||
39bffca2 AL |
507 | static TypeInfo port92_info = { |
508 | .name = "port92", | |
509 | .parent = TYPE_ISA_DEVICE, | |
510 | .instance_size = sizeof(Port92State), | |
511 | .class_init = port92_class_initfn, | |
4b78a802 BS |
512 | }; |
513 | ||
83f7d43a | 514 | static void port92_register_types(void) |
4b78a802 | 515 | { |
39bffca2 | 516 | type_register_static(&port92_info); |
4b78a802 | 517 | } |
83f7d43a AF |
518 | |
519 | type_init(port92_register_types) | |
4b78a802 | 520 | |
956a3e6b | 521 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 522 | { |
4a8fa5dc | 523 | CPUX86State *cpu = opaque; |
e1a23744 | 524 | |
956a3e6b | 525 | /* XXX: send to all CPUs ? */ |
4b78a802 | 526 | /* XXX: add logic to handle multiple A20 line sources */ |
956a3e6b | 527 | cpu_x86_set_a20(cpu, level); |
e1a23744 FB |
528 | } |
529 | ||
80cabfad FB |
530 | /***********************************************************/ |
531 | /* Bochs BIOS debug ports */ | |
532 | ||
9596ebb7 | 533 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 534 | { |
a2f659ee FB |
535 | static const char shutdown_str[8] = "Shutdown"; |
536 | static int shutdown_index = 0; | |
3b46e624 | 537 | |
80cabfad FB |
538 | switch(addr) { |
539 | /* Bochs BIOS messages */ | |
540 | case 0x400: | |
541 | case 0x401: | |
0550f9c1 BK |
542 | /* used to be panic, now unused */ |
543 | break; | |
80cabfad FB |
544 | case 0x402: |
545 | case 0x403: | |
546 | #ifdef DEBUG_BIOS | |
547 | fprintf(stderr, "%c", val); | |
548 | #endif | |
549 | break; | |
a2f659ee FB |
550 | case 0x8900: |
551 | /* same as Bochs power off */ | |
552 | if (val == shutdown_str[shutdown_index]) { | |
553 | shutdown_index++; | |
554 | if (shutdown_index == 8) { | |
555 | shutdown_index = 0; | |
556 | qemu_system_shutdown_request(); | |
557 | } | |
558 | } else { | |
559 | shutdown_index = 0; | |
560 | } | |
561 | break; | |
80cabfad FB |
562 | |
563 | /* LGPL'ed VGA BIOS messages */ | |
564 | case 0x501: | |
565 | case 0x502: | |
4333979e | 566 | exit((val << 1) | 1); |
80cabfad FB |
567 | case 0x500: |
568 | case 0x503: | |
569 | #ifdef DEBUG_BIOS | |
570 | fprintf(stderr, "%c", val); | |
571 | #endif | |
572 | break; | |
573 | } | |
574 | } | |
575 | ||
4c5b10b7 JS |
576 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
577 | { | |
8ca209ad | 578 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
579 | struct e820_entry *entry; |
580 | ||
581 | if (index >= E820_NR_ENTRIES) | |
582 | return -EBUSY; | |
8ca209ad | 583 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 584 | |
8ca209ad AW |
585 | entry->address = cpu_to_le64(address); |
586 | entry->length = cpu_to_le64(length); | |
587 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 588 | |
8ca209ad AW |
589 | e820_table.count = cpu_to_le32(index); |
590 | return index; | |
4c5b10b7 JS |
591 | } |
592 | ||
bf483392 | 593 | static void *bochs_bios_init(void) |
80cabfad | 594 | { |
3cce6243 | 595 | void *fw_cfg; |
b6f6e3d3 AL |
596 | uint8_t *smbios_table; |
597 | size_t smbios_len; | |
11c2fd3e AL |
598 | uint64_t *numa_fw_cfg; |
599 | int i, j; | |
3cce6243 | 600 | |
b41a2cd1 FB |
601 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
602 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
603 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
604 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 605 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 | 606 | |
4333979e | 607 | register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
608 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
609 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
610 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
611 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
612 | |
613 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 614 | |
3cce6243 | 615 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 616 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
617 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
618 | acpi_tables_len); | |
9b5b76d4 | 619 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 AL |
620 | |
621 | smbios_table = smbios_get_table(&smbios_len); | |
622 | if (smbios_table) | |
623 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
624 | smbios_table, smbios_len); | |
4c5b10b7 JS |
625 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
626 | sizeof(struct e820_table)); | |
11c2fd3e | 627 | |
40ac17cd GN |
628 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
629 | sizeof(struct hpet_fw_config)); | |
11c2fd3e AL |
630 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
631 | * of nodes, one word for each VCPU->node and one word for each node to | |
632 | * hold the amount of memory. | |
633 | */ | |
991dfefd | 634 | numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); |
11c2fd3e | 635 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 636 | for (i = 0; i < max_cpus; i++) { |
11c2fd3e AL |
637 | for (j = 0; j < nb_numa_nodes; j++) { |
638 | if (node_cpumask[j] & (1 << i)) { | |
639 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
640 | break; | |
641 | } | |
642 | } | |
643 | } | |
644 | for (i = 0; i < nb_numa_nodes; i++) { | |
991dfefd | 645 | numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); |
11c2fd3e AL |
646 | } |
647 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
991dfefd | 648 | (1 + max_cpus + nb_numa_nodes) * 8); |
bf483392 AG |
649 | |
650 | return fw_cfg; | |
80cabfad FB |
651 | } |
652 | ||
642a4f96 TS |
653 | static long get_file_size(FILE *f) |
654 | { | |
655 | long where, size; | |
656 | ||
657 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
658 | ||
659 | where = ftell(f); | |
660 | fseek(f, 0, SEEK_END); | |
661 | size = ftell(f); | |
662 | fseek(f, where, SEEK_SET); | |
663 | ||
664 | return size; | |
665 | } | |
666 | ||
f16408df | 667 | static void load_linux(void *fw_cfg, |
4fc9af53 | 668 | const char *kernel_filename, |
642a4f96 | 669 | const char *initrd_filename, |
e6ade764 | 670 | const char *kernel_cmdline, |
45a50b16 | 671 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
672 | { |
673 | uint16_t protocol; | |
5cea8590 | 674 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 675 | uint32_t initrd_max; |
57a46d05 | 676 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 677 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 678 | FILE *f; |
bf4e5d92 | 679 | char *vmode; |
642a4f96 TS |
680 | |
681 | /* Align to 16 bytes as a paranoia measure */ | |
682 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
683 | ||
684 | /* load the kernel header */ | |
685 | f = fopen(kernel_filename, "rb"); | |
686 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
687 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
688 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
689 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
690 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
691 | exit(1); |
692 | } | |
693 | ||
694 | /* kernel protocol version */ | |
bc4edd79 | 695 | #if 0 |
642a4f96 | 696 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 697 | #endif |
642a4f96 TS |
698 | if (ldl_p(header+0x202) == 0x53726448) |
699 | protocol = lduw_p(header+0x206); | |
f16408df AG |
700 | else { |
701 | /* This looks like a multiboot kernel. If it is, let's stop | |
702 | treating it like a Linux kernel. */ | |
52001445 AL |
703 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
704 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 705 | return; |
642a4f96 | 706 | protocol = 0; |
f16408df | 707 | } |
642a4f96 TS |
708 | |
709 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
710 | /* Low kernel */ | |
a37af289 BS |
711 | real_addr = 0x90000; |
712 | cmdline_addr = 0x9a000 - cmdline_size; | |
713 | prot_addr = 0x10000; | |
642a4f96 TS |
714 | } else if (protocol < 0x202) { |
715 | /* High but ancient kernel */ | |
a37af289 BS |
716 | real_addr = 0x90000; |
717 | cmdline_addr = 0x9a000 - cmdline_size; | |
718 | prot_addr = 0x100000; | |
642a4f96 TS |
719 | } else { |
720 | /* High and recent kernel */ | |
a37af289 BS |
721 | real_addr = 0x10000; |
722 | cmdline_addr = 0x20000; | |
723 | prot_addr = 0x100000; | |
642a4f96 TS |
724 | } |
725 | ||
bc4edd79 | 726 | #if 0 |
642a4f96 | 727 | fprintf(stderr, |
526ccb7a AZ |
728 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
729 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
730 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
731 | real_addr, |
732 | cmdline_addr, | |
733 | prot_addr); | |
bc4edd79 | 734 | #endif |
642a4f96 TS |
735 | |
736 | /* highest address for loading the initrd */ | |
737 | if (protocol >= 0x203) | |
738 | initrd_max = ldl_p(header+0x22c); | |
739 | else | |
740 | initrd_max = 0x37ffffff; | |
741 | ||
e6ade764 GC |
742 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
743 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 744 | |
57a46d05 AG |
745 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
746 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
747 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
748 | (uint8_t*)strdup(kernel_cmdline), | |
749 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
750 | |
751 | if (protocol >= 0x202) { | |
a37af289 | 752 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
753 | } else { |
754 | stw_p(header+0x20, 0xA33F); | |
755 | stw_p(header+0x22, cmdline_addr-real_addr); | |
756 | } | |
757 | ||
bf4e5d92 PT |
758 | /* handle vga= parameter */ |
759 | vmode = strstr(kernel_cmdline, "vga="); | |
760 | if (vmode) { | |
761 | unsigned int video_mode; | |
762 | /* skip "vga=" */ | |
763 | vmode += 4; | |
764 | if (!strncmp(vmode, "normal", 6)) { | |
765 | video_mode = 0xffff; | |
766 | } else if (!strncmp(vmode, "ext", 3)) { | |
767 | video_mode = 0xfffe; | |
768 | } else if (!strncmp(vmode, "ask", 3)) { | |
769 | video_mode = 0xfffd; | |
770 | } else { | |
771 | video_mode = strtol(vmode, NULL, 0); | |
772 | } | |
773 | stw_p(header+0x1fa, video_mode); | |
774 | } | |
775 | ||
642a4f96 | 776 | /* loader type */ |
5cbdb3a3 | 777 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
778 | If this code is substantially changed, you may want to consider |
779 | incrementing the revision. */ | |
780 | if (protocol >= 0x200) | |
781 | header[0x210] = 0xB0; | |
782 | ||
783 | /* heap */ | |
784 | if (protocol >= 0x201) { | |
785 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
786 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
787 | } | |
788 | ||
789 | /* load initrd */ | |
790 | if (initrd_filename) { | |
791 | if (protocol < 0x200) { | |
792 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
793 | exit(1); | |
794 | } | |
795 | ||
45a50b16 | 796 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
797 | if (initrd_size < 0) { |
798 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
799 | initrd_filename); | |
800 | exit(1); | |
801 | } | |
802 | ||
45a50b16 | 803 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 804 | |
7267c094 | 805 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
806 | load_image(initrd_filename, initrd_data); |
807 | ||
808 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
809 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
810 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 811 | |
a37af289 | 812 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
813 | stl_p(header+0x21c, initrd_size); |
814 | } | |
815 | ||
45a50b16 | 816 | /* load kernel and setup */ |
642a4f96 TS |
817 | setup_size = header[0x1f1]; |
818 | if (setup_size == 0) | |
819 | setup_size = 4; | |
642a4f96 | 820 | setup_size = (setup_size+1)*512; |
45a50b16 | 821 | kernel_size -= setup_size; |
642a4f96 | 822 | |
7267c094 AL |
823 | setup = g_malloc(setup_size); |
824 | kernel = g_malloc(kernel_size); | |
45a50b16 | 825 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
826 | if (fread(setup, 1, setup_size, f) != setup_size) { |
827 | fprintf(stderr, "fread() failed\n"); | |
828 | exit(1); | |
829 | } | |
830 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
831 | fprintf(stderr, "fread() failed\n"); | |
832 | exit(1); | |
833 | } | |
642a4f96 | 834 | fclose(f); |
45a50b16 | 835 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
836 | |
837 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
838 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
839 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
840 | ||
841 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
842 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
843 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
844 | ||
2e55e842 GN |
845 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
846 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 847 | nb_option_roms++; |
642a4f96 TS |
848 | } |
849 | ||
b41a2cd1 FB |
850 | #define NE2000_NB_MAX 6 |
851 | ||
675d6f82 BS |
852 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
853 | 0x280, 0x380 }; | |
854 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 855 | |
675d6f82 BS |
856 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
857 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 858 | |
48a18b3c | 859 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
860 | { |
861 | static int nb_ne2k = 0; | |
862 | ||
863 | if (nb_ne2k == NE2000_NB_MAX) | |
864 | return; | |
48a18b3c | 865 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 866 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
867 | nb_ne2k++; |
868 | } | |
869 | ||
4a8fa5dc | 870 | int cpu_is_bsp(CPUX86State *env) |
678e12cc | 871 | { |
6cb2996c JK |
872 | /* We hard-wire the BSP to the first CPU. */ |
873 | return env->cpu_index == 0; | |
678e12cc GN |
874 | } |
875 | ||
92a16d7a | 876 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
877 | { |
878 | if (cpu_single_env) { | |
879 | return cpu_single_env->apic_state; | |
880 | } else { | |
881 | return NULL; | |
882 | } | |
883 | } | |
884 | ||
92a16d7a BS |
885 | static DeviceState *apic_init(void *env, uint8_t apic_id) |
886 | { | |
887 | DeviceState *dev; | |
92a16d7a BS |
888 | static int apic_mapped; |
889 | ||
3d4b2649 | 890 | if (kvm_irqchip_in_kernel()) { |
680c1c6f | 891 | dev = qdev_create(NULL, "kvm-apic"); |
9468e9c4 WL |
892 | } else if (xen_enabled()) { |
893 | dev = qdev_create(NULL, "xen-apic"); | |
680c1c6f JK |
894 | } else { |
895 | dev = qdev_create(NULL, "apic"); | |
896 | } | |
9468e9c4 | 897 | |
92a16d7a BS |
898 | qdev_prop_set_uint8(dev, "id", apic_id); |
899 | qdev_prop_set_ptr(dev, "cpu_env", env); | |
900 | qdev_init_nofail(dev); | |
92a16d7a BS |
901 | |
902 | /* XXX: mapping more APICs at the same memory location */ | |
903 | if (apic_mapped == 0) { | |
904 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
905 | on the global memory bus. */ | |
906 | /* XXX: what if the base changes? */ | |
680c1c6f | 907 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE); |
92a16d7a BS |
908 | apic_mapped = 1; |
909 | } | |
910 | ||
92a16d7a BS |
911 | return dev; |
912 | } | |
913 | ||
845773ab | 914 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 915 | { |
4a8fa5dc | 916 | CPUX86State *s = opaque; |
53b67b30 BS |
917 | |
918 | if (level) { | |
919 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
920 | } | |
921 | } | |
922 | ||
427bd8d6 | 923 | static void pc_cpu_reset(void *opaque) |
0e26b7b8 | 924 | { |
e5fe7a34 AF |
925 | X86CPU *cpu = opaque; |
926 | CPUX86State *env = &cpu->env; | |
0e26b7b8 | 927 | |
e5fe7a34 | 928 | cpu_reset(CPU(cpu)); |
427bd8d6 | 929 | env->halted = !cpu_is_bsp(env); |
0e26b7b8 BS |
930 | } |
931 | ||
608911ac | 932 | static X86CPU *pc_new_cpu(const char *cpu_model) |
3a31f36a | 933 | { |
608911ac | 934 | X86CPU *cpu; |
4a8fa5dc | 935 | CPUX86State *env; |
3a31f36a | 936 | |
608911ac AF |
937 | cpu = cpu_x86_init(cpu_model); |
938 | if (cpu == NULL) { | |
3a31f36a JK |
939 | fprintf(stderr, "Unable to find x86 CPU definition\n"); |
940 | exit(1); | |
941 | } | |
608911ac | 942 | env = &cpu->env; |
3a31f36a | 943 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
0e26b7b8 BS |
944 | env->apic_state = apic_init(env, env->cpuid_apic_id); |
945 | } | |
e5fe7a34 AF |
946 | qemu_register_reset(pc_cpu_reset, cpu); |
947 | pc_cpu_reset(cpu); | |
608911ac | 948 | return cpu; |
3a31f36a JK |
949 | } |
950 | ||
845773ab | 951 | void pc_cpus_init(const char *cpu_model) |
70166477 IY |
952 | { |
953 | int i; | |
954 | ||
955 | /* init CPUs */ | |
956 | if (cpu_model == NULL) { | |
957 | #ifdef TARGET_X86_64 | |
958 | cpu_model = "qemu64"; | |
959 | #else | |
960 | cpu_model = "qemu32"; | |
961 | #endif | |
962 | } | |
963 | ||
964 | for(i = 0; i < smp_cpus; i++) { | |
965 | pc_new_cpu(cpu_model); | |
966 | } | |
967 | } | |
968 | ||
459ae5ea | 969 | void *pc_memory_init(MemoryRegion *system_memory, |
4aa63af1 | 970 | const char *kernel_filename, |
845773ab IY |
971 | const char *kernel_cmdline, |
972 | const char *initrd_filename, | |
e0e7e67b | 973 | ram_addr_t below_4g_mem_size, |
ae0a5466 | 974 | ram_addr_t above_4g_mem_size, |
4463aee6 | 975 | MemoryRegion *rom_memory, |
ae0a5466 | 976 | MemoryRegion **ram_memory) |
80cabfad | 977 | { |
cbc5b5f3 JJ |
978 | int linux_boot, i; |
979 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 980 | MemoryRegion *ram_below_4g, *ram_above_4g; |
81a204e4 | 981 | void *fw_cfg; |
d592d303 | 982 | |
80cabfad FB |
983 | linux_boot = (kernel_filename != NULL); |
984 | ||
00cb2a99 | 985 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 986 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
987 | * with older qemus that used qemu_ram_alloc(). |
988 | */ | |
7267c094 | 989 | ram = g_malloc(sizeof(*ram)); |
c5705a77 | 990 | memory_region_init_ram(ram, "pc.ram", |
00cb2a99 | 991 | below_4g_mem_size + above_4g_mem_size); |
c5705a77 | 992 | vmstate_register_ram_global(ram); |
ae0a5466 | 993 | *ram_memory = ram; |
7267c094 | 994 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
00cb2a99 AK |
995 | memory_region_init_alias(ram_below_4g, "ram-below-4g", ram, |
996 | 0, below_4g_mem_size); | |
997 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
bbe80adf | 998 | if (above_4g_mem_size > 0) { |
7267c094 | 999 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
00cb2a99 AK |
1000 | memory_region_init_alias(ram_above_4g, "ram-above-4g", ram, |
1001 | below_4g_mem_size, above_4g_mem_size); | |
1002 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1003 | ram_above_4g); | |
bbe80adf | 1004 | } |
82b36dc3 | 1005 | |
cbc5b5f3 JJ |
1006 | |
1007 | /* Initialize PC system firmware */ | |
1008 | pc_system_firmware_init(rom_memory); | |
00cb2a99 | 1009 | |
7267c094 | 1010 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
c5705a77 AK |
1011 | memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE); |
1012 | vmstate_register_ram_global(option_rom_mr); | |
4463aee6 | 1013 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1014 | PC_ROM_MIN_VGA, |
1015 | option_rom_mr, | |
1016 | 1); | |
f753ff16 | 1017 | |
bf483392 | 1018 | fw_cfg = bochs_bios_init(); |
8832cb80 | 1019 | rom_set_fw(fw_cfg); |
1d108d97 | 1020 | |
f753ff16 | 1021 | if (linux_boot) { |
81a204e4 | 1022 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
1023 | } |
1024 | ||
1025 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1026 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1027 | } |
459ae5ea | 1028 | return fw_cfg; |
3d53f5c3 IY |
1029 | } |
1030 | ||
845773ab IY |
1031 | qemu_irq *pc_allocate_cpu_irq(void) |
1032 | { | |
1033 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1034 | } | |
1035 | ||
48a18b3c | 1036 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1037 | { |
ad6d45fa AL |
1038 | DeviceState *dev = NULL; |
1039 | ||
765d7908 IY |
1040 | if (cirrus_vga_enabled) { |
1041 | if (pci_bus) { | |
ad6d45fa | 1042 | dev = pci_cirrus_vga_init(pci_bus); |
765d7908 | 1043 | } else { |
3d402831 | 1044 | dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev; |
765d7908 IY |
1045 | } |
1046 | } else if (vmsvga_enabled) { | |
7ba7e49e | 1047 | if (pci_bus) { |
ad6d45fa | 1048 | dev = pci_vmsvga_init(pci_bus); |
7ba7e49e | 1049 | } else { |
765d7908 | 1050 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); |
7ba7e49e | 1051 | } |
a19cbfb3 GH |
1052 | #ifdef CONFIG_SPICE |
1053 | } else if (qxl_enabled) { | |
ad6d45fa AL |
1054 | if (pci_bus) { |
1055 | dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev; | |
1056 | } else { | |
a19cbfb3 | 1057 | fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__); |
ad6d45fa | 1058 | } |
a19cbfb3 | 1059 | #endif |
765d7908 IY |
1060 | } else if (std_vga_enabled) { |
1061 | if (pci_bus) { | |
ad6d45fa | 1062 | dev = pci_vga_init(pci_bus); |
765d7908 | 1063 | } else { |
48a18b3c | 1064 | dev = isa_vga_init(isa_bus); |
765d7908 IY |
1065 | } |
1066 | } | |
ad6d45fa AL |
1067 | |
1068 | return dev; | |
765d7908 IY |
1069 | } |
1070 | ||
4556bd8b BS |
1071 | static void cpu_request_exit(void *opaque, int irq, int level) |
1072 | { | |
4a8fa5dc | 1073 | CPUX86State *env = cpu_single_env; |
4556bd8b BS |
1074 | |
1075 | if (env && level) { | |
1076 | cpu_exit(env); | |
1077 | } | |
1078 | } | |
1079 | ||
48a18b3c | 1080 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1081 | ISADevice **rtc_state, |
34d4260e | 1082 | ISADevice **floppy, |
1611977c | 1083 | bool no_vmport) |
ffe513da IY |
1084 | { |
1085 | int i; | |
1086 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1087 | DeviceState *hpet = NULL; |
1088 | int pit_isa_irq = 0; | |
1089 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1090 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1091 | qemu_irq *a20_line; |
c2d8d311 | 1092 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 1093 | qemu_irq *cpu_exit_irq; |
ffe513da IY |
1094 | |
1095 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
1096 | ||
1097 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
1098 | ||
5d17c0d2 JK |
1099 | /* |
1100 | * Check if an HPET shall be created. | |
1101 | * | |
1102 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1103 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1104 | */ | |
1105 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
ce967e2f | 1106 | hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
822557eb | 1107 | |
dd703b99 | 1108 | if (hpet) { |
b881fbe9 JK |
1109 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1110 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); | |
dd703b99 | 1111 | } |
ce967e2f JK |
1112 | pit_isa_irq = -1; |
1113 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1114 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1115 | } |
ffe513da | 1116 | } |
48a18b3c | 1117 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1118 | |
1119 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1120 | ||
c2d8d311 SS |
1121 | if (!xen_enabled()) { |
1122 | if (kvm_irqchip_in_kernel()) { | |
1123 | pit = kvm_pit_init(isa_bus, 0x40); | |
1124 | } else { | |
1125 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1126 | } | |
1127 | if (hpet) { | |
1128 | /* connect PIT to output control line of the HPET */ | |
1129 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); | |
1130 | } | |
1131 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1132 | } |
ffe513da IY |
1133 | |
1134 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1135 | if (serial_hds[i]) { | |
48a18b3c | 1136 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1137 | } |
1138 | } | |
1139 | ||
1140 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1141 | if (parallel_hds[i]) { | |
48a18b3c | 1142 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1143 | } |
1144 | } | |
1145 | ||
4b78a802 | 1146 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1147 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1148 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1149 | if (!no_vmport) { |
48a18b3c HP |
1150 | vmport_init(isa_bus); |
1151 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1152 | } else { |
1153 | vmmouse = NULL; | |
1154 | } | |
86d86414 BS |
1155 | if (vmmouse) { |
1156 | qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042); | |
43f20196 | 1157 | qdev_init_nofail(&vmmouse->qdev); |
86d86414 | 1158 | } |
48a18b3c | 1159 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1160 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1161 | |
4556bd8b BS |
1162 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1163 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1164 | |
1165 | for(i = 0; i < MAX_FD; i++) { | |
1166 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1167 | } | |
48a18b3c | 1168 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1169 | } |
1170 | ||
845773ab | 1171 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1172 | { |
1173 | int max_bus; | |
1174 | int bus; | |
1175 | ||
1176 | max_bus = drive_get_max_bus(IF_SCSI); | |
1177 | for (bus = 0; bus <= max_bus; bus++) { | |
1178 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1179 | } | |
1180 | } |