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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
aa28b9bf | 26 | #include "apic.h" |
87ecb68b | 27 | #include "fdc.h" |
c0897e0c | 28 | #include "ide.h" |
87ecb68b | 29 | #include "pci.h" |
18e08a55 | 30 | #include "vmware_vga.h" |
376253ec | 31 | #include "monitor.h" |
3cce6243 | 32 | #include "fw_cfg.h" |
16b29ae1 | 33 | #include "hpet_emul.h" |
b6f6e3d3 | 34 | #include "smbios.h" |
ca20cf32 BS |
35 | #include "loader.h" |
36 | #include "elf.h" | |
52001445 | 37 | #include "multiboot.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
92a16d7a | 39 | #include "msix.h" |
822557eb | 40 | #include "sysbus.h" |
666daa68 | 41 | #include "sysemu.h" |
2446333c | 42 | #include "blockdev.h" |
80cabfad | 43 | |
b41a2cd1 FB |
44 | /* output Bochs bios info messages */ |
45 | //#define DEBUG_BIOS | |
46 | ||
471fd342 BS |
47 | /* debug PC/ISA interrupts */ |
48 | //#define DEBUG_IRQ | |
49 | ||
50 | #ifdef DEBUG_IRQ | |
51 | #define DPRINTF(fmt, ...) \ | |
52 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
53 | #else | |
54 | #define DPRINTF(fmt, ...) | |
55 | #endif | |
56 | ||
80cabfad | 57 | #define BIOS_FILENAME "bios.bin" |
80cabfad | 58 | |
7fb4fdcf AZ |
59 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
60 | ||
a80274c3 PB |
61 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
62 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 63 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 64 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 65 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 66 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 67 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 68 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 69 | |
92a16d7a BS |
70 | #define MSI_ADDR_BASE 0xfee00000 |
71 | ||
4c5b10b7 JS |
72 | #define E820_NR_ENTRIES 16 |
73 | ||
74 | struct e820_entry { | |
75 | uint64_t address; | |
76 | uint64_t length; | |
77 | uint32_t type; | |
67d4b0c1 | 78 | } __attribute((__packed__, __aligned__(4))); |
4c5b10b7 JS |
79 | |
80 | struct e820_table { | |
81 | uint32_t count; | |
82 | struct e820_entry entry[E820_NR_ENTRIES]; | |
67d4b0c1 | 83 | } __attribute((__packed__, __aligned__(4))); |
4c5b10b7 JS |
84 | |
85 | static struct e820_table e820_table; | |
86 | ||
845773ab | 87 | void isa_irq_handler(void *opaque, int n, int level) |
1452411b AK |
88 | { |
89 | IsaIrqState *isa = (IsaIrqState *)opaque; | |
90 | ||
471fd342 | 91 | DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n); |
1632dc6a AK |
92 | if (n < 16) { |
93 | qemu_set_irq(isa->i8259[n], level); | |
94 | } | |
2c8d9340 GH |
95 | if (isa->ioapic) |
96 | qemu_set_irq(isa->ioapic[n], level); | |
1632dc6a | 97 | }; |
1452411b | 98 | |
b41a2cd1 | 99 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
100 | { |
101 | } | |
102 | ||
f929aad6 | 103 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 104 | static qemu_irq ferr_irq; |
8e78eb28 IY |
105 | |
106 | void pc_register_ferr_irq(qemu_irq irq) | |
107 | { | |
108 | ferr_irq = irq; | |
109 | } | |
110 | ||
f929aad6 FB |
111 | /* XXX: add IGNNE support */ |
112 | void cpu_set_ferr(CPUX86State *s) | |
113 | { | |
d537cf6c | 114 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
115 | } |
116 | ||
117 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
118 | { | |
d537cf6c | 119 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
120 | } |
121 | ||
28ab0e2e | 122 | /* TSC handling */ |
28ab0e2e FB |
123 | uint64_t cpu_get_tsc(CPUX86State *env) |
124 | { | |
4a1418e0 | 125 | return cpu_get_ticks(); |
28ab0e2e FB |
126 | } |
127 | ||
a5954d5c | 128 | /* SMM support */ |
f885f1ea IY |
129 | |
130 | static cpu_set_smm_t smm_set; | |
131 | static void *smm_arg; | |
132 | ||
133 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
134 | { | |
135 | assert(smm_set == NULL); | |
136 | assert(smm_arg == NULL); | |
137 | smm_set = callback; | |
138 | smm_arg = arg; | |
139 | } | |
140 | ||
a5954d5c FB |
141 | void cpu_smm_update(CPUState *env) |
142 | { | |
f885f1ea IY |
143 | if (smm_set && smm_arg && env == first_cpu) |
144 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); | |
a5954d5c FB |
145 | } |
146 | ||
147 | ||
3de388f6 FB |
148 | /* IRQ handling */ |
149 | int cpu_get_pic_interrupt(CPUState *env) | |
150 | { | |
151 | int intno; | |
152 | ||
cf6d64bf | 153 | intno = apic_get_interrupt(env->apic_state); |
3de388f6 FB |
154 | if (intno >= 0) { |
155 | /* set irq request if a PIC irq is still pending */ | |
156 | /* XXX: improve that */ | |
5fafdf24 | 157 | pic_update_irq(isa_pic); |
3de388f6 FB |
158 | return intno; |
159 | } | |
3de388f6 | 160 | /* read the irq from the PIC */ |
cf6d64bf | 161 | if (!apic_accept_pic_intr(env->apic_state)) { |
0e21e12b | 162 | return -1; |
cf6d64bf | 163 | } |
0e21e12b | 164 | |
3de388f6 FB |
165 | intno = pic_read_irq(isa_pic); |
166 | return intno; | |
167 | } | |
168 | ||
d537cf6c | 169 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 170 | { |
a5b38b51 AJ |
171 | CPUState *env = first_cpu; |
172 | ||
471fd342 | 173 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
d5529471 AJ |
174 | if (env->apic_state) { |
175 | while (env) { | |
cf6d64bf BS |
176 | if (apic_accept_pic_intr(env->apic_state)) { |
177 | apic_deliver_pic_intr(env->apic_state, level); | |
178 | } | |
d5529471 AJ |
179 | env = env->next_cpu; |
180 | } | |
181 | } else { | |
b614106a AJ |
182 | if (level) |
183 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
184 | else | |
185 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 186 | } |
3de388f6 FB |
187 | } |
188 | ||
b0a21b53 FB |
189 | /* PC cmos mappings */ |
190 | ||
80cabfad FB |
191 | #define REG_EQUIPMENT_BYTE 0x14 |
192 | ||
777428f2 FB |
193 | static int cmos_get_fd_drive_type(int fd0) |
194 | { | |
195 | int val; | |
196 | ||
197 | switch (fd0) { | |
198 | case 0: | |
199 | /* 1.44 Mb 3"5 drive */ | |
200 | val = 4; | |
201 | break; | |
202 | case 1: | |
203 | /* 2.88 Mb 3"5 drive */ | |
204 | val = 5; | |
205 | break; | |
206 | case 2: | |
207 | /* 1.2 Mb 5"5 drive */ | |
208 | val = 2; | |
209 | break; | |
210 | default: | |
211 | val = 0; | |
212 | break; | |
213 | } | |
214 | return val; | |
215 | } | |
216 | ||
ec2654fb | 217 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, |
1d914fa0 | 218 | ISADevice *s) |
ba6c2377 | 219 | { |
ba6c2377 FB |
220 | int cylinders, heads, sectors; |
221 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
222 | rtc_set_memory(s, type_ofs, 47); | |
223 | rtc_set_memory(s, info_ofs, cylinders); | |
224 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
225 | rtc_set_memory(s, info_ofs + 2, heads); | |
226 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
227 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
228 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
229 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
230 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
231 | rtc_set_memory(s, info_ofs + 8, sectors); | |
232 | } | |
233 | ||
6ac0e82d AZ |
234 | /* convert boot_device letter to something recognizable by the bios */ |
235 | static int boot_device2nibble(char boot_device) | |
236 | { | |
237 | switch(boot_device) { | |
238 | case 'a': | |
239 | case 'b': | |
240 | return 0x01; /* floppy boot */ | |
241 | case 'c': | |
242 | return 0x02; /* hard drive boot */ | |
243 | case 'd': | |
244 | return 0x03; /* CD-ROM boot */ | |
245 | case 'n': | |
246 | return 0x04; /* Network boot */ | |
247 | } | |
248 | return 0; | |
249 | } | |
250 | ||
1d914fa0 | 251 | static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
0ecdffbb AJ |
252 | { |
253 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
254 | int nbds, bds[3] = { 0, }; |
255 | int i; | |
256 | ||
257 | nbds = strlen(boot_device); | |
258 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 259 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
260 | return(1); |
261 | } | |
262 | for (i = 0; i < nbds; i++) { | |
263 | bds[i] = boot_device2nibble(boot_device[i]); | |
264 | if (bds[i] == 0) { | |
1ecda02b MA |
265 | error_report("Invalid boot device for PC: '%c'", |
266 | boot_device[i]); | |
0ecdffbb AJ |
267 | return(1); |
268 | } | |
269 | } | |
270 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 271 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
272 | return(0); |
273 | } | |
274 | ||
d9346e81 MA |
275 | static int pc_boot_set(void *opaque, const char *boot_device) |
276 | { | |
277 | return set_boot_dev(opaque, boot_device, 0); | |
278 | } | |
279 | ||
c0897e0c MA |
280 | typedef struct pc_cmos_init_late_arg { |
281 | ISADevice *rtc_state; | |
282 | BusState *idebus0, *idebus1; | |
283 | } pc_cmos_init_late_arg; | |
284 | ||
285 | static void pc_cmos_init_late(void *opaque) | |
286 | { | |
287 | pc_cmos_init_late_arg *arg = opaque; | |
288 | ISADevice *s = arg->rtc_state; | |
289 | int val; | |
290 | BlockDriverState *hd_table[4]; | |
291 | int i; | |
292 | ||
293 | ide_get_bs(hd_table, arg->idebus0); | |
294 | ide_get_bs(hd_table + 2, arg->idebus1); | |
295 | ||
296 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
297 | if (hd_table[0]) | |
298 | cmos_init_hd(0x19, 0x1b, hd_table[0], s); | |
299 | if (hd_table[1]) | |
300 | cmos_init_hd(0x1a, 0x24, hd_table[1], s); | |
301 | ||
302 | val = 0; | |
303 | for (i = 0; i < 4; i++) { | |
304 | if (hd_table[i]) { | |
305 | int cylinders, heads, sectors, translation; | |
306 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
307 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
308 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
309 | geometry can be different if a translation is done. */ | |
310 | translation = bdrv_get_translation_hint(hd_table[i]); | |
311 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
312 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
313 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
314 | /* No translation. */ | |
315 | translation = 0; | |
316 | } else { | |
317 | /* LBA translation. */ | |
318 | translation = 1; | |
319 | } | |
320 | } else { | |
321 | translation--; | |
322 | } | |
323 | val |= translation << (i * 2); | |
324 | } | |
325 | } | |
326 | rtc_set_memory(s, 0x39, val); | |
327 | ||
328 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
329 | } | |
330 | ||
845773ab | 331 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c MA |
332 | const char *boot_device, |
333 | BusState *idebus0, BusState *idebus1, | |
1d914fa0 | 334 | FDCtrl *floppy_controller, ISADevice *s) |
80cabfad | 335 | { |
80cabfad | 336 | int val; |
b41a2cd1 | 337 | int fd0, fd1, nb; |
c0897e0c | 338 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 339 | |
b0a21b53 | 340 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
341 | |
342 | /* memory size */ | |
333190eb FB |
343 | val = 640; /* base memory in K */ |
344 | rtc_set_memory(s, 0x15, val); | |
345 | rtc_set_memory(s, 0x16, val >> 8); | |
346 | ||
80cabfad FB |
347 | val = (ram_size / 1024) - 1024; |
348 | if (val > 65535) | |
349 | val = 65535; | |
b0a21b53 FB |
350 | rtc_set_memory(s, 0x17, val); |
351 | rtc_set_memory(s, 0x18, val >> 8); | |
352 | rtc_set_memory(s, 0x30, val); | |
353 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 354 | |
00f82b8a AJ |
355 | if (above_4g_mem_size) { |
356 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
357 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
358 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
359 | } | |
360 | ||
9da98861 FB |
361 | if (ram_size > (16 * 1024 * 1024)) |
362 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
363 | else | |
364 | val = 0; | |
80cabfad FB |
365 | if (val > 65535) |
366 | val = 65535; | |
b0a21b53 FB |
367 | rtc_set_memory(s, 0x34, val); |
368 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 369 | |
298e01b6 AJ |
370 | /* set the number of CPU */ |
371 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
372 | ||
6ac0e82d | 373 | /* set boot devices, and disable floppy signature check if requested */ |
d9346e81 | 374 | if (set_boot_dev(s, boot_device, fd_bootchk)) { |
28c5af54 JM |
375 | exit(1); |
376 | } | |
80cabfad | 377 | |
b41a2cd1 FB |
378 | /* floppy type */ |
379 | ||
baca51fa FB |
380 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
381 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 382 | |
777428f2 | 383 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 384 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 385 | |
b0a21b53 | 386 | val = 0; |
b41a2cd1 | 387 | nb = 0; |
80cabfad FB |
388 | if (fd0 < 3) |
389 | nb++; | |
390 | if (fd1 < 3) | |
391 | nb++; | |
392 | switch (nb) { | |
393 | case 0: | |
394 | break; | |
395 | case 1: | |
b0a21b53 | 396 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
397 | break; |
398 | case 2: | |
b0a21b53 | 399 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
400 | break; |
401 | } | |
b0a21b53 FB |
402 | val |= 0x02; /* FPU is there */ |
403 | val |= 0x04; /* PS/2 mouse installed */ | |
404 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
405 | ||
ba6c2377 | 406 | /* hard drives */ |
c0897e0c MA |
407 | arg.rtc_state = s; |
408 | arg.idebus0 = idebus0; | |
409 | arg.idebus1 = idebus1; | |
410 | qemu_register_reset(pc_cmos_init_late, &arg); | |
80cabfad FB |
411 | } |
412 | ||
956a3e6b | 413 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 414 | { |
956a3e6b | 415 | CPUState *cpu = opaque; |
e1a23744 | 416 | |
956a3e6b BS |
417 | /* XXX: send to all CPUs ? */ |
418 | cpu_x86_set_a20(cpu, level); | |
e1a23744 FB |
419 | } |
420 | ||
80cabfad FB |
421 | /***********************************************************/ |
422 | /* Bochs BIOS debug ports */ | |
423 | ||
9596ebb7 | 424 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 425 | { |
a2f659ee FB |
426 | static const char shutdown_str[8] = "Shutdown"; |
427 | static int shutdown_index = 0; | |
3b46e624 | 428 | |
80cabfad FB |
429 | switch(addr) { |
430 | /* Bochs BIOS messages */ | |
431 | case 0x400: | |
432 | case 0x401: | |
433 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
434 | exit(1); | |
435 | case 0x402: | |
436 | case 0x403: | |
437 | #ifdef DEBUG_BIOS | |
438 | fprintf(stderr, "%c", val); | |
439 | #endif | |
440 | break; | |
a2f659ee FB |
441 | case 0x8900: |
442 | /* same as Bochs power off */ | |
443 | if (val == shutdown_str[shutdown_index]) { | |
444 | shutdown_index++; | |
445 | if (shutdown_index == 8) { | |
446 | shutdown_index = 0; | |
447 | qemu_system_shutdown_request(); | |
448 | } | |
449 | } else { | |
450 | shutdown_index = 0; | |
451 | } | |
452 | break; | |
80cabfad FB |
453 | |
454 | /* LGPL'ed VGA BIOS messages */ | |
455 | case 0x501: | |
456 | case 0x502: | |
457 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
458 | exit(1); | |
459 | case 0x500: | |
460 | case 0x503: | |
461 | #ifdef DEBUG_BIOS | |
462 | fprintf(stderr, "%c", val); | |
463 | #endif | |
464 | break; | |
465 | } | |
466 | } | |
467 | ||
4c5b10b7 JS |
468 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
469 | { | |
8ca209ad | 470 | int index = le32_to_cpu(e820_table.count); |
4c5b10b7 JS |
471 | struct e820_entry *entry; |
472 | ||
473 | if (index >= E820_NR_ENTRIES) | |
474 | return -EBUSY; | |
8ca209ad | 475 | entry = &e820_table.entry[index++]; |
4c5b10b7 | 476 | |
8ca209ad AW |
477 | entry->address = cpu_to_le64(address); |
478 | entry->length = cpu_to_le64(length); | |
479 | entry->type = cpu_to_le32(type); | |
4c5b10b7 | 480 | |
8ca209ad AW |
481 | e820_table.count = cpu_to_le32(index); |
482 | return index; | |
4c5b10b7 JS |
483 | } |
484 | ||
bf483392 | 485 | static void *bochs_bios_init(void) |
80cabfad | 486 | { |
3cce6243 | 487 | void *fw_cfg; |
b6f6e3d3 AL |
488 | uint8_t *smbios_table; |
489 | size_t smbios_len; | |
11c2fd3e AL |
490 | uint64_t *numa_fw_cfg; |
491 | int i, j; | |
3cce6243 | 492 | |
b41a2cd1 FB |
493 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
494 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
495 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
496 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 497 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
498 | |
499 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
500 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
501 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
502 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
503 | |
504 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
bf483392 | 505 | |
3cce6243 | 506 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 507 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
508 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
509 | acpi_tables_len); | |
6b35e7bf | 510 | fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1); |
b6f6e3d3 AL |
511 | |
512 | smbios_table = smbios_get_table(&smbios_len); | |
513 | if (smbios_table) | |
514 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
515 | smbios_table, smbios_len); | |
4c5b10b7 JS |
516 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
517 | sizeof(struct e820_table)); | |
11c2fd3e | 518 | |
40ac17cd GN |
519 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
520 | sizeof(struct hpet_fw_config)); | |
11c2fd3e AL |
521 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
522 | * of nodes, one word for each VCPU->node and one word for each node to | |
523 | * hold the amount of memory. | |
524 | */ | |
525 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
526 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
527 | for (i = 0; i < smp_cpus; i++) { | |
528 | for (j = 0; j < nb_numa_nodes; j++) { | |
529 | if (node_cpumask[j] & (1 << i)) { | |
530 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
531 | break; | |
532 | } | |
533 | } | |
534 | } | |
535 | for (i = 0; i < nb_numa_nodes; i++) { | |
536 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
537 | } | |
538 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
539 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
bf483392 AG |
540 | |
541 | return fw_cfg; | |
80cabfad FB |
542 | } |
543 | ||
642a4f96 TS |
544 | static long get_file_size(FILE *f) |
545 | { | |
546 | long where, size; | |
547 | ||
548 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
549 | ||
550 | where = ftell(f); | |
551 | fseek(f, 0, SEEK_END); | |
552 | size = ftell(f); | |
553 | fseek(f, where, SEEK_SET); | |
554 | ||
555 | return size; | |
556 | } | |
557 | ||
f16408df | 558 | static void load_linux(void *fw_cfg, |
4fc9af53 | 559 | const char *kernel_filename, |
642a4f96 | 560 | const char *initrd_filename, |
e6ade764 | 561 | const char *kernel_cmdline, |
45a50b16 | 562 | target_phys_addr_t max_ram_size) |
642a4f96 TS |
563 | { |
564 | uint16_t protocol; | |
5cea8590 | 565 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 566 | uint32_t initrd_max; |
57a46d05 | 567 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
c227f099 | 568 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 569 | FILE *f; |
bf4e5d92 | 570 | char *vmode; |
642a4f96 TS |
571 | |
572 | /* Align to 16 bytes as a paranoia measure */ | |
573 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
574 | ||
575 | /* load the kernel header */ | |
576 | f = fopen(kernel_filename, "rb"); | |
577 | if (!f || !(kernel_size = get_file_size(f)) || | |
f16408df AG |
578 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
579 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
850810d0 JF |
580 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", |
581 | kernel_filename, strerror(errno)); | |
642a4f96 TS |
582 | exit(1); |
583 | } | |
584 | ||
585 | /* kernel protocol version */ | |
bc4edd79 | 586 | #if 0 |
642a4f96 | 587 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 588 | #endif |
642a4f96 TS |
589 | if (ldl_p(header+0x202) == 0x53726448) |
590 | protocol = lduw_p(header+0x206); | |
f16408df AG |
591 | else { |
592 | /* This looks like a multiboot kernel. If it is, let's stop | |
593 | treating it like a Linux kernel. */ | |
52001445 AL |
594 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
595 | kernel_cmdline, kernel_size, header)) | |
82663ee2 | 596 | return; |
642a4f96 | 597 | protocol = 0; |
f16408df | 598 | } |
642a4f96 TS |
599 | |
600 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
601 | /* Low kernel */ | |
a37af289 BS |
602 | real_addr = 0x90000; |
603 | cmdline_addr = 0x9a000 - cmdline_size; | |
604 | prot_addr = 0x10000; | |
642a4f96 TS |
605 | } else if (protocol < 0x202) { |
606 | /* High but ancient kernel */ | |
a37af289 BS |
607 | real_addr = 0x90000; |
608 | cmdline_addr = 0x9a000 - cmdline_size; | |
609 | prot_addr = 0x100000; | |
642a4f96 TS |
610 | } else { |
611 | /* High and recent kernel */ | |
a37af289 BS |
612 | real_addr = 0x10000; |
613 | cmdline_addr = 0x20000; | |
614 | prot_addr = 0x100000; | |
642a4f96 TS |
615 | } |
616 | ||
bc4edd79 | 617 | #if 0 |
642a4f96 | 618 | fprintf(stderr, |
526ccb7a AZ |
619 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
620 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
621 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
622 | real_addr, |
623 | cmdline_addr, | |
624 | prot_addr); | |
bc4edd79 | 625 | #endif |
642a4f96 TS |
626 | |
627 | /* highest address for loading the initrd */ | |
628 | if (protocol >= 0x203) | |
629 | initrd_max = ldl_p(header+0x22c); | |
630 | else | |
631 | initrd_max = 0x37ffffff; | |
632 | ||
e6ade764 GC |
633 | if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) |
634 | initrd_max = max_ram_size-ACPI_DATA_SIZE-1; | |
642a4f96 | 635 | |
57a46d05 AG |
636 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
637 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
638 | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, | |
639 | (uint8_t*)strdup(kernel_cmdline), | |
640 | strlen(kernel_cmdline)+1); | |
642a4f96 TS |
641 | |
642 | if (protocol >= 0x202) { | |
a37af289 | 643 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
644 | } else { |
645 | stw_p(header+0x20, 0xA33F); | |
646 | stw_p(header+0x22, cmdline_addr-real_addr); | |
647 | } | |
648 | ||
bf4e5d92 PT |
649 | /* handle vga= parameter */ |
650 | vmode = strstr(kernel_cmdline, "vga="); | |
651 | if (vmode) { | |
652 | unsigned int video_mode; | |
653 | /* skip "vga=" */ | |
654 | vmode += 4; | |
655 | if (!strncmp(vmode, "normal", 6)) { | |
656 | video_mode = 0xffff; | |
657 | } else if (!strncmp(vmode, "ext", 3)) { | |
658 | video_mode = 0xfffe; | |
659 | } else if (!strncmp(vmode, "ask", 3)) { | |
660 | video_mode = 0xfffd; | |
661 | } else { | |
662 | video_mode = strtol(vmode, NULL, 0); | |
663 | } | |
664 | stw_p(header+0x1fa, video_mode); | |
665 | } | |
666 | ||
642a4f96 TS |
667 | /* loader type */ |
668 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
669 | If this code is substantially changed, you may want to consider | |
670 | incrementing the revision. */ | |
671 | if (protocol >= 0x200) | |
672 | header[0x210] = 0xB0; | |
673 | ||
674 | /* heap */ | |
675 | if (protocol >= 0x201) { | |
676 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
677 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
678 | } | |
679 | ||
680 | /* load initrd */ | |
681 | if (initrd_filename) { | |
682 | if (protocol < 0x200) { | |
683 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
684 | exit(1); | |
685 | } | |
686 | ||
45a50b16 | 687 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 MK |
688 | if (initrd_size < 0) { |
689 | fprintf(stderr, "qemu: error reading initrd %s\n", | |
690 | initrd_filename); | |
691 | exit(1); | |
692 | } | |
693 | ||
45a50b16 | 694 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 AG |
695 | |
696 | initrd_data = qemu_malloc(initrd_size); | |
697 | load_image(initrd_filename, initrd_data); | |
698 | ||
699 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
700 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
701 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 702 | |
a37af289 | 703 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
704 | stl_p(header+0x21c, initrd_size); |
705 | } | |
706 | ||
45a50b16 | 707 | /* load kernel and setup */ |
642a4f96 TS |
708 | setup_size = header[0x1f1]; |
709 | if (setup_size == 0) | |
710 | setup_size = 4; | |
642a4f96 | 711 | setup_size = (setup_size+1)*512; |
45a50b16 | 712 | kernel_size -= setup_size; |
642a4f96 | 713 | |
45a50b16 GH |
714 | setup = qemu_malloc(setup_size); |
715 | kernel = qemu_malloc(kernel_size); | |
716 | fseek(f, 0, SEEK_SET); | |
5a41ecc5 KS |
717 | if (fread(setup, 1, setup_size, f) != setup_size) { |
718 | fprintf(stderr, "fread() failed\n"); | |
719 | exit(1); | |
720 | } | |
721 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
722 | fprintf(stderr, "fread() failed\n"); | |
723 | exit(1); | |
724 | } | |
642a4f96 | 725 | fclose(f); |
45a50b16 | 726 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
727 | |
728 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
729 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
730 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
731 | ||
732 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
733 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
734 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
735 | ||
736 | option_rom[nb_option_roms] = "linuxboot.bin"; | |
737 | nb_option_roms++; | |
642a4f96 TS |
738 | } |
739 | ||
b41a2cd1 FB |
740 | #define NE2000_NB_MAX 6 |
741 | ||
675d6f82 BS |
742 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
743 | 0x280, 0x380 }; | |
744 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 745 | |
675d6f82 BS |
746 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
747 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
6508fe59 | 748 | |
845773ab | 749 | void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
750 | { |
751 | struct soundhw *c; | |
6a36d84e | 752 | |
3a8bae3e | 753 | for (c = soundhw; c->name; ++c) { |
754 | if (c->enabled) { | |
755 | if (c->isa) { | |
756 | c->init.init_isa(pic); | |
757 | } else { | |
758 | if (pci_bus) { | |
759 | c->init.init_pci(pci_bus); | |
6a36d84e FB |
760 | } |
761 | } | |
762 | } | |
763 | } | |
764 | } | |
6a36d84e | 765 | |
845773ab | 766 | void pc_init_ne2k_isa(NICInfo *nd) |
a41b2ff2 PB |
767 | { |
768 | static int nb_ne2k = 0; | |
769 | ||
770 | if (nb_ne2k == NE2000_NB_MAX) | |
771 | return; | |
3a38d437 | 772 | isa_ne2000_init(ne2000_io[nb_ne2k], |
9453c5bc | 773 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
774 | nb_ne2k++; |
775 | } | |
776 | ||
678e12cc GN |
777 | int cpu_is_bsp(CPUState *env) |
778 | { | |
6cb2996c JK |
779 | /* We hard-wire the BSP to the first CPU. */ |
780 | return env->cpu_index == 0; | |
678e12cc GN |
781 | } |
782 | ||
92a16d7a | 783 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 BS |
784 | { |
785 | if (cpu_single_env) { | |
786 | return cpu_single_env->apic_state; | |
787 | } else { | |
788 | return NULL; | |
789 | } | |
790 | } | |
791 | ||
92a16d7a BS |
792 | static DeviceState *apic_init(void *env, uint8_t apic_id) |
793 | { | |
794 | DeviceState *dev; | |
795 | SysBusDevice *d; | |
796 | static int apic_mapped; | |
797 | ||
798 | dev = qdev_create(NULL, "apic"); | |
799 | qdev_prop_set_uint8(dev, "id", apic_id); | |
800 | qdev_prop_set_ptr(dev, "cpu_env", env); | |
801 | qdev_init_nofail(dev); | |
802 | d = sysbus_from_qdev(dev); | |
803 | ||
804 | /* XXX: mapping more APICs at the same memory location */ | |
805 | if (apic_mapped == 0) { | |
806 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
807 | on the global memory bus. */ | |
808 | /* XXX: what if the base changes? */ | |
809 | sysbus_mmio_map(d, 0, MSI_ADDR_BASE); | |
810 | apic_mapped = 1; | |
811 | } | |
812 | ||
813 | msix_supported = 1; | |
814 | ||
815 | return dev; | |
816 | } | |
817 | ||
53b67b30 BS |
818 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
819 | BIOS will read it and start S3 resume at POST Entry */ | |
845773ab | 820 | void pc_cmos_set_s3_resume(void *opaque, int irq, int level) |
53b67b30 | 821 | { |
1d914fa0 | 822 | ISADevice *s = opaque; |
53b67b30 BS |
823 | |
824 | if (level) { | |
825 | rtc_set_memory(s, 0xF, 0xFE); | |
826 | } | |
827 | } | |
828 | ||
845773ab | 829 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 BS |
830 | { |
831 | CPUState *s = opaque; | |
832 | ||
833 | if (level) { | |
834 | cpu_interrupt(s, CPU_INTERRUPT_SMI); | |
835 | } | |
836 | } | |
837 | ||
427bd8d6 | 838 | static void pc_cpu_reset(void *opaque) |
0e26b7b8 BS |
839 | { |
840 | CPUState *env = opaque; | |
841 | ||
842 | cpu_reset(env); | |
427bd8d6 | 843 | env->halted = !cpu_is_bsp(env); |
0e26b7b8 BS |
844 | } |
845 | ||
3a31f36a JK |
846 | static CPUState *pc_new_cpu(const char *cpu_model) |
847 | { | |
848 | CPUState *env; | |
849 | ||
850 | env = cpu_init(cpu_model); | |
851 | if (!env) { | |
852 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
853 | exit(1); | |
854 | } | |
855 | if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { | |
856 | env->cpuid_apic_id = env->cpu_index; | |
0e26b7b8 BS |
857 | env->apic_state = apic_init(env, env->cpuid_apic_id); |
858 | } | |
427bd8d6 JK |
859 | qemu_register_reset(pc_cpu_reset, env); |
860 | pc_cpu_reset(env); | |
3a31f36a JK |
861 | return env; |
862 | } | |
863 | ||
845773ab | 864 | void pc_cpus_init(const char *cpu_model) |
70166477 IY |
865 | { |
866 | int i; | |
867 | ||
868 | /* init CPUs */ | |
869 | if (cpu_model == NULL) { | |
870 | #ifdef TARGET_X86_64 | |
871 | cpu_model = "qemu64"; | |
872 | #else | |
873 | cpu_model = "qemu32"; | |
874 | #endif | |
875 | } | |
876 | ||
877 | for(i = 0; i < smp_cpus; i++) { | |
878 | pc_new_cpu(cpu_model); | |
879 | } | |
880 | } | |
881 | ||
845773ab IY |
882 | void pc_memory_init(ram_addr_t ram_size, |
883 | const char *kernel_filename, | |
884 | const char *kernel_cmdline, | |
885 | const char *initrd_filename, | |
886 | ram_addr_t *below_4g_mem_size_p, | |
887 | ram_addr_t *above_4g_mem_size_p) | |
80cabfad | 888 | { |
5cea8590 | 889 | char *filename; |
642a4f96 | 890 | int ret, linux_boot, i; |
c227f099 AL |
891 | ram_addr_t ram_addr, bios_offset, option_rom_offset; |
892 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; | |
45a50b16 | 893 | int bios_size, isa_bios_size; |
81a204e4 | 894 | void *fw_cfg; |
d592d303 | 895 | |
00f82b8a AJ |
896 | if (ram_size >= 0xe0000000 ) { |
897 | above_4g_mem_size = ram_size - 0xe0000000; | |
898 | below_4g_mem_size = 0xe0000000; | |
899 | } else { | |
900 | below_4g_mem_size = ram_size; | |
901 | } | |
3d53f5c3 IY |
902 | *above_4g_mem_size_p = above_4g_mem_size; |
903 | *below_4g_mem_size_p = below_4g_mem_size; | |
00f82b8a | 904 | |
44ae28f3 AW |
905 | #if TARGET_PHYS_ADDR_BITS == 32 |
906 | if (above_4g_mem_size > 0) { | |
907 | hw_error("To much RAM for 32-bit physical address"); | |
908 | } | |
909 | #endif | |
80cabfad FB |
910 | linux_boot = (kernel_filename != NULL); |
911 | ||
912 | /* allocate RAM */ | |
1724f049 AW |
913 | ram_addr = qemu_ram_alloc(NULL, "pc.ram", |
914 | below_4g_mem_size + above_4g_mem_size); | |
82b36dc3 | 915 | cpu_register_physical_memory(0, 0xa0000, ram_addr); |
82b36dc3 AL |
916 | cpu_register_physical_memory(0x100000, |
917 | below_4g_mem_size - 0x100000, | |
60e4c631 | 918 | ram_addr + 0x100000); |
44ae28f3 | 919 | #if TARGET_PHYS_ADDR_BITS > 32 |
bbe80adf AW |
920 | if (above_4g_mem_size > 0) { |
921 | cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size, | |
922 | ram_addr + below_4g_mem_size); | |
923 | } | |
8a637d44 | 924 | #endif |
82b36dc3 | 925 | |
970ac5a3 | 926 | /* BIOS load */ |
1192dad8 JM |
927 | if (bios_name == NULL) |
928 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
929 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
930 | if (filename) { | |
931 | bios_size = get_image_size(filename); | |
932 | } else { | |
933 | bios_size = -1; | |
934 | } | |
5fafdf24 | 935 | if (bios_size <= 0 || |
970ac5a3 | 936 | (bios_size % 65536) != 0) { |
7587cf44 FB |
937 | goto bios_error; |
938 | } | |
1724f049 | 939 | bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size); |
51edd4e6 GH |
940 | ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size)); |
941 | if (ret != 0) { | |
7587cf44 | 942 | bios_error: |
5cea8590 | 943 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); |
80cabfad FB |
944 | exit(1); |
945 | } | |
5cea8590 PB |
946 | if (filename) { |
947 | qemu_free(filename); | |
948 | } | |
7587cf44 FB |
949 | /* map the last 128KB of the BIOS in ISA space */ |
950 | isa_bios_size = bios_size; | |
951 | if (isa_bios_size > (128 * 1024)) | |
952 | isa_bios_size = 128 * 1024; | |
5fafdf24 TS |
953 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
954 | isa_bios_size, | |
7587cf44 | 955 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 956 | |
1724f049 | 957 | option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE); |
45a50b16 | 958 | cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); |
f753ff16 | 959 | |
1d108d97 AG |
960 | /* map all the bios at the top of memory */ |
961 | cpu_register_physical_memory((uint32_t)(-bios_size), | |
962 | bios_size, bios_offset | IO_MEM_ROM); | |
963 | ||
bf483392 | 964 | fw_cfg = bochs_bios_init(); |
8832cb80 | 965 | rom_set_fw(fw_cfg); |
1d108d97 | 966 | |
f753ff16 | 967 | if (linux_boot) { |
81a204e4 | 968 | load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
f753ff16 PB |
969 | } |
970 | ||
971 | for (i = 0; i < nb_option_roms; i++) { | |
45a50b16 | 972 | rom_add_option(option_rom[i]); |
406c8df3 | 973 | } |
3d53f5c3 IY |
974 | } |
975 | ||
845773ab IY |
976 | qemu_irq *pc_allocate_cpu_irq(void) |
977 | { | |
978 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
979 | } | |
980 | ||
981 | void pc_vga_init(PCIBus *pci_bus) | |
765d7908 IY |
982 | { |
983 | if (cirrus_vga_enabled) { | |
984 | if (pci_bus) { | |
985 | pci_cirrus_vga_init(pci_bus); | |
986 | } else { | |
987 | isa_cirrus_vga_init(); | |
988 | } | |
989 | } else if (vmsvga_enabled) { | |
990 | if (pci_bus) | |
991 | pci_vmsvga_init(pci_bus); | |
992 | else | |
993 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
994 | } else if (std_vga_enabled) { | |
995 | if (pci_bus) { | |
78895427 | 996 | pci_vga_init(pci_bus); |
765d7908 IY |
997 | } else { |
998 | isa_vga_init(); | |
999 | } | |
1000 | } | |
1001 | } | |
1002 | ||
4556bd8b BS |
1003 | static void cpu_request_exit(void *opaque, int irq, int level) |
1004 | { | |
1005 | CPUState *env = cpu_single_env; | |
1006 | ||
1007 | if (env && level) { | |
1008 | cpu_exit(env); | |
1009 | } | |
1010 | } | |
1011 | ||
845773ab IY |
1012 | void pc_basic_device_init(qemu_irq *isa_irq, |
1013 | FDCtrl **floppy_controller, | |
1d914fa0 | 1014 | ISADevice **rtc_state) |
ffe513da IY |
1015 | { |
1016 | int i; | |
1017 | DriveInfo *fd[MAX_FD]; | |
1018 | PITState *pit; | |
7d932dfd | 1019 | qemu_irq rtc_irq = NULL; |
956a3e6b BS |
1020 | qemu_irq *a20_line; |
1021 | ISADevice *i8042; | |
4556bd8b | 1022 | qemu_irq *cpu_exit_irq; |
ffe513da IY |
1023 | |
1024 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); | |
1025 | ||
1026 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); | |
1027 | ||
ffe513da | 1028 | if (!no_hpet) { |
822557eb JK |
1029 | DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL); |
1030 | ||
1031 | for (i = 0; i < 24; i++) { | |
1032 | sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]); | |
1033 | } | |
7d932dfd | 1034 | rtc_irq = qdev_get_gpio_in(hpet, 0); |
ffe513da | 1035 | } |
7d932dfd JK |
1036 | *rtc_state = rtc_init(2000, rtc_irq); |
1037 | ||
1038 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1039 | ||
1040 | pit = pit_init(0x40, isa_reserve_irq(0)); | |
1041 | pcspk_init(pit); | |
ffe513da IY |
1042 | |
1043 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1044 | if (serial_hds[i]) { | |
1045 | serial_isa_init(i, serial_hds[i]); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1050 | if (parallel_hds[i]) { | |
1051 | parallel_init(i, parallel_hds[i]); | |
1052 | } | |
1053 | } | |
1054 | ||
956a3e6b BS |
1055 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1); |
1056 | i8042 = isa_create_simple("i8042"); | |
1057 | i8042_setup_a20_line(i8042, a20_line); | |
1058 | vmmouse_init(i8042); | |
1059 | ||
4556bd8b BS |
1060 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1061 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1062 | |
1063 | for(i = 0; i < MAX_FD; i++) { | |
1064 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1065 | } | |
1066 | *floppy_controller = fdctrl_init_isa(fd); | |
1067 | } | |
1068 | ||
845773ab | 1069 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1070 | { |
1071 | int max_bus; | |
1072 | int bus; | |
1073 | ||
1074 | max_bus = drive_get_max_bus(IF_SCSI); | |
1075 | for (bus = 0; bus <= max_bus; bus++) { | |
1076 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1077 | } | |
1078 | } |