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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
26 | #include "fdc.h" | |
27 | #include "pci.h" | |
28 | #include "block.h" | |
29 | #include "sysemu.h" | |
30 | #include "audio/audio.h" | |
31 | #include "net.h" | |
32 | #include "smbus.h" | |
33 | #include "boards.h" | |
376253ec | 34 | #include "monitor.h" |
3cce6243 | 35 | #include "fw_cfg.h" |
16b29ae1 | 36 | #include "hpet_emul.h" |
9dd986cc | 37 | #include "watchdog.h" |
b6f6e3d3 | 38 | #include "smbios.h" |
80cabfad | 39 | |
b41a2cd1 FB |
40 | /* output Bochs bios info messages */ |
41 | //#define DEBUG_BIOS | |
42 | ||
80cabfad FB |
43 | #define BIOS_FILENAME "bios.bin" |
44 | #define VGABIOS_FILENAME "vgabios.bin" | |
de9258a8 | 45 | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
80cabfad | 46 | |
7fb4fdcf AZ |
47 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
48 | ||
a80274c3 PB |
49 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
50 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 51 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 52 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 53 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
80cabfad | 54 | |
e4bcb14c TS |
55 | #define MAX_IDE_BUS 2 |
56 | ||
baca51fa | 57 | static fdctrl_t *floppy_controller; |
b0a21b53 | 58 | static RTCState *rtc_state; |
ec844b96 | 59 | static PITState *pit; |
d592d303 | 60 | static IOAPICState *ioapic; |
a5954d5c | 61 | static PCIDevice *i440fx_state; |
80cabfad | 62 | |
e28f9884 GC |
63 | typedef struct rom_reset_data { |
64 | uint8_t *data; | |
65 | target_phys_addr_t addr; | |
66 | unsigned size; | |
67 | } RomResetData; | |
68 | ||
69 | static void option_rom_reset(void *_rrd) | |
70 | { | |
71 | RomResetData *rrd = _rrd; | |
72 | ||
73 | cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); | |
74 | } | |
75 | ||
76 | static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) | |
77 | { | |
78 | RomResetData *rrd = qemu_malloc(sizeof *rrd); | |
79 | ||
80 | rrd->data = qemu_malloc(size); | |
81 | cpu_physical_memory_read(addr, rrd->data, size); | |
82 | rrd->addr = addr; | |
83 | rrd->size = size; | |
84 | qemu_register_reset(option_rom_reset, rrd); | |
85 | } | |
86 | ||
b41a2cd1 | 87 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
88 | { |
89 | } | |
90 | ||
f929aad6 | 91 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 92 | static qemu_irq ferr_irq; |
f929aad6 FB |
93 | /* XXX: add IGNNE support */ |
94 | void cpu_set_ferr(CPUX86State *s) | |
95 | { | |
d537cf6c | 96 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
97 | } |
98 | ||
99 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
100 | { | |
d537cf6c | 101 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
102 | } |
103 | ||
28ab0e2e | 104 | /* TSC handling */ |
28ab0e2e FB |
105 | uint64_t cpu_get_tsc(CPUX86State *env) |
106 | { | |
1dce7c3c FB |
107 | /* Note: when using kqemu, it is more logical to return the host TSC |
108 | because kqemu does not trap the RDTSC instruction for | |
109 | performance reasons */ | |
640f42e4 | 110 | #ifdef CONFIG_KQEMU |
1dce7c3c FB |
111 | if (env->kqemu_enabled) { |
112 | return cpu_get_real_ticks(); | |
5fafdf24 | 113 | } else |
1dce7c3c FB |
114 | #endif |
115 | { | |
116 | return cpu_get_ticks(); | |
117 | } | |
28ab0e2e FB |
118 | } |
119 | ||
a5954d5c FB |
120 | /* SMM support */ |
121 | void cpu_smm_update(CPUState *env) | |
122 | { | |
123 | if (i440fx_state && env == first_cpu) | |
124 | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); | |
125 | } | |
126 | ||
127 | ||
3de388f6 FB |
128 | /* IRQ handling */ |
129 | int cpu_get_pic_interrupt(CPUState *env) | |
130 | { | |
131 | int intno; | |
132 | ||
3de388f6 FB |
133 | intno = apic_get_interrupt(env); |
134 | if (intno >= 0) { | |
135 | /* set irq request if a PIC irq is still pending */ | |
136 | /* XXX: improve that */ | |
5fafdf24 | 137 | pic_update_irq(isa_pic); |
3de388f6 FB |
138 | return intno; |
139 | } | |
3de388f6 | 140 | /* read the irq from the PIC */ |
0e21e12b TS |
141 | if (!apic_accept_pic_intr(env)) |
142 | return -1; | |
143 | ||
3de388f6 FB |
144 | intno = pic_read_irq(isa_pic); |
145 | return intno; | |
146 | } | |
147 | ||
d537cf6c | 148 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 149 | { |
a5b38b51 AJ |
150 | CPUState *env = first_cpu; |
151 | ||
d5529471 AJ |
152 | if (env->apic_state) { |
153 | while (env) { | |
154 | if (apic_accept_pic_intr(env)) | |
1a7de94a | 155 | apic_deliver_pic_intr(env, level); |
d5529471 AJ |
156 | env = env->next_cpu; |
157 | } | |
158 | } else { | |
b614106a AJ |
159 | if (level) |
160 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
161 | else | |
162 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 163 | } |
3de388f6 FB |
164 | } |
165 | ||
b0a21b53 FB |
166 | /* PC cmos mappings */ |
167 | ||
80cabfad FB |
168 | #define REG_EQUIPMENT_BYTE 0x14 |
169 | ||
777428f2 FB |
170 | static int cmos_get_fd_drive_type(int fd0) |
171 | { | |
172 | int val; | |
173 | ||
174 | switch (fd0) { | |
175 | case 0: | |
176 | /* 1.44 Mb 3"5 drive */ | |
177 | val = 4; | |
178 | break; | |
179 | case 1: | |
180 | /* 2.88 Mb 3"5 drive */ | |
181 | val = 5; | |
182 | break; | |
183 | case 2: | |
184 | /* 1.2 Mb 5"5 drive */ | |
185 | val = 2; | |
186 | break; | |
187 | default: | |
188 | val = 0; | |
189 | break; | |
190 | } | |
191 | return val; | |
192 | } | |
193 | ||
5fafdf24 | 194 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
ba6c2377 FB |
195 | { |
196 | RTCState *s = rtc_state; | |
197 | int cylinders, heads, sectors; | |
198 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
199 | rtc_set_memory(s, type_ofs, 47); | |
200 | rtc_set_memory(s, info_ofs, cylinders); | |
201 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
202 | rtc_set_memory(s, info_ofs + 2, heads); | |
203 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
204 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
205 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
206 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
207 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
208 | rtc_set_memory(s, info_ofs + 8, sectors); | |
209 | } | |
210 | ||
6ac0e82d AZ |
211 | /* convert boot_device letter to something recognizable by the bios */ |
212 | static int boot_device2nibble(char boot_device) | |
213 | { | |
214 | switch(boot_device) { | |
215 | case 'a': | |
216 | case 'b': | |
217 | return 0x01; /* floppy boot */ | |
218 | case 'c': | |
219 | return 0x02; /* hard drive boot */ | |
220 | case 'd': | |
221 | return 0x03; /* CD-ROM boot */ | |
222 | case 'n': | |
223 | return 0x04; /* Network boot */ | |
224 | } | |
225 | return 0; | |
226 | } | |
227 | ||
0ecdffbb AJ |
228 | /* copy/pasted from cmos_init, should be made a general function |
229 | and used there as well */ | |
3b4366de | 230 | static int pc_boot_set(void *opaque, const char *boot_device) |
0ecdffbb | 231 | { |
376253ec | 232 | Monitor *mon = cur_mon; |
0ecdffbb | 233 | #define PC_MAX_BOOT_DEVICES 3 |
3b4366de | 234 | RTCState *s = (RTCState *)opaque; |
0ecdffbb AJ |
235 | int nbds, bds[3] = { 0, }; |
236 | int i; | |
237 | ||
238 | nbds = strlen(boot_device); | |
239 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
376253ec | 240 | monitor_printf(mon, "Too many boot devices for PC\n"); |
0ecdffbb AJ |
241 | return(1); |
242 | } | |
243 | for (i = 0; i < nbds; i++) { | |
244 | bds[i] = boot_device2nibble(boot_device[i]); | |
245 | if (bds[i] == 0) { | |
376253ec AL |
246 | monitor_printf(mon, "Invalid boot device for PC: '%c'\n", |
247 | boot_device[i]); | |
0ecdffbb AJ |
248 | return(1); |
249 | } | |
250 | } | |
251 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
252 | rtc_set_memory(s, 0x38, (bds[2] << 4)); | |
253 | return(0); | |
254 | } | |
255 | ||
ba6c2377 | 256 | /* hd_table must contain 4 block drivers */ |
00f82b8a AJ |
257 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
258 | const char *boot_device, BlockDriverState **hd_table) | |
80cabfad | 259 | { |
b0a21b53 | 260 | RTCState *s = rtc_state; |
28c5af54 | 261 | int nbds, bds[3] = { 0, }; |
80cabfad | 262 | int val; |
b41a2cd1 | 263 | int fd0, fd1, nb; |
ba6c2377 | 264 | int i; |
b0a21b53 | 265 | |
b0a21b53 | 266 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
267 | |
268 | /* memory size */ | |
333190eb FB |
269 | val = 640; /* base memory in K */ |
270 | rtc_set_memory(s, 0x15, val); | |
271 | rtc_set_memory(s, 0x16, val >> 8); | |
272 | ||
80cabfad FB |
273 | val = (ram_size / 1024) - 1024; |
274 | if (val > 65535) | |
275 | val = 65535; | |
b0a21b53 FB |
276 | rtc_set_memory(s, 0x17, val); |
277 | rtc_set_memory(s, 0x18, val >> 8); | |
278 | rtc_set_memory(s, 0x30, val); | |
279 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 280 | |
00f82b8a AJ |
281 | if (above_4g_mem_size) { |
282 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
283 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
284 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
285 | } | |
286 | ||
9da98861 FB |
287 | if (ram_size > (16 * 1024 * 1024)) |
288 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
289 | else | |
290 | val = 0; | |
80cabfad FB |
291 | if (val > 65535) |
292 | val = 65535; | |
b0a21b53 FB |
293 | rtc_set_memory(s, 0x34, val); |
294 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 295 | |
298e01b6 AJ |
296 | /* set the number of CPU */ |
297 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
298 | ||
6ac0e82d | 299 | /* set boot devices, and disable floppy signature check if requested */ |
28c5af54 JM |
300 | #define PC_MAX_BOOT_DEVICES 3 |
301 | nbds = strlen(boot_device); | |
302 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
303 | fprintf(stderr, "Too many boot devices for PC\n"); | |
304 | exit(1); | |
305 | } | |
306 | for (i = 0; i < nbds; i++) { | |
307 | bds[i] = boot_device2nibble(boot_device[i]); | |
308 | if (bds[i] == 0) { | |
309 | fprintf(stderr, "Invalid boot device for PC: '%c'\n", | |
310 | boot_device[i]); | |
311 | exit(1); | |
312 | } | |
313 | } | |
314 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
315 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
80cabfad | 316 | |
b41a2cd1 FB |
317 | /* floppy type */ |
318 | ||
baca51fa FB |
319 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
320 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 321 | |
777428f2 | 322 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 323 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 324 | |
b0a21b53 | 325 | val = 0; |
b41a2cd1 | 326 | nb = 0; |
80cabfad FB |
327 | if (fd0 < 3) |
328 | nb++; | |
329 | if (fd1 < 3) | |
330 | nb++; | |
331 | switch (nb) { | |
332 | case 0: | |
333 | break; | |
334 | case 1: | |
b0a21b53 | 335 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
336 | break; |
337 | case 2: | |
b0a21b53 | 338 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
339 | break; |
340 | } | |
b0a21b53 FB |
341 | val |= 0x02; /* FPU is there */ |
342 | val |= 0x04; /* PS/2 mouse installed */ | |
343 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
344 | ||
ba6c2377 FB |
345 | /* hard drives */ |
346 | ||
347 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
348 | if (hd_table[0]) | |
349 | cmos_init_hd(0x19, 0x1b, hd_table[0]); | |
5fafdf24 | 350 | if (hd_table[1]) |
ba6c2377 FB |
351 | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
352 | ||
353 | val = 0; | |
40b6ecc6 | 354 | for (i = 0; i < 4; i++) { |
ba6c2377 | 355 | if (hd_table[i]) { |
46d4767d FB |
356 | int cylinders, heads, sectors, translation; |
357 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
358 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
359 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
360 | geometry can be different if a translation is done. */ | |
361 | translation = bdrv_get_translation_hint(hd_table[i]); | |
362 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
363 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
364 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
365 | /* No translation. */ | |
366 | translation = 0; | |
367 | } else { | |
368 | /* LBA translation. */ | |
369 | translation = 1; | |
370 | } | |
40b6ecc6 | 371 | } else { |
46d4767d | 372 | translation--; |
ba6c2377 | 373 | } |
ba6c2377 FB |
374 | val |= translation << (i * 2); |
375 | } | |
40b6ecc6 | 376 | } |
ba6c2377 | 377 | rtc_set_memory(s, 0x39, val); |
80cabfad FB |
378 | } |
379 | ||
59b8ad81 FB |
380 | void ioport_set_a20(int enable) |
381 | { | |
382 | /* XXX: send to all CPUs ? */ | |
383 | cpu_x86_set_a20(first_cpu, enable); | |
384 | } | |
385 | ||
386 | int ioport_get_a20(void) | |
387 | { | |
388 | return ((first_cpu->a20_mask >> 20) & 1); | |
389 | } | |
390 | ||
e1a23744 FB |
391 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
392 | { | |
59b8ad81 | 393 | ioport_set_a20((val >> 1) & 1); |
e1a23744 FB |
394 | /* XXX: bit 0 is fast reset */ |
395 | } | |
396 | ||
397 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
398 | { | |
59b8ad81 | 399 | return ioport_get_a20() << 1; |
e1a23744 FB |
400 | } |
401 | ||
80cabfad FB |
402 | /***********************************************************/ |
403 | /* Bochs BIOS debug ports */ | |
404 | ||
9596ebb7 | 405 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 406 | { |
a2f659ee FB |
407 | static const char shutdown_str[8] = "Shutdown"; |
408 | static int shutdown_index = 0; | |
3b46e624 | 409 | |
80cabfad FB |
410 | switch(addr) { |
411 | /* Bochs BIOS messages */ | |
412 | case 0x400: | |
413 | case 0x401: | |
414 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
415 | exit(1); | |
416 | case 0x402: | |
417 | case 0x403: | |
418 | #ifdef DEBUG_BIOS | |
419 | fprintf(stderr, "%c", val); | |
420 | #endif | |
421 | break; | |
a2f659ee FB |
422 | case 0x8900: |
423 | /* same as Bochs power off */ | |
424 | if (val == shutdown_str[shutdown_index]) { | |
425 | shutdown_index++; | |
426 | if (shutdown_index == 8) { | |
427 | shutdown_index = 0; | |
428 | qemu_system_shutdown_request(); | |
429 | } | |
430 | } else { | |
431 | shutdown_index = 0; | |
432 | } | |
433 | break; | |
80cabfad FB |
434 | |
435 | /* LGPL'ed VGA BIOS messages */ | |
436 | case 0x501: | |
437 | case 0x502: | |
438 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
439 | exit(1); | |
440 | case 0x500: | |
441 | case 0x503: | |
442 | #ifdef DEBUG_BIOS | |
443 | fprintf(stderr, "%c", val); | |
444 | #endif | |
445 | break; | |
446 | } | |
447 | } | |
448 | ||
11c2fd3e AL |
449 | extern uint64_t node_cpumask[MAX_NODES]; |
450 | ||
9596ebb7 | 451 | static void bochs_bios_init(void) |
80cabfad | 452 | { |
3cce6243 | 453 | void *fw_cfg; |
b6f6e3d3 AL |
454 | uint8_t *smbios_table; |
455 | size_t smbios_len; | |
11c2fd3e AL |
456 | uint64_t *numa_fw_cfg; |
457 | int i, j; | |
3cce6243 | 458 | |
b41a2cd1 FB |
459 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
460 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
461 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
462 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 463 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
464 | |
465 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
466 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
467 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
468 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
469 | |
470 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
471 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 | 472 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80deece2 BS |
473 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
474 | acpi_tables_len); | |
b6f6e3d3 AL |
475 | |
476 | smbios_table = smbios_get_table(&smbios_len); | |
477 | if (smbios_table) | |
478 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
479 | smbios_table, smbios_len); | |
11c2fd3e AL |
480 | |
481 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
482 | * of nodes, one word for each VCPU->node and one word for each node to | |
483 | * hold the amount of memory. | |
484 | */ | |
485 | numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); | |
486 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
487 | for (i = 0; i < smp_cpus; i++) { | |
488 | for (j = 0; j < nb_numa_nodes; j++) { | |
489 | if (node_cpumask[j] & (1 << i)) { | |
490 | numa_fw_cfg[i + 1] = cpu_to_le64(j); | |
491 | break; | |
492 | } | |
493 | } | |
494 | } | |
495 | for (i = 0; i < nb_numa_nodes; i++) { | |
496 | numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]); | |
497 | } | |
498 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, | |
499 | (1 + smp_cpus + nb_numa_nodes) * 8); | |
80cabfad FB |
500 | } |
501 | ||
642a4f96 TS |
502 | /* Generate an initial boot sector which sets state and jump to |
503 | a specified vector */ | |
7ffa4767 | 504 | static void generate_bootsect(target_phys_addr_t option_rom, |
4fc9af53 | 505 | uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
642a4f96 | 506 | { |
4fc9af53 AL |
507 | uint8_t rom[512], *p, *reloc; |
508 | uint8_t sum; | |
642a4f96 TS |
509 | int i; |
510 | ||
4fc9af53 AL |
511 | memset(rom, 0, sizeof(rom)); |
512 | ||
513 | p = rom; | |
514 | /* Make sure we have an option rom signature */ | |
515 | *p++ = 0x55; | |
516 | *p++ = 0xaa; | |
642a4f96 | 517 | |
4fc9af53 AL |
518 | /* ROM size in sectors*/ |
519 | *p++ = 1; | |
642a4f96 | 520 | |
4fc9af53 | 521 | /* Hook int19 */ |
642a4f96 | 522 | |
4fc9af53 AL |
523 | *p++ = 0x50; /* push ax */ |
524 | *p++ = 0x1e; /* push ds */ | |
525 | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ | |
526 | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ | |
642a4f96 | 527 | |
4fc9af53 AL |
528 | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
529 | *p++ = 0x64; *p++ = 0x00; | |
530 | reloc = p; | |
531 | *p++ = 0x00; *p++ = 0x00; | |
532 | ||
533 | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ | |
534 | *p++ = 0x66; *p++ = 0x00; | |
535 | ||
536 | *p++ = 0x1f; /* pop ds */ | |
537 | *p++ = 0x58; /* pop ax */ | |
538 | *p++ = 0xcb; /* lret */ | |
539 | ||
642a4f96 | 540 | /* Actual code */ |
4fc9af53 AL |
541 | *reloc = (p - rom); |
542 | ||
642a4f96 TS |
543 | *p++ = 0xfa; /* CLI */ |
544 | *p++ = 0xfc; /* CLD */ | |
545 | ||
546 | for (i = 0; i < 6; i++) { | |
547 | if (i == 1) /* Skip CS */ | |
548 | continue; | |
549 | ||
550 | *p++ = 0xb8; /* MOV AX,imm16 */ | |
551 | *p++ = segs[i]; | |
552 | *p++ = segs[i] >> 8; | |
553 | *p++ = 0x8e; /* MOV <seg>,AX */ | |
554 | *p++ = 0xc0 + (i << 3); | |
555 | } | |
556 | ||
557 | for (i = 0; i < 8; i++) { | |
558 | *p++ = 0x66; /* 32-bit operand size */ | |
559 | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ | |
560 | *p++ = gpr[i]; | |
561 | *p++ = gpr[i] >> 8; | |
562 | *p++ = gpr[i] >> 16; | |
563 | *p++ = gpr[i] >> 24; | |
564 | } | |
565 | ||
566 | *p++ = 0xea; /* JMP FAR */ | |
567 | *p++ = ip; /* IP */ | |
568 | *p++ = ip >> 8; | |
569 | *p++ = segs[1]; /* CS */ | |
570 | *p++ = segs[1] >> 8; | |
571 | ||
4fc9af53 AL |
572 | /* sign rom */ |
573 | sum = 0; | |
574 | for (i = 0; i < (sizeof(rom) - 1); i++) | |
575 | sum += rom[i]; | |
576 | rom[sizeof(rom) - 1] = -sum; | |
577 | ||
7ffa4767 | 578 | cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom)); |
d6ecb036 | 579 | option_rom_setup_reset(option_rom, sizeof (rom)); |
642a4f96 | 580 | } |
80cabfad | 581 | |
642a4f96 TS |
582 | static long get_file_size(FILE *f) |
583 | { | |
584 | long where, size; | |
585 | ||
586 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
587 | ||
588 | where = ftell(f); | |
589 | fseek(f, 0, SEEK_END); | |
590 | size = ftell(f); | |
591 | fseek(f, where, SEEK_SET); | |
592 | ||
593 | return size; | |
594 | } | |
595 | ||
7ffa4767 | 596 | static void load_linux(target_phys_addr_t option_rom, |
4fc9af53 | 597 | const char *kernel_filename, |
642a4f96 TS |
598 | const char *initrd_filename, |
599 | const char *kernel_cmdline) | |
600 | { | |
601 | uint16_t protocol; | |
602 | uint32_t gpr[8]; | |
603 | uint16_t seg[6]; | |
604 | uint16_t real_seg; | |
605 | int setup_size, kernel_size, initrd_size, cmdline_size; | |
606 | uint32_t initrd_max; | |
607 | uint8_t header[1024]; | |
a37af289 | 608 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr; |
642a4f96 TS |
609 | FILE *f, *fi; |
610 | ||
611 | /* Align to 16 bytes as a paranoia measure */ | |
612 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
613 | ||
614 | /* load the kernel header */ | |
615 | f = fopen(kernel_filename, "rb"); | |
616 | if (!f || !(kernel_size = get_file_size(f)) || | |
617 | fread(header, 1, 1024, f) != 1024) { | |
618 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
619 | kernel_filename); | |
620 | exit(1); | |
621 | } | |
622 | ||
623 | /* kernel protocol version */ | |
bc4edd79 | 624 | #if 0 |
642a4f96 | 625 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 626 | #endif |
642a4f96 TS |
627 | if (ldl_p(header+0x202) == 0x53726448) |
628 | protocol = lduw_p(header+0x206); | |
629 | else | |
630 | protocol = 0; | |
631 | ||
632 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
633 | /* Low kernel */ | |
a37af289 BS |
634 | real_addr = 0x90000; |
635 | cmdline_addr = 0x9a000 - cmdline_size; | |
636 | prot_addr = 0x10000; | |
642a4f96 TS |
637 | } else if (protocol < 0x202) { |
638 | /* High but ancient kernel */ | |
a37af289 BS |
639 | real_addr = 0x90000; |
640 | cmdline_addr = 0x9a000 - cmdline_size; | |
641 | prot_addr = 0x100000; | |
642a4f96 TS |
642 | } else { |
643 | /* High and recent kernel */ | |
a37af289 BS |
644 | real_addr = 0x10000; |
645 | cmdline_addr = 0x20000; | |
646 | prot_addr = 0x100000; | |
642a4f96 TS |
647 | } |
648 | ||
bc4edd79 | 649 | #if 0 |
642a4f96 | 650 | fprintf(stderr, |
526ccb7a AZ |
651 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
652 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
653 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
654 | real_addr, |
655 | cmdline_addr, | |
656 | prot_addr); | |
bc4edd79 | 657 | #endif |
642a4f96 TS |
658 | |
659 | /* highest address for loading the initrd */ | |
660 | if (protocol >= 0x203) | |
661 | initrd_max = ldl_p(header+0x22c); | |
662 | else | |
663 | initrd_max = 0x37ffffff; | |
664 | ||
665 | if (initrd_max >= ram_size-ACPI_DATA_SIZE) | |
666 | initrd_max = ram_size-ACPI_DATA_SIZE-1; | |
667 | ||
668 | /* kernel command line */ | |
a37af289 | 669 | pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline); |
642a4f96 TS |
670 | |
671 | if (protocol >= 0x202) { | |
a37af289 | 672 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
673 | } else { |
674 | stw_p(header+0x20, 0xA33F); | |
675 | stw_p(header+0x22, cmdline_addr-real_addr); | |
676 | } | |
677 | ||
678 | /* loader type */ | |
679 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
680 | If this code is substantially changed, you may want to consider | |
681 | incrementing the revision. */ | |
682 | if (protocol >= 0x200) | |
683 | header[0x210] = 0xB0; | |
684 | ||
685 | /* heap */ | |
686 | if (protocol >= 0x201) { | |
687 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
688 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
689 | } | |
690 | ||
691 | /* load initrd */ | |
692 | if (initrd_filename) { | |
693 | if (protocol < 0x200) { | |
694 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
695 | exit(1); | |
696 | } | |
697 | ||
698 | fi = fopen(initrd_filename, "rb"); | |
699 | if (!fi) { | |
700 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
701 | initrd_filename); | |
702 | exit(1); | |
703 | } | |
704 | ||
705 | initrd_size = get_file_size(fi); | |
a37af289 | 706 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
642a4f96 | 707 | |
526ccb7a AZ |
708 | fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx |
709 | "\n", initrd_size, initrd_addr); | |
642a4f96 | 710 | |
a37af289 | 711 | if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) { |
642a4f96 TS |
712 | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n", |
713 | initrd_filename); | |
714 | exit(1); | |
715 | } | |
716 | fclose(fi); | |
717 | ||
a37af289 | 718 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
719 | stl_p(header+0x21c, initrd_size); |
720 | } | |
721 | ||
722 | /* store the finalized header and load the rest of the kernel */ | |
a37af289 | 723 | cpu_physical_memory_write(real_addr, header, 1024); |
642a4f96 TS |
724 | |
725 | setup_size = header[0x1f1]; | |
726 | if (setup_size == 0) | |
727 | setup_size = 4; | |
728 | ||
729 | setup_size = (setup_size+1)*512; | |
730 | kernel_size -= setup_size; /* Size of protected-mode code */ | |
731 | ||
a37af289 BS |
732 | if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || |
733 | !fread_targphys_ok(prot_addr, kernel_size, f)) { | |
642a4f96 TS |
734 | fprintf(stderr, "qemu: read error on kernel '%s'\n", |
735 | kernel_filename); | |
736 | exit(1); | |
737 | } | |
738 | fclose(f); | |
739 | ||
740 | /* generate bootsector to set up the initial register state */ | |
a37af289 | 741 | real_seg = real_addr >> 4; |
642a4f96 TS |
742 | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
743 | seg[1] = real_seg+0x20; /* CS */ | |
744 | memset(gpr, 0, sizeof gpr); | |
745 | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ | |
746 | ||
d6ecb036 GC |
747 | option_rom_setup_reset(real_addr, setup_size); |
748 | option_rom_setup_reset(prot_addr, kernel_size); | |
749 | option_rom_setup_reset(cmdline_addr, cmdline_size); | |
750 | if (initrd_filename) | |
751 | option_rom_setup_reset(initrd_addr, initrd_size); | |
752 | ||
4fc9af53 | 753 | generate_bootsect(option_rom, gpr, seg, 0); |
642a4f96 TS |
754 | } |
755 | ||
59b8ad81 FB |
756 | static void main_cpu_reset(void *opaque) |
757 | { | |
758 | CPUState *env = opaque; | |
759 | cpu_reset(env); | |
760 | } | |
761 | ||
b41a2cd1 FB |
762 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
763 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
764 | static const int ide_irq[2] = { 14, 15 }; | |
765 | ||
766 | #define NE2000_NB_MAX 6 | |
767 | ||
8d11df9e | 768 | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
b41a2cd1 FB |
769 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
770 | ||
8d11df9e FB |
771 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
772 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
773 | ||
6508fe59 FB |
774 | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
775 | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
776 | ||
6a36d84e | 777 | #ifdef HAS_AUDIO |
d537cf6c | 778 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
779 | { |
780 | struct soundhw *c; | |
781 | int audio_enabled = 0; | |
782 | ||
783 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
784 | audio_enabled = c->enabled; | |
785 | } | |
786 | ||
787 | if (audio_enabled) { | |
0d9acba8 PB |
788 | for (c = soundhw; c->name; ++c) { |
789 | if (c->enabled) { | |
790 | if (c->isa) { | |
22d83b14 PB |
791 | c->init.init_isa(pic); |
792 | } else { | |
0d9acba8 | 793 | if (pci_bus) { |
22d83b14 | 794 | c->init.init_pci(pci_bus); |
6a36d84e FB |
795 | } |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
800 | } | |
801 | #endif | |
802 | ||
d537cf6c | 803 | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
a41b2ff2 PB |
804 | { |
805 | static int nb_ne2k = 0; | |
806 | ||
807 | if (nb_ne2k == NE2000_NB_MAX) | |
808 | return; | |
d537cf6c | 809 | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
a41b2ff2 PB |
810 | nb_ne2k++; |
811 | } | |
812 | ||
f753ff16 PB |
813 | static int load_option_rom(const char *oprom, target_phys_addr_t start, |
814 | target_phys_addr_t end) | |
815 | { | |
816 | int size; | |
817 | ||
818 | size = get_image_size(oprom); | |
819 | if (size > 0 && start + size > end) { | |
820 | fprintf(stderr, "Not enough space to load option rom '%s'\n", | |
821 | oprom); | |
822 | exit(1); | |
823 | } | |
824 | size = load_image_targphys(oprom, start, end - start); | |
825 | if (size < 0) { | |
826 | fprintf(stderr, "Could not load option rom '%s'\n", oprom); | |
827 | exit(1); | |
828 | } | |
829 | /* Round up optiom rom size to the next 2k boundary */ | |
830 | size = (size + 2047) & ~2047; | |
e28f9884 | 831 | option_rom_setup_reset(start, size); |
f753ff16 PB |
832 | return size; |
833 | } | |
834 | ||
80cabfad | 835 | /* PC hardware initialisation */ |
fbe1b595 | 836 | static void pc_init1(ram_addr_t ram_size, |
3023f332 | 837 | const char *boot_device, |
b5ff2d6e | 838 | const char *kernel_filename, const char *kernel_cmdline, |
3dbbdc25 | 839 | const char *initrd_filename, |
a049de61 | 840 | int pci_enabled, const char *cpu_model) |
80cabfad FB |
841 | { |
842 | char buf[1024]; | |
642a4f96 | 843 | int ret, linux_boot, i; |
b584726d | 844 | ram_addr_t ram_addr, bios_offset, option_rom_offset; |
00f82b8a | 845 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; |
f753ff16 | 846 | int bios_size, isa_bios_size, oprom_area_size; |
46e50e9d | 847 | PCIBus *pci_bus; |
5c3ff3a7 | 848 | int piix3_devfn = -1; |
59b8ad81 | 849 | CPUState *env; |
d537cf6c PB |
850 | qemu_irq *cpu_irq; |
851 | qemu_irq *i8259; | |
e4bcb14c TS |
852 | int index; |
853 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
854 | BlockDriverState *fd[MAX_FD]; | |
34b39c2b | 855 | int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled; |
d592d303 | 856 | |
00f82b8a AJ |
857 | if (ram_size >= 0xe0000000 ) { |
858 | above_4g_mem_size = ram_size - 0xe0000000; | |
859 | below_4g_mem_size = 0xe0000000; | |
860 | } else { | |
861 | below_4g_mem_size = ram_size; | |
862 | } | |
863 | ||
80cabfad FB |
864 | linux_boot = (kernel_filename != NULL); |
865 | ||
59b8ad81 | 866 | /* init CPUs */ |
a049de61 FB |
867 | if (cpu_model == NULL) { |
868 | #ifdef TARGET_X86_64 | |
869 | cpu_model = "qemu64"; | |
870 | #else | |
871 | cpu_model = "qemu32"; | |
872 | #endif | |
873 | } | |
874 | ||
59b8ad81 | 875 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
876 | env = cpu_init(cpu_model); |
877 | if (!env) { | |
878 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
879 | exit(1); | |
880 | } | |
59b8ad81 | 881 | if (i != 0) |
ce5232c5 | 882 | env->halted = 1; |
59b8ad81 FB |
883 | if (smp_cpus > 1) { |
884 | /* XXX: enable it in all cases */ | |
885 | env->cpuid_features |= CPUID_APIC; | |
886 | } | |
59b8ad81 FB |
887 | qemu_register_reset(main_cpu_reset, env); |
888 | if (pci_enabled) { | |
889 | apic_init(env); | |
890 | } | |
891 | } | |
892 | ||
26fb5e48 AJ |
893 | vmport_init(); |
894 | ||
80cabfad | 895 | /* allocate RAM */ |
82b36dc3 AL |
896 | ram_addr = qemu_ram_alloc(0xa0000); |
897 | cpu_register_physical_memory(0, 0xa0000, ram_addr); | |
898 | ||
899 | /* Allocate, even though we won't register, so we don't break the | |
900 | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), | |
901 | * and some bios areas, which will be registered later | |
902 | */ | |
903 | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); | |
904 | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); | |
905 | cpu_register_physical_memory(0x100000, | |
906 | below_4g_mem_size - 0x100000, | |
907 | ram_addr); | |
00f82b8a AJ |
908 | |
909 | /* above 4giga memory allocation */ | |
910 | if (above_4g_mem_size > 0) { | |
82b36dc3 AL |
911 | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
912 | cpu_register_physical_memory(0x100000000ULL, | |
526ccb7a | 913 | above_4g_mem_size, |
82b36dc3 | 914 | ram_addr); |
00f82b8a | 915 | } |
80cabfad | 916 | |
82b36dc3 | 917 | |
970ac5a3 | 918 | /* BIOS load */ |
1192dad8 JM |
919 | if (bios_name == NULL) |
920 | bios_name = BIOS_FILENAME; | |
921 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
7587cf44 | 922 | bios_size = get_image_size(buf); |
5fafdf24 | 923 | if (bios_size <= 0 || |
970ac5a3 | 924 | (bios_size % 65536) != 0) { |
7587cf44 FB |
925 | goto bios_error; |
926 | } | |
970ac5a3 | 927 | bios_offset = qemu_ram_alloc(bios_size); |
44654490 | 928 | ret = load_image(buf, qemu_get_ram_ptr(bios_offset)); |
7587cf44 FB |
929 | if (ret != bios_size) { |
930 | bios_error: | |
970ac5a3 | 931 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf); |
80cabfad FB |
932 | exit(1); |
933 | } | |
7587cf44 FB |
934 | /* map the last 128KB of the BIOS in ISA space */ |
935 | isa_bios_size = bios_size; | |
936 | if (isa_bios_size > (128 * 1024)) | |
937 | isa_bios_size = 128 * 1024; | |
5fafdf24 TS |
938 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
939 | isa_bios_size, | |
7587cf44 | 940 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 941 | |
4fc9af53 | 942 | |
f753ff16 PB |
943 | |
944 | option_rom_offset = qemu_ram_alloc(0x20000); | |
945 | oprom_area_size = 0; | |
49669fc5 | 946 | cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); |
f753ff16 PB |
947 | |
948 | if (using_vga) { | |
949 | /* VGA BIOS load */ | |
950 | if (cirrus_vga_enabled) { | |
951 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, | |
952 | VGABIOS_CIRRUS_FILENAME); | |
953 | } else { | |
954 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
970ac5a3 | 955 | } |
f753ff16 PB |
956 | oprom_area_size = load_option_rom(buf, 0xc0000, 0xe0000); |
957 | } | |
958 | /* Although video roms can grow larger than 0x8000, the area between | |
959 | * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking | |
960 | * for any other kind of option rom inside this area */ | |
961 | if (oprom_area_size < 0x8000) | |
962 | oprom_area_size = 0x8000; | |
963 | ||
964 | if (linux_boot) { | |
7ffa4767 | 965 | load_linux(0xc0000 + oprom_area_size, |
f753ff16 PB |
966 | kernel_filename, initrd_filename, kernel_cmdline); |
967 | oprom_area_size += 2048; | |
968 | } | |
969 | ||
970 | for (i = 0; i < nb_option_roms; i++) { | |
971 | oprom_area_size += load_option_rom(option_rom[i], | |
972 | 0xc0000 + oprom_area_size, 0xe0000); | |
9ae02555 TS |
973 | } |
974 | ||
7587cf44 | 975 | /* map all the bios at the top of memory */ |
5fafdf24 | 976 | cpu_register_physical_memory((uint32_t)(-bios_size), |
7587cf44 | 977 | bios_size, bios_offset | IO_MEM_ROM); |
3b46e624 | 978 | |
80cabfad FB |
979 | bochs_bios_init(); |
980 | ||
a5b38b51 | 981 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
d537cf6c PB |
982 | i8259 = i8259_init(cpu_irq[0]); |
983 | ferr_irq = i8259[13]; | |
984 | ||
69b91039 | 985 | if (pci_enabled) { |
d537cf6c | 986 | pci_bus = i440fx_init(&i440fx_state, i8259); |
8f1c91d8 | 987 | piix3_devfn = piix3_init(pci_bus, -1); |
46e50e9d FB |
988 | } else { |
989 | pci_bus = NULL; | |
69b91039 FB |
990 | } |
991 | ||
80cabfad | 992 | /* init basic PC hardware */ |
b41a2cd1 | 993 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
80cabfad | 994 | |
f929aad6 FB |
995 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
996 | ||
1f04275e FB |
997 | if (cirrus_vga_enabled) { |
998 | if (pci_enabled) { | |
fbe1b595 | 999 | pci_cirrus_vga_init(pci_bus); |
1f04275e | 1000 | } else { |
fbe1b595 | 1001 | isa_cirrus_vga_init(); |
1f04275e | 1002 | } |
d34cab9f TS |
1003 | } else if (vmsvga_enabled) { |
1004 | if (pci_enabled) | |
fbe1b595 | 1005 | pci_vmsvga_init(pci_bus); |
d34cab9f TS |
1006 | else |
1007 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
c2b3b41a | 1008 | } else if (std_vga_enabled) { |
89b6b508 | 1009 | if (pci_enabled) { |
fbe1b595 | 1010 | pci_vga_init(pci_bus, 0, 0); |
89b6b508 | 1011 | } else { |
fbe1b595 | 1012 | isa_vga_init(); |
89b6b508 | 1013 | } |
1f04275e | 1014 | } |
80cabfad | 1015 | |
42fc73a1 | 1016 | rtc_state = rtc_init(0x70, i8259[8], 2000); |
80cabfad | 1017 | |
3b4366de BS |
1018 | qemu_register_boot_set(pc_boot_set, rtc_state); |
1019 | ||
e1a23744 FB |
1020 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
1021 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
1022 | ||
d592d303 | 1023 | if (pci_enabled) { |
d592d303 FB |
1024 | ioapic = ioapic_init(); |
1025 | } | |
d537cf6c | 1026 | pit = pit_init(0x40, i8259[0]); |
fd06c375 | 1027 | pcspk_init(pit); |
16b29ae1 AL |
1028 | if (!no_hpet) { |
1029 | hpet_init(i8259); | |
1030 | } | |
d592d303 FB |
1031 | if (pci_enabled) { |
1032 | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); | |
1033 | } | |
b41a2cd1 | 1034 | |
8d11df9e FB |
1035 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1036 | if (serial_hds[i]) { | |
b6cd0ea1 AJ |
1037 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200, |
1038 | serial_hds[i]); | |
8d11df9e FB |
1039 | } |
1040 | } | |
b41a2cd1 | 1041 | |
6508fe59 FB |
1042 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1043 | if (parallel_hds[i]) { | |
d537cf6c PB |
1044 | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
1045 | parallel_hds[i]); | |
6508fe59 FB |
1046 | } |
1047 | } | |
1048 | ||
9dd986cc RJ |
1049 | watchdog_pc_init(pci_bus); |
1050 | ||
a41b2ff2 | 1051 | for(i = 0; i < nb_nics; i++) { |
cb457d76 AL |
1052 | NICInfo *nd = &nd_table[i]; |
1053 | ||
1054 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
d537cf6c | 1055 | pc_init_ne2k_isa(nd, i8259); |
cb457d76 AL |
1056 | else |
1057 | pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); | |
a41b2ff2 | 1058 | } |
b41a2cd1 | 1059 | |
5e3cb534 AL |
1060 | qemu_system_hot_add_init(); |
1061 | ||
e4bcb14c TS |
1062 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
1063 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1064 | exit(1); | |
1065 | } | |
1066 | ||
1067 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
1068 | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
1069 | if (index != -1) | |
1070 | hd[i] = drives_table[index].bdrv; | |
1071 | else | |
1072 | hd[i] = NULL; | |
1073 | } | |
1074 | ||
a41b2ff2 | 1075 | if (pci_enabled) { |
e4bcb14c | 1076 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); |
a41b2ff2 | 1077 | } else { |
e4bcb14c | 1078 | for(i = 0; i < MAX_IDE_BUS; i++) { |
d537cf6c | 1079 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
e4bcb14c | 1080 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); |
69b91039 | 1081 | } |
b41a2cd1 | 1082 | } |
69b91039 | 1083 | |
d537cf6c | 1084 | i8042_init(i8259[1], i8259[12], 0x60); |
7c29d0c0 | 1085 | DMA_init(0); |
6a36d84e | 1086 | #ifdef HAS_AUDIO |
d537cf6c | 1087 | audio_init(pci_enabled ? pci_bus : NULL, i8259); |
fb065187 | 1088 | #endif |
80cabfad | 1089 | |
e4bcb14c TS |
1090 | for(i = 0; i < MAX_FD; i++) { |
1091 | index = drive_get_index(IF_FLOPPY, 0, i); | |
1092 | if (index != -1) | |
1093 | fd[i] = drives_table[index].bdrv; | |
1094 | else | |
1095 | fd[i] = NULL; | |
1096 | } | |
1097 | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); | |
b41a2cd1 | 1098 | |
00f82b8a | 1099 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
69b91039 | 1100 | |
bb36d470 | 1101 | if (pci_enabled && usb_enabled) { |
afcc3cdf | 1102 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); |
bb36d470 FB |
1103 | } |
1104 | ||
6515b203 | 1105 | if (pci_enabled && acpi_enabled) { |
3fffc223 | 1106 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
0ff596d0 PB |
1107 | i2c_bus *smbus; |
1108 | ||
1109 | /* TODO: Populate SPD eeprom data. */ | |
cf7a2fe2 | 1110 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
3fffc223 | 1111 | for (i = 0; i < 8; i++) { |
1ea96673 PB |
1112 | DeviceState *eeprom; |
1113 | eeprom = qdev_create(smbus, "smbus-eeprom"); | |
1114 | qdev_set_prop_int(eeprom, "address", 0x50 + i); | |
1115 | qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); | |
1116 | qdev_init(eeprom); | |
3fffc223 | 1117 | } |
6515b203 | 1118 | } |
3b46e624 | 1119 | |
a5954d5c FB |
1120 | if (i440fx_state) { |
1121 | i440fx_init_memory_mappings(i440fx_state); | |
1122 | } | |
e4bcb14c | 1123 | |
7d8406be | 1124 | if (pci_enabled) { |
e4bcb14c | 1125 | int max_bus; |
9be5dafe | 1126 | int bus; |
96d30e48 | 1127 | |
e4bcb14c | 1128 | max_bus = drive_get_max_bus(IF_SCSI); |
e4bcb14c | 1129 | for (bus = 0; bus <= max_bus; bus++) { |
9be5dafe | 1130 | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
e4bcb14c | 1131 | } |
7d8406be | 1132 | } |
6e02c38d AL |
1133 | |
1134 | /* Add virtio block devices */ | |
1135 | if (pci_enabled) { | |
1136 | int index; | |
1137 | int unit_id = 0; | |
1138 | ||
1139 | while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { | |
53c25cea | 1140 | pci_create_simple(pci_bus, -1, "virtio-blk-pci"); |
6e02c38d AL |
1141 | unit_id++; |
1142 | } | |
1143 | } | |
bd322087 AL |
1144 | |
1145 | /* Add virtio balloon device */ | |
2d72c572 | 1146 | if (pci_enabled) { |
53c25cea | 1147 | pci_create_simple(pci_bus, -1, "virtio-balloon-pci"); |
2d72c572 | 1148 | } |
a2fa19f9 AL |
1149 | |
1150 | /* Add virtio console devices */ | |
1151 | if (pci_enabled) { | |
1152 | for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { | |
0e058a8a | 1153 | if (virtcon_hds[i]) { |
53c25cea | 1154 | pci_create_simple(pci_bus, -1, "virtio-console-pci"); |
0e058a8a | 1155 | } |
a2fa19f9 AL |
1156 | } |
1157 | } | |
80cabfad | 1158 | } |
b5ff2d6e | 1159 | |
fbe1b595 | 1160 | static void pc_init_pci(ram_addr_t ram_size, |
3023f332 | 1161 | const char *boot_device, |
5fafdf24 | 1162 | const char *kernel_filename, |
3dbbdc25 | 1163 | const char *kernel_cmdline, |
94fc95cd JM |
1164 | const char *initrd_filename, |
1165 | const char *cpu_model) | |
3dbbdc25 | 1166 | { |
fbe1b595 | 1167 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1168 | kernel_filename, kernel_cmdline, |
a049de61 | 1169 | initrd_filename, 1, cpu_model); |
3dbbdc25 FB |
1170 | } |
1171 | ||
fbe1b595 | 1172 | static void pc_init_isa(ram_addr_t ram_size, |
3023f332 | 1173 | const char *boot_device, |
5fafdf24 | 1174 | const char *kernel_filename, |
3dbbdc25 | 1175 | const char *kernel_cmdline, |
94fc95cd JM |
1176 | const char *initrd_filename, |
1177 | const char *cpu_model) | |
3dbbdc25 | 1178 | { |
fbe1b595 | 1179 | pc_init1(ram_size, boot_device, |
3dbbdc25 | 1180 | kernel_filename, kernel_cmdline, |
a049de61 | 1181 | initrd_filename, 0, cpu_model); |
3dbbdc25 FB |
1182 | } |
1183 | ||
0bacd130 AL |
1184 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
1185 | BIOS will read it and start S3 resume at POST Entry */ | |
1186 | void cmos_set_s3_resume(void) | |
1187 | { | |
1188 | if (rtc_state) | |
1189 | rtc_set_memory(rtc_state, 0xF, 0xFE); | |
1190 | } | |
1191 | ||
b5ff2d6e | 1192 | QEMUMachine pc_machine = { |
a245f2e7 AJ |
1193 | .name = "pc", |
1194 | .desc = "Standard PC", | |
1195 | .init = pc_init_pci, | |
b2097003 | 1196 | .max_cpus = 255, |
3dbbdc25 FB |
1197 | }; |
1198 | ||
1199 | QEMUMachine isapc_machine = { | |
a245f2e7 AJ |
1200 | .name = "isapc", |
1201 | .desc = "ISA-only PC", | |
1202 | .init = pc_init_isa, | |
b2097003 | 1203 | .max_cpus = 1, |
b5ff2d6e | 1204 | }; |