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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
26 | #include "fdc.h" | |
27 | #include "pci.h" | |
28 | #include "block.h" | |
29 | #include "sysemu.h" | |
30 | #include "audio/audio.h" | |
31 | #include "net.h" | |
32 | #include "smbus.h" | |
33 | #include "boards.h" | |
80cabfad | 34 | |
b41a2cd1 FB |
35 | /* output Bochs bios info messages */ |
36 | //#define DEBUG_BIOS | |
37 | ||
80cabfad FB |
38 | #define BIOS_FILENAME "bios.bin" |
39 | #define VGABIOS_FILENAME "vgabios.bin" | |
de9258a8 | 40 | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
80cabfad | 41 | |
7fb4fdcf AZ |
42 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
43 | ||
a80274c3 PB |
44 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
45 | #define ACPI_DATA_SIZE 0x10000 | |
80cabfad | 46 | |
e4bcb14c TS |
47 | #define MAX_IDE_BUS 2 |
48 | ||
baca51fa | 49 | static fdctrl_t *floppy_controller; |
b0a21b53 | 50 | static RTCState *rtc_state; |
ec844b96 | 51 | static PITState *pit; |
d592d303 | 52 | static IOAPICState *ioapic; |
a5954d5c | 53 | static PCIDevice *i440fx_state; |
80cabfad | 54 | |
b41a2cd1 | 55 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
56 | { |
57 | } | |
58 | ||
f929aad6 | 59 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 60 | static qemu_irq ferr_irq; |
f929aad6 FB |
61 | /* XXX: add IGNNE support */ |
62 | void cpu_set_ferr(CPUX86State *s) | |
63 | { | |
d537cf6c | 64 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
65 | } |
66 | ||
67 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
68 | { | |
d537cf6c | 69 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
70 | } |
71 | ||
28ab0e2e | 72 | /* TSC handling */ |
28ab0e2e FB |
73 | uint64_t cpu_get_tsc(CPUX86State *env) |
74 | { | |
1dce7c3c FB |
75 | /* Note: when using kqemu, it is more logical to return the host TSC |
76 | because kqemu does not trap the RDTSC instruction for | |
77 | performance reasons */ | |
78 | #if USE_KQEMU | |
79 | if (env->kqemu_enabled) { | |
80 | return cpu_get_real_ticks(); | |
5fafdf24 | 81 | } else |
1dce7c3c FB |
82 | #endif |
83 | { | |
84 | return cpu_get_ticks(); | |
85 | } | |
28ab0e2e FB |
86 | } |
87 | ||
a5954d5c FB |
88 | /* SMM support */ |
89 | void cpu_smm_update(CPUState *env) | |
90 | { | |
91 | if (i440fx_state && env == first_cpu) | |
92 | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); | |
93 | } | |
94 | ||
95 | ||
3de388f6 FB |
96 | /* IRQ handling */ |
97 | int cpu_get_pic_interrupt(CPUState *env) | |
98 | { | |
99 | int intno; | |
100 | ||
3de388f6 FB |
101 | intno = apic_get_interrupt(env); |
102 | if (intno >= 0) { | |
103 | /* set irq request if a PIC irq is still pending */ | |
104 | /* XXX: improve that */ | |
5fafdf24 | 105 | pic_update_irq(isa_pic); |
3de388f6 FB |
106 | return intno; |
107 | } | |
3de388f6 | 108 | /* read the irq from the PIC */ |
0e21e12b TS |
109 | if (!apic_accept_pic_intr(env)) |
110 | return -1; | |
111 | ||
3de388f6 FB |
112 | intno = pic_read_irq(isa_pic); |
113 | return intno; | |
114 | } | |
115 | ||
d537cf6c | 116 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 117 | { |
a5b38b51 AJ |
118 | CPUState *env = first_cpu; |
119 | ||
120 | if (!level) | |
121 | return; | |
122 | ||
123 | while (env) { | |
124 | if (apic_accept_pic_intr(env)) | |
125 | apic_local_deliver(env, APIC_LINT0); | |
126 | env = env->next_cpu; | |
127 | } | |
3de388f6 FB |
128 | } |
129 | ||
b0a21b53 FB |
130 | /* PC cmos mappings */ |
131 | ||
80cabfad FB |
132 | #define REG_EQUIPMENT_BYTE 0x14 |
133 | ||
777428f2 FB |
134 | static int cmos_get_fd_drive_type(int fd0) |
135 | { | |
136 | int val; | |
137 | ||
138 | switch (fd0) { | |
139 | case 0: | |
140 | /* 1.44 Mb 3"5 drive */ | |
141 | val = 4; | |
142 | break; | |
143 | case 1: | |
144 | /* 2.88 Mb 3"5 drive */ | |
145 | val = 5; | |
146 | break; | |
147 | case 2: | |
148 | /* 1.2 Mb 5"5 drive */ | |
149 | val = 2; | |
150 | break; | |
151 | default: | |
152 | val = 0; | |
153 | break; | |
154 | } | |
155 | return val; | |
156 | } | |
157 | ||
5fafdf24 | 158 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
ba6c2377 FB |
159 | { |
160 | RTCState *s = rtc_state; | |
161 | int cylinders, heads, sectors; | |
162 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
163 | rtc_set_memory(s, type_ofs, 47); | |
164 | rtc_set_memory(s, info_ofs, cylinders); | |
165 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
166 | rtc_set_memory(s, info_ofs + 2, heads); | |
167 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
168 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
169 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
170 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
171 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
172 | rtc_set_memory(s, info_ofs + 8, sectors); | |
173 | } | |
174 | ||
6ac0e82d AZ |
175 | /* convert boot_device letter to something recognizable by the bios */ |
176 | static int boot_device2nibble(char boot_device) | |
177 | { | |
178 | switch(boot_device) { | |
179 | case 'a': | |
180 | case 'b': | |
181 | return 0x01; /* floppy boot */ | |
182 | case 'c': | |
183 | return 0x02; /* hard drive boot */ | |
184 | case 'd': | |
185 | return 0x03; /* CD-ROM boot */ | |
186 | case 'n': | |
187 | return 0x04; /* Network boot */ | |
188 | } | |
189 | return 0; | |
190 | } | |
191 | ||
ba6c2377 | 192 | /* hd_table must contain 4 block drivers */ |
03875444 | 193 | static void cmos_init(int ram_size, const char *boot_device, BlockDriverState **hd_table) |
80cabfad | 194 | { |
b0a21b53 | 195 | RTCState *s = rtc_state; |
28c5af54 | 196 | int nbds, bds[3] = { 0, }; |
80cabfad | 197 | int val; |
b41a2cd1 | 198 | int fd0, fd1, nb; |
ba6c2377 | 199 | int i; |
b0a21b53 | 200 | |
b0a21b53 | 201 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
202 | |
203 | /* memory size */ | |
333190eb FB |
204 | val = 640; /* base memory in K */ |
205 | rtc_set_memory(s, 0x15, val); | |
206 | rtc_set_memory(s, 0x16, val >> 8); | |
207 | ||
80cabfad FB |
208 | val = (ram_size / 1024) - 1024; |
209 | if (val > 65535) | |
210 | val = 65535; | |
b0a21b53 FB |
211 | rtc_set_memory(s, 0x17, val); |
212 | rtc_set_memory(s, 0x18, val >> 8); | |
213 | rtc_set_memory(s, 0x30, val); | |
214 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 215 | |
9da98861 FB |
216 | if (ram_size > (16 * 1024 * 1024)) |
217 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
218 | else | |
219 | val = 0; | |
80cabfad FB |
220 | if (val > 65535) |
221 | val = 65535; | |
b0a21b53 FB |
222 | rtc_set_memory(s, 0x34, val); |
223 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 224 | |
298e01b6 AJ |
225 | /* set the number of CPU */ |
226 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
227 | ||
6ac0e82d | 228 | /* set boot devices, and disable floppy signature check if requested */ |
28c5af54 JM |
229 | #define PC_MAX_BOOT_DEVICES 3 |
230 | nbds = strlen(boot_device); | |
231 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
232 | fprintf(stderr, "Too many boot devices for PC\n"); | |
233 | exit(1); | |
234 | } | |
235 | for (i = 0; i < nbds; i++) { | |
236 | bds[i] = boot_device2nibble(boot_device[i]); | |
237 | if (bds[i] == 0) { | |
238 | fprintf(stderr, "Invalid boot device for PC: '%c'\n", | |
239 | boot_device[i]); | |
240 | exit(1); | |
241 | } | |
242 | } | |
243 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
244 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
80cabfad | 245 | |
b41a2cd1 FB |
246 | /* floppy type */ |
247 | ||
baca51fa FB |
248 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
249 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 250 | |
777428f2 | 251 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 252 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 253 | |
b0a21b53 | 254 | val = 0; |
b41a2cd1 | 255 | nb = 0; |
80cabfad FB |
256 | if (fd0 < 3) |
257 | nb++; | |
258 | if (fd1 < 3) | |
259 | nb++; | |
260 | switch (nb) { | |
261 | case 0: | |
262 | break; | |
263 | case 1: | |
b0a21b53 | 264 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
265 | break; |
266 | case 2: | |
b0a21b53 | 267 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
268 | break; |
269 | } | |
b0a21b53 FB |
270 | val |= 0x02; /* FPU is there */ |
271 | val |= 0x04; /* PS/2 mouse installed */ | |
272 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
273 | ||
ba6c2377 FB |
274 | /* hard drives */ |
275 | ||
276 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
277 | if (hd_table[0]) | |
278 | cmos_init_hd(0x19, 0x1b, hd_table[0]); | |
5fafdf24 | 279 | if (hd_table[1]) |
ba6c2377 FB |
280 | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
281 | ||
282 | val = 0; | |
40b6ecc6 | 283 | for (i = 0; i < 4; i++) { |
ba6c2377 | 284 | if (hd_table[i]) { |
46d4767d FB |
285 | int cylinders, heads, sectors, translation; |
286 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
287 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
288 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
289 | geometry can be different if a translation is done. */ | |
290 | translation = bdrv_get_translation_hint(hd_table[i]); | |
291 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
292 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
293 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
294 | /* No translation. */ | |
295 | translation = 0; | |
296 | } else { | |
297 | /* LBA translation. */ | |
298 | translation = 1; | |
299 | } | |
40b6ecc6 | 300 | } else { |
46d4767d | 301 | translation--; |
ba6c2377 | 302 | } |
ba6c2377 FB |
303 | val |= translation << (i * 2); |
304 | } | |
40b6ecc6 | 305 | } |
ba6c2377 | 306 | rtc_set_memory(s, 0x39, val); |
80cabfad FB |
307 | } |
308 | ||
59b8ad81 FB |
309 | void ioport_set_a20(int enable) |
310 | { | |
311 | /* XXX: send to all CPUs ? */ | |
312 | cpu_x86_set_a20(first_cpu, enable); | |
313 | } | |
314 | ||
315 | int ioport_get_a20(void) | |
316 | { | |
317 | return ((first_cpu->a20_mask >> 20) & 1); | |
318 | } | |
319 | ||
e1a23744 FB |
320 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
321 | { | |
59b8ad81 | 322 | ioport_set_a20((val >> 1) & 1); |
e1a23744 FB |
323 | /* XXX: bit 0 is fast reset */ |
324 | } | |
325 | ||
326 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
327 | { | |
59b8ad81 | 328 | return ioport_get_a20() << 1; |
e1a23744 FB |
329 | } |
330 | ||
80cabfad FB |
331 | /***********************************************************/ |
332 | /* Bochs BIOS debug ports */ | |
333 | ||
9596ebb7 | 334 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 335 | { |
a2f659ee FB |
336 | static const char shutdown_str[8] = "Shutdown"; |
337 | static int shutdown_index = 0; | |
3b46e624 | 338 | |
80cabfad FB |
339 | switch(addr) { |
340 | /* Bochs BIOS messages */ | |
341 | case 0x400: | |
342 | case 0x401: | |
343 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
344 | exit(1); | |
345 | case 0x402: | |
346 | case 0x403: | |
347 | #ifdef DEBUG_BIOS | |
348 | fprintf(stderr, "%c", val); | |
349 | #endif | |
350 | break; | |
a2f659ee FB |
351 | case 0x8900: |
352 | /* same as Bochs power off */ | |
353 | if (val == shutdown_str[shutdown_index]) { | |
354 | shutdown_index++; | |
355 | if (shutdown_index == 8) { | |
356 | shutdown_index = 0; | |
357 | qemu_system_shutdown_request(); | |
358 | } | |
359 | } else { | |
360 | shutdown_index = 0; | |
361 | } | |
362 | break; | |
80cabfad FB |
363 | |
364 | /* LGPL'ed VGA BIOS messages */ | |
365 | case 0x501: | |
366 | case 0x502: | |
367 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
368 | exit(1); | |
369 | case 0x500: | |
370 | case 0x503: | |
371 | #ifdef DEBUG_BIOS | |
372 | fprintf(stderr, "%c", val); | |
373 | #endif | |
374 | break; | |
375 | } | |
376 | } | |
377 | ||
9596ebb7 | 378 | static void bochs_bios_init(void) |
80cabfad | 379 | { |
b41a2cd1 FB |
380 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
381 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
382 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
383 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 384 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
385 | |
386 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
387 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
388 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
389 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
80cabfad FB |
390 | } |
391 | ||
642a4f96 TS |
392 | /* Generate an initial boot sector which sets state and jump to |
393 | a specified vector */ | |
3f6c925f | 394 | static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
642a4f96 TS |
395 | { |
396 | uint8_t bootsect[512], *p; | |
397 | int i; | |
e4bcb14c | 398 | int hda; |
642a4f96 | 399 | |
e4bcb14c TS |
400 | hda = drive_get_index(IF_IDE, 0, 0); |
401 | if (hda == -1) { | |
642a4f96 TS |
402 | fprintf(stderr, "A disk image must be given for 'hda' when booting " |
403 | "a Linux kernel\n"); | |
404 | exit(1); | |
405 | } | |
406 | ||
407 | memset(bootsect, 0, sizeof(bootsect)); | |
408 | ||
409 | /* Copy the MSDOS partition table if possible */ | |
e4bcb14c | 410 | bdrv_read(drives_table[hda].bdrv, 0, bootsect, 1); |
642a4f96 TS |
411 | |
412 | /* Make sure we have a partition signature */ | |
413 | bootsect[510] = 0x55; | |
414 | bootsect[511] = 0xaa; | |
415 | ||
416 | /* Actual code */ | |
417 | p = bootsect; | |
418 | *p++ = 0xfa; /* CLI */ | |
419 | *p++ = 0xfc; /* CLD */ | |
420 | ||
421 | for (i = 0; i < 6; i++) { | |
422 | if (i == 1) /* Skip CS */ | |
423 | continue; | |
424 | ||
425 | *p++ = 0xb8; /* MOV AX,imm16 */ | |
426 | *p++ = segs[i]; | |
427 | *p++ = segs[i] >> 8; | |
428 | *p++ = 0x8e; /* MOV <seg>,AX */ | |
429 | *p++ = 0xc0 + (i << 3); | |
430 | } | |
431 | ||
432 | for (i = 0; i < 8; i++) { | |
433 | *p++ = 0x66; /* 32-bit operand size */ | |
434 | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ | |
435 | *p++ = gpr[i]; | |
436 | *p++ = gpr[i] >> 8; | |
437 | *p++ = gpr[i] >> 16; | |
438 | *p++ = gpr[i] >> 24; | |
439 | } | |
440 | ||
441 | *p++ = 0xea; /* JMP FAR */ | |
442 | *p++ = ip; /* IP */ | |
443 | *p++ = ip >> 8; | |
444 | *p++ = segs[1]; /* CS */ | |
445 | *p++ = segs[1] >> 8; | |
446 | ||
e4bcb14c | 447 | bdrv_set_boot_sector(drives_table[hda].bdrv, bootsect, sizeof(bootsect)); |
642a4f96 | 448 | } |
80cabfad | 449 | |
642a4f96 TS |
450 | static long get_file_size(FILE *f) |
451 | { | |
452 | long where, size; | |
453 | ||
454 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
455 | ||
456 | where = ftell(f); | |
457 | fseek(f, 0, SEEK_END); | |
458 | size = ftell(f); | |
459 | fseek(f, where, SEEK_SET); | |
460 | ||
461 | return size; | |
462 | } | |
463 | ||
464 | static void load_linux(const char *kernel_filename, | |
465 | const char *initrd_filename, | |
466 | const char *kernel_cmdline) | |
467 | { | |
468 | uint16_t protocol; | |
469 | uint32_t gpr[8]; | |
470 | uint16_t seg[6]; | |
471 | uint16_t real_seg; | |
472 | int setup_size, kernel_size, initrd_size, cmdline_size; | |
473 | uint32_t initrd_max; | |
474 | uint8_t header[1024]; | |
475 | uint8_t *real_addr, *prot_addr, *cmdline_addr, *initrd_addr; | |
476 | FILE *f, *fi; | |
477 | ||
478 | /* Align to 16 bytes as a paranoia measure */ | |
479 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
480 | ||
481 | /* load the kernel header */ | |
482 | f = fopen(kernel_filename, "rb"); | |
483 | if (!f || !(kernel_size = get_file_size(f)) || | |
484 | fread(header, 1, 1024, f) != 1024) { | |
485 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
486 | kernel_filename); | |
487 | exit(1); | |
488 | } | |
489 | ||
490 | /* kernel protocol version */ | |
bc4edd79 | 491 | #if 0 |
642a4f96 | 492 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 493 | #endif |
642a4f96 TS |
494 | if (ldl_p(header+0x202) == 0x53726448) |
495 | protocol = lduw_p(header+0x206); | |
496 | else | |
497 | protocol = 0; | |
498 | ||
499 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
500 | /* Low kernel */ | |
501 | real_addr = phys_ram_base + 0x90000; | |
502 | cmdline_addr = phys_ram_base + 0x9a000 - cmdline_size; | |
503 | prot_addr = phys_ram_base + 0x10000; | |
504 | } else if (protocol < 0x202) { | |
505 | /* High but ancient kernel */ | |
506 | real_addr = phys_ram_base + 0x90000; | |
507 | cmdline_addr = phys_ram_base + 0x9a000 - cmdline_size; | |
508 | prot_addr = phys_ram_base + 0x100000; | |
509 | } else { | |
510 | /* High and recent kernel */ | |
511 | real_addr = phys_ram_base + 0x10000; | |
512 | cmdline_addr = phys_ram_base + 0x20000; | |
513 | prot_addr = phys_ram_base + 0x100000; | |
514 | } | |
515 | ||
bc4edd79 | 516 | #if 0 |
642a4f96 TS |
517 | fprintf(stderr, |
518 | "qemu: real_addr = %#zx\n" | |
519 | "qemu: cmdline_addr = %#zx\n" | |
520 | "qemu: prot_addr = %#zx\n", | |
521 | real_addr-phys_ram_base, | |
522 | cmdline_addr-phys_ram_base, | |
523 | prot_addr-phys_ram_base); | |
bc4edd79 | 524 | #endif |
642a4f96 TS |
525 | |
526 | /* highest address for loading the initrd */ | |
527 | if (protocol >= 0x203) | |
528 | initrd_max = ldl_p(header+0x22c); | |
529 | else | |
530 | initrd_max = 0x37ffffff; | |
531 | ||
532 | if (initrd_max >= ram_size-ACPI_DATA_SIZE) | |
533 | initrd_max = ram_size-ACPI_DATA_SIZE-1; | |
534 | ||
535 | /* kernel command line */ | |
ffe8ab83 | 536 | pstrcpy((char*)cmdline_addr, 4096, kernel_cmdline); |
642a4f96 TS |
537 | |
538 | if (protocol >= 0x202) { | |
539 | stl_p(header+0x228, cmdline_addr-phys_ram_base); | |
540 | } else { | |
541 | stw_p(header+0x20, 0xA33F); | |
542 | stw_p(header+0x22, cmdline_addr-real_addr); | |
543 | } | |
544 | ||
545 | /* loader type */ | |
546 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
547 | If this code is substantially changed, you may want to consider | |
548 | incrementing the revision. */ | |
549 | if (protocol >= 0x200) | |
550 | header[0x210] = 0xB0; | |
551 | ||
552 | /* heap */ | |
553 | if (protocol >= 0x201) { | |
554 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
555 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
556 | } | |
557 | ||
558 | /* load initrd */ | |
559 | if (initrd_filename) { | |
560 | if (protocol < 0x200) { | |
561 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
562 | exit(1); | |
563 | } | |
564 | ||
565 | fi = fopen(initrd_filename, "rb"); | |
566 | if (!fi) { | |
567 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
568 | initrd_filename); | |
569 | exit(1); | |
570 | } | |
571 | ||
572 | initrd_size = get_file_size(fi); | |
573 | initrd_addr = phys_ram_base + ((initrd_max-initrd_size) & ~4095); | |
574 | ||
575 | fprintf(stderr, "qemu: loading initrd (%#x bytes) at %#zx\n", | |
576 | initrd_size, initrd_addr-phys_ram_base); | |
577 | ||
578 | if (fread(initrd_addr, 1, initrd_size, fi) != initrd_size) { | |
579 | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n", | |
580 | initrd_filename); | |
581 | exit(1); | |
582 | } | |
583 | fclose(fi); | |
584 | ||
585 | stl_p(header+0x218, initrd_addr-phys_ram_base); | |
586 | stl_p(header+0x21c, initrd_size); | |
587 | } | |
588 | ||
589 | /* store the finalized header and load the rest of the kernel */ | |
590 | memcpy(real_addr, header, 1024); | |
591 | ||
592 | setup_size = header[0x1f1]; | |
593 | if (setup_size == 0) | |
594 | setup_size = 4; | |
595 | ||
596 | setup_size = (setup_size+1)*512; | |
597 | kernel_size -= setup_size; /* Size of protected-mode code */ | |
598 | ||
599 | if (fread(real_addr+1024, 1, setup_size-1024, f) != setup_size-1024 || | |
600 | fread(prot_addr, 1, kernel_size, f) != kernel_size) { | |
601 | fprintf(stderr, "qemu: read error on kernel '%s'\n", | |
602 | kernel_filename); | |
603 | exit(1); | |
604 | } | |
605 | fclose(f); | |
606 | ||
607 | /* generate bootsector to set up the initial register state */ | |
608 | real_seg = (real_addr-phys_ram_base) >> 4; | |
609 | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; | |
610 | seg[1] = real_seg+0x20; /* CS */ | |
611 | memset(gpr, 0, sizeof gpr); | |
612 | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ | |
613 | ||
614 | generate_bootsect(gpr, seg, 0); | |
615 | } | |
616 | ||
59b8ad81 FB |
617 | static void main_cpu_reset(void *opaque) |
618 | { | |
619 | CPUState *env = opaque; | |
620 | cpu_reset(env); | |
621 | } | |
622 | ||
b41a2cd1 FB |
623 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
624 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
625 | static const int ide_irq[2] = { 14, 15 }; | |
626 | ||
627 | #define NE2000_NB_MAX 6 | |
628 | ||
8d11df9e | 629 | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
b41a2cd1 FB |
630 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
631 | ||
8d11df9e FB |
632 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
633 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
634 | ||
6508fe59 FB |
635 | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
636 | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
637 | ||
6a36d84e | 638 | #ifdef HAS_AUDIO |
d537cf6c | 639 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
640 | { |
641 | struct soundhw *c; | |
642 | int audio_enabled = 0; | |
643 | ||
644 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
645 | audio_enabled = c->enabled; | |
646 | } | |
647 | ||
648 | if (audio_enabled) { | |
649 | AudioState *s; | |
650 | ||
651 | s = AUD_init (); | |
652 | if (s) { | |
653 | for (c = soundhw; c->name; ++c) { | |
654 | if (c->enabled) { | |
655 | if (c->isa) { | |
d537cf6c | 656 | c->init.init_isa (s, pic); |
6a36d84e FB |
657 | } |
658 | else { | |
659 | if (pci_bus) { | |
660 | c->init.init_pci (pci_bus, s); | |
661 | } | |
662 | } | |
663 | } | |
664 | } | |
665 | } | |
666 | } | |
667 | } | |
668 | #endif | |
669 | ||
d537cf6c | 670 | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
a41b2ff2 PB |
671 | { |
672 | static int nb_ne2k = 0; | |
673 | ||
674 | if (nb_ne2k == NE2000_NB_MAX) | |
675 | return; | |
d537cf6c | 676 | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
a41b2ff2 PB |
677 | nb_ne2k++; |
678 | } | |
679 | ||
80cabfad | 680 | /* PC hardware initialisation */ |
03875444 | 681 | static void pc_init1(int ram_size, int vga_ram_size, |
b881c2c6 | 682 | const char *boot_device, DisplayState *ds, |
b5ff2d6e | 683 | const char *kernel_filename, const char *kernel_cmdline, |
3dbbdc25 | 684 | const char *initrd_filename, |
a049de61 | 685 | int pci_enabled, const char *cpu_model) |
80cabfad FB |
686 | { |
687 | char buf[1024]; | |
642a4f96 | 688 | int ret, linux_boot, i; |
970ac5a3 FB |
689 | ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset; |
690 | int bios_size, isa_bios_size, vga_bios_size; | |
46e50e9d | 691 | PCIBus *pci_bus; |
5c3ff3a7 | 692 | int piix3_devfn = -1; |
59b8ad81 | 693 | CPUState *env; |
a41b2ff2 | 694 | NICInfo *nd; |
d537cf6c PB |
695 | qemu_irq *cpu_irq; |
696 | qemu_irq *i8259; | |
e4bcb14c TS |
697 | int index; |
698 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
699 | BlockDriverState *fd[MAX_FD]; | |
d592d303 | 700 | |
80cabfad FB |
701 | linux_boot = (kernel_filename != NULL); |
702 | ||
59b8ad81 | 703 | /* init CPUs */ |
a049de61 FB |
704 | if (cpu_model == NULL) { |
705 | #ifdef TARGET_X86_64 | |
706 | cpu_model = "qemu64"; | |
707 | #else | |
708 | cpu_model = "qemu32"; | |
709 | #endif | |
710 | } | |
711 | ||
59b8ad81 | 712 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
713 | env = cpu_init(cpu_model); |
714 | if (!env) { | |
715 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
716 | exit(1); | |
717 | } | |
59b8ad81 | 718 | if (i != 0) |
ad49ff9d | 719 | env->hflags |= HF_HALTED_MASK; |
59b8ad81 FB |
720 | if (smp_cpus > 1) { |
721 | /* XXX: enable it in all cases */ | |
722 | env->cpuid_features |= CPUID_APIC; | |
723 | } | |
a5954d5c | 724 | register_savevm("cpu", i, 4, cpu_save, cpu_load, env); |
59b8ad81 FB |
725 | qemu_register_reset(main_cpu_reset, env); |
726 | if (pci_enabled) { | |
727 | apic_init(env); | |
728 | } | |
729 | } | |
730 | ||
26fb5e48 AJ |
731 | vmport_init(); |
732 | ||
80cabfad | 733 | /* allocate RAM */ |
970ac5a3 | 734 | ram_addr = qemu_ram_alloc(ram_size); |
03875444 | 735 | cpu_register_physical_memory(0, ram_size, ram_addr); |
80cabfad | 736 | |
970ac5a3 FB |
737 | /* allocate VGA RAM */ |
738 | vga_ram_addr = qemu_ram_alloc(vga_ram_size); | |
7587cf44 | 739 | |
970ac5a3 | 740 | /* BIOS load */ |
1192dad8 JM |
741 | if (bios_name == NULL) |
742 | bios_name = BIOS_FILENAME; | |
743 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
7587cf44 | 744 | bios_size = get_image_size(buf); |
5fafdf24 | 745 | if (bios_size <= 0 || |
970ac5a3 | 746 | (bios_size % 65536) != 0) { |
7587cf44 FB |
747 | goto bios_error; |
748 | } | |
970ac5a3 | 749 | bios_offset = qemu_ram_alloc(bios_size); |
7587cf44 FB |
750 | ret = load_image(buf, phys_ram_base + bios_offset); |
751 | if (ret != bios_size) { | |
752 | bios_error: | |
970ac5a3 | 753 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf); |
80cabfad FB |
754 | exit(1); |
755 | } | |
7587cf44 | 756 | |
80cabfad | 757 | /* VGA BIOS load */ |
de9258a8 FB |
758 | if (cirrus_vga_enabled) { |
759 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); | |
760 | } else { | |
761 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
762 | } | |
970ac5a3 | 763 | vga_bios_size = get_image_size(buf); |
5fafdf24 | 764 | if (vga_bios_size <= 0 || vga_bios_size > 65536) |
970ac5a3 FB |
765 | goto vga_bios_error; |
766 | vga_bios_offset = qemu_ram_alloc(65536); | |
767 | ||
7587cf44 | 768 | ret = load_image(buf, phys_ram_base + vga_bios_offset); |
970ac5a3 FB |
769 | if (ret != vga_bios_size) { |
770 | vga_bios_error: | |
771 | fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf); | |
772 | exit(1); | |
773 | } | |
774 | ||
80cabfad | 775 | /* setup basic memory access */ |
5fafdf24 | 776 | cpu_register_physical_memory(0xc0000, 0x10000, |
7587cf44 FB |
777 | vga_bios_offset | IO_MEM_ROM); |
778 | ||
779 | /* map the last 128KB of the BIOS in ISA space */ | |
780 | isa_bios_size = bios_size; | |
781 | if (isa_bios_size > (128 * 1024)) | |
782 | isa_bios_size = 128 * 1024; | |
5fafdf24 | 783 | cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size, |
7587cf44 | 784 | IO_MEM_UNASSIGNED); |
5fafdf24 TS |
785 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
786 | isa_bios_size, | |
7587cf44 | 787 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 788 | |
970ac5a3 FB |
789 | { |
790 | ram_addr_t option_rom_offset; | |
791 | int size, offset; | |
792 | ||
793 | offset = 0; | |
794 | for (i = 0; i < nb_option_roms; i++) { | |
795 | size = get_image_size(option_rom[i]); | |
796 | if (size < 0) { | |
5fafdf24 | 797 | fprintf(stderr, "Could not load option rom '%s'\n", |
970ac5a3 FB |
798 | option_rom[i]); |
799 | exit(1); | |
800 | } | |
801 | if (size > (0x10000 - offset)) | |
802 | goto option_rom_error; | |
803 | option_rom_offset = qemu_ram_alloc(size); | |
804 | ret = load_image(option_rom[i], phys_ram_base + option_rom_offset); | |
805 | if (ret != size) { | |
806 | option_rom_error: | |
807 | fprintf(stderr, "Too many option ROMS\n"); | |
808 | exit(1); | |
809 | } | |
810 | size = (size + 4095) & ~4095; | |
811 | cpu_register_physical_memory(0xd0000 + offset, | |
812 | size, option_rom_offset | IO_MEM_ROM); | |
813 | offset += size; | |
814 | } | |
9ae02555 TS |
815 | } |
816 | ||
7587cf44 | 817 | /* map all the bios at the top of memory */ |
5fafdf24 | 818 | cpu_register_physical_memory((uint32_t)(-bios_size), |
7587cf44 | 819 | bios_size, bios_offset | IO_MEM_ROM); |
3b46e624 | 820 | |
80cabfad FB |
821 | bochs_bios_init(); |
822 | ||
642a4f96 TS |
823 | if (linux_boot) |
824 | load_linux(kernel_filename, initrd_filename, kernel_cmdline); | |
80cabfad | 825 | |
a5b38b51 | 826 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
d537cf6c PB |
827 | i8259 = i8259_init(cpu_irq[0]); |
828 | ferr_irq = i8259[13]; | |
829 | ||
69b91039 | 830 | if (pci_enabled) { |
d537cf6c | 831 | pci_bus = i440fx_init(&i440fx_state, i8259); |
8f1c91d8 | 832 | piix3_devfn = piix3_init(pci_bus, -1); |
46e50e9d FB |
833 | } else { |
834 | pci_bus = NULL; | |
69b91039 FB |
835 | } |
836 | ||
80cabfad | 837 | /* init basic PC hardware */ |
b41a2cd1 | 838 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
80cabfad | 839 | |
f929aad6 FB |
840 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
841 | ||
1f04275e FB |
842 | if (cirrus_vga_enabled) { |
843 | if (pci_enabled) { | |
5fafdf24 TS |
844 | pci_cirrus_vga_init(pci_bus, |
845 | ds, phys_ram_base + vga_ram_addr, | |
970ac5a3 | 846 | vga_ram_addr, vga_ram_size); |
1f04275e | 847 | } else { |
5fafdf24 | 848 | isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 849 | vga_ram_addr, vga_ram_size); |
1f04275e | 850 | } |
d34cab9f TS |
851 | } else if (vmsvga_enabled) { |
852 | if (pci_enabled) | |
45e4522e AZ |
853 | pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
854 | vga_ram_addr, vga_ram_size); | |
d34cab9f TS |
855 | else |
856 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
1f04275e | 857 | } else { |
89b6b508 | 858 | if (pci_enabled) { |
5fafdf24 | 859 | pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 860 | vga_ram_addr, vga_ram_size, 0, 0); |
89b6b508 | 861 | } else { |
5fafdf24 | 862 | isa_vga_init(ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 863 | vga_ram_addr, vga_ram_size); |
89b6b508 | 864 | } |
1f04275e | 865 | } |
80cabfad | 866 | |
d537cf6c | 867 | rtc_state = rtc_init(0x70, i8259[8]); |
80cabfad | 868 | |
e1a23744 FB |
869 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
870 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
871 | ||
d592d303 | 872 | if (pci_enabled) { |
d592d303 FB |
873 | ioapic = ioapic_init(); |
874 | } | |
d537cf6c | 875 | pit = pit_init(0x40, i8259[0]); |
fd06c375 | 876 | pcspk_init(pit); |
d592d303 FB |
877 | if (pci_enabled) { |
878 | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); | |
879 | } | |
b41a2cd1 | 880 | |
8d11df9e FB |
881 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
882 | if (serial_hds[i]) { | |
d537cf6c | 883 | serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); |
8d11df9e FB |
884 | } |
885 | } | |
b41a2cd1 | 886 | |
6508fe59 FB |
887 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
888 | if (parallel_hds[i]) { | |
d537cf6c PB |
889 | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
890 | parallel_hds[i]); | |
6508fe59 FB |
891 | } |
892 | } | |
893 | ||
a41b2ff2 PB |
894 | for(i = 0; i < nb_nics; i++) { |
895 | nd = &nd_table[i]; | |
896 | if (!nd->model) { | |
897 | if (pci_enabled) { | |
898 | nd->model = "ne2k_pci"; | |
899 | } else { | |
900 | nd->model = "ne2k_isa"; | |
901 | } | |
69b91039 | 902 | } |
a41b2ff2 | 903 | if (strcmp(nd->model, "ne2k_isa") == 0) { |
d537cf6c | 904 | pc_init_ne2k_isa(nd, i8259); |
a41b2ff2 | 905 | } else if (pci_enabled) { |
c4a7060c BS |
906 | if (strcmp(nd->model, "?") == 0) |
907 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n"); | |
abcebc7e | 908 | pci_nic_init(pci_bus, nd, -1); |
c4a7060c BS |
909 | } else if (strcmp(nd->model, "?") == 0) { |
910 | fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n"); | |
911 | exit(1); | |
a41b2ff2 PB |
912 | } else { |
913 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
914 | exit(1); | |
69b91039 | 915 | } |
a41b2ff2 | 916 | } |
b41a2cd1 | 917 | |
e4bcb14c TS |
918 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
919 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
920 | exit(1); | |
921 | } | |
922 | ||
923 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
924 | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
925 | if (index != -1) | |
926 | hd[i] = drives_table[index].bdrv; | |
927 | else | |
928 | hd[i] = NULL; | |
929 | } | |
930 | ||
a41b2ff2 | 931 | if (pci_enabled) { |
e4bcb14c | 932 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); |
a41b2ff2 | 933 | } else { |
e4bcb14c | 934 | for(i = 0; i < MAX_IDE_BUS; i++) { |
d537cf6c | 935 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
e4bcb14c | 936 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); |
69b91039 | 937 | } |
b41a2cd1 | 938 | } |
69b91039 | 939 | |
d537cf6c | 940 | i8042_init(i8259[1], i8259[12], 0x60); |
7c29d0c0 | 941 | DMA_init(0); |
6a36d84e | 942 | #ifdef HAS_AUDIO |
d537cf6c | 943 | audio_init(pci_enabled ? pci_bus : NULL, i8259); |
fb065187 | 944 | #endif |
80cabfad | 945 | |
e4bcb14c TS |
946 | for(i = 0; i < MAX_FD; i++) { |
947 | index = drive_get_index(IF_FLOPPY, 0, i); | |
948 | if (index != -1) | |
949 | fd[i] = drives_table[index].bdrv; | |
950 | else | |
951 | fd[i] = NULL; | |
952 | } | |
953 | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); | |
b41a2cd1 | 954 | |
03875444 | 955 | cmos_init(ram_size, boot_device, hd); |
69b91039 | 956 | |
bb36d470 | 957 | if (pci_enabled && usb_enabled) { |
afcc3cdf | 958 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); |
bb36d470 FB |
959 | } |
960 | ||
6515b203 | 961 | if (pci_enabled && acpi_enabled) { |
3fffc223 | 962 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
0ff596d0 PB |
963 | i2c_bus *smbus; |
964 | ||
965 | /* TODO: Populate SPD eeprom data. */ | |
cf7a2fe2 | 966 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
3fffc223 | 967 | for (i = 0; i < 8; i++) { |
0ff596d0 | 968 | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); |
3fffc223 | 969 | } |
6515b203 | 970 | } |
3b46e624 | 971 | |
a5954d5c FB |
972 | if (i440fx_state) { |
973 | i440fx_init_memory_mappings(i440fx_state); | |
974 | } | |
e4bcb14c | 975 | |
7d8406be | 976 | if (pci_enabled) { |
e4bcb14c TS |
977 | int max_bus; |
978 | int bus, unit; | |
7d8406be | 979 | void *scsi; |
96d30e48 | 980 | |
e4bcb14c TS |
981 | max_bus = drive_get_max_bus(IF_SCSI); |
982 | ||
983 | for (bus = 0; bus <= max_bus; bus++) { | |
984 | scsi = lsi_scsi_init(pci_bus, -1); | |
985 | for (unit = 0; unit < LSI_MAX_DEVS; unit++) { | |
986 | index = drive_get_index(IF_SCSI, bus, unit); | |
987 | if (index == -1) | |
988 | continue; | |
989 | lsi_scsi_attach(scsi, drives_table[index].bdrv, unit); | |
990 | } | |
991 | } | |
7d8406be | 992 | } |
80cabfad | 993 | } |
b5ff2d6e | 994 | |
03875444 | 995 | static void pc_init_pci(int ram_size, int vga_ram_size, |
b881c2c6 | 996 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 997 | const char *kernel_filename, |
3dbbdc25 | 998 | const char *kernel_cmdline, |
94fc95cd JM |
999 | const char *initrd_filename, |
1000 | const char *cpu_model) | |
3dbbdc25 | 1001 | { |
b881c2c6 | 1002 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
3dbbdc25 | 1003 | kernel_filename, kernel_cmdline, |
a049de61 | 1004 | initrd_filename, 1, cpu_model); |
3dbbdc25 FB |
1005 | } |
1006 | ||
03875444 | 1007 | static void pc_init_isa(int ram_size, int vga_ram_size, |
b881c2c6 | 1008 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 1009 | const char *kernel_filename, |
3dbbdc25 | 1010 | const char *kernel_cmdline, |
94fc95cd JM |
1011 | const char *initrd_filename, |
1012 | const char *cpu_model) | |
3dbbdc25 | 1013 | { |
b881c2c6 | 1014 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
3dbbdc25 | 1015 | kernel_filename, kernel_cmdline, |
a049de61 | 1016 | initrd_filename, 0, cpu_model); |
3dbbdc25 FB |
1017 | } |
1018 | ||
b5ff2d6e FB |
1019 | QEMUMachine pc_machine = { |
1020 | "pc", | |
1021 | "Standard PC", | |
3dbbdc25 | 1022 | pc_init_pci, |
7fb4fdcf | 1023 | VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
3dbbdc25 FB |
1024 | }; |
1025 | ||
1026 | QEMUMachine isapc_machine = { | |
1027 | "isapc", | |
1028 | "ISA-only PC", | |
1029 | pc_init_isa, | |
7fb4fdcf | 1030 | VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, |
b5ff2d6e | 1031 | }; |