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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef HW_PC_H |
2 | #define HW_PC_H | |
376253ec AL |
3 | |
4 | #include "qemu-common.h" | |
35bed8ee | 5 | #include "ioport.h" |
376253ec | 6 | |
87ecb68b PB |
7 | /* PC-style peripherals (also used by other machines). */ |
8 | ||
9 | /* serial.c */ | |
10 | ||
b6cd0ea1 AJ |
11 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
12 | CharDriverState *chr); | |
c227f099 | 13 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, |
b6cd0ea1 AJ |
14 | qemu_irq irq, int baudbase, |
15 | CharDriverState *chr, int ioregister); | |
ac0be998 | 16 | SerialState *serial_isa_init(int index, CharDriverState *chr); |
038eaf82 | 17 | void serial_set_frequency(SerialState *s, uint32_t frequency); |
87ecb68b PB |
18 | |
19 | /* parallel.c */ | |
20 | ||
21 | typedef struct ParallelState ParallelState; | |
021f0674 | 22 | ParallelState *parallel_init(int index, CharDriverState *chr); |
c227f099 | 23 | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr); |
87ecb68b PB |
24 | |
25 | /* i8259.c */ | |
26 | ||
27 | typedef struct PicState2 PicState2; | |
28 | extern PicState2 *isa_pic; | |
29 | void pic_set_irq(int irq, int level); | |
30 | void pic_set_irq_new(void *opaque, int irq, int level); | |
31 | qemu_irq *i8259_init(qemu_irq parent_irq); | |
87ecb68b PB |
32 | int pic_read_irq(PicState2 *s); |
33 | void pic_update_irq(PicState2 *s); | |
34 | uint32_t pic_intack_read(PicState2 *s); | |
376253ec AL |
35 | void pic_info(Monitor *mon); |
36 | void irq_info(Monitor *mon); | |
87ecb68b PB |
37 | |
38 | /* APIC */ | |
39 | typedef struct IOAPICState IOAPICState; | |
610626af AL |
40 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
41 | uint8_t delivery_mode, | |
42 | uint8_t vector_num, uint8_t polarity, | |
43 | uint8_t trigger_mode); | |
87ecb68b PB |
44 | int apic_init(CPUState *env); |
45 | int apic_accept_pic_intr(CPUState *env); | |
1a7de94a | 46 | void apic_deliver_pic_intr(CPUState *env, int level); |
87ecb68b | 47 | int apic_get_interrupt(CPUState *env); |
1632dc6a | 48 | qemu_irq *ioapic_init(void); |
87ecb68b | 49 | void ioapic_set_irq(void *opaque, int vector, int level); |
73822ec8 AL |
50 | void apic_reset_irq_delivered(void); |
51 | int apic_get_irq_delivered(void); | |
87ecb68b PB |
52 | |
53 | /* i8254.c */ | |
54 | ||
55 | #define PIT_FREQ 1193182 | |
56 | ||
57 | typedef struct PITState PITState; | |
58 | ||
59 | PITState *pit_init(int base, qemu_irq irq); | |
60 | void pit_set_gate(PITState *pit, int channel, int val); | |
61 | int pit_get_gate(PITState *pit, int channel); | |
62 | int pit_get_initial_count(PITState *pit, int channel); | |
63 | int pit_get_mode(PITState *pit, int channel); | |
64 | int pit_get_out(PITState *pit, int channel, int64_t current_time); | |
65 | ||
bf4f74c0 AJ |
66 | void hpet_pit_disable(void); |
67 | void hpet_pit_enable(void); | |
68 | ||
87ecb68b | 69 | /* vmport.c */ |
26fb5e48 | 70 | void vmport_init(void); |
87ecb68b PB |
71 | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); |
72 | ||
73 | /* vmmouse.c */ | |
74 | void *vmmouse_init(void *m); | |
75 | ||
76 | /* pckbd.c */ | |
77 | ||
78 | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); | |
79 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, | |
c227f099 AL |
80 | target_phys_addr_t base, ram_addr_t size, |
81 | target_phys_addr_t mask); | |
87ecb68b PB |
82 | |
83 | /* mc146818rtc.c */ | |
84 | ||
85 | typedef struct RTCState RTCState; | |
86 | ||
32e0c826 | 87 | RTCState *rtc_init(int base_year); |
87ecb68b PB |
88 | void rtc_set_memory(RTCState *s, int addr, int val); |
89 | void rtc_set_date(RTCState *s, const struct tm *tm); | |
0bacd130 | 90 | void cmos_set_s3_resume(void); |
87ecb68b PB |
91 | |
92 | /* pc.c */ | |
93 | extern int fd_bootchk; | |
94 | ||
95 | void ioport_set_a20(int enable); | |
96 | int ioport_get_a20(void); | |
97 | ||
98 | /* acpi.c */ | |
99 | extern int acpi_enabled; | |
80deece2 BS |
100 | extern char *acpi_tables; |
101 | extern size_t acpi_tables_len; | |
102 | ||
9d5e77a2 IY |
103 | void acpi_bios_init(void); |
104 | int acpi_table_add(const char *table_desc); | |
105 | ||
106 | /* acpi_piix.c */ | |
cf7a2fe2 AJ |
107 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
108 | qemu_irq sci_irq); | |
87ecb68b | 109 | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); |
3f84865a | 110 | void piix4_acpi_system_hot_add_init(PCIBus *bus); |
87ecb68b | 111 | |
16b29ae1 AL |
112 | /* hpet.c */ |
113 | extern int no_hpet; | |
114 | ||
87ecb68b PB |
115 | /* pcspk.c */ |
116 | void pcspk_init(PITState *); | |
22d83b14 | 117 | int pcspk_audio_init(qemu_irq *pic); |
87ecb68b PB |
118 | |
119 | /* piix_pci.c */ | |
0a3bacf3 JQ |
120 | struct PCII440FXState; |
121 | typedef struct PCII440FXState PCII440FXState; | |
122 | ||
85a750ca | 123 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic); |
0a3bacf3 | 124 | void i440fx_set_smm(PCII440FXState *d, int val); |
0a3bacf3 | 125 | void i440fx_init_memory_mappings(PCII440FXState *d); |
87ecb68b | 126 | |
823e675a | 127 | /* piix4.c */ |
b1d8e52e | 128 | extern PCIDevice *piix4_dev; |
87ecb68b PB |
129 | int piix4_init(PCIBus *bus, int devfn); |
130 | ||
131 | /* vga.c */ | |
cb5a7aa8 | 132 | enum vga_retrace_method { |
133 | VGA_RETRACE_DUMB, | |
134 | VGA_RETRACE_PRECISE | |
135 | }; | |
136 | ||
137 | extern enum vga_retrace_method vga_retrace_method; | |
87ecb68b | 138 | |
fbe1b595 PB |
139 | int isa_vga_init(void); |
140 | int pci_vga_init(PCIBus *bus, | |
87ecb68b | 141 | unsigned long vga_bios_offset, int vga_bios_size); |
c227f099 AL |
142 | int isa_vga_mm_init(target_phys_addr_t vram_base, |
143 | target_phys_addr_t ctrl_base, int it_shift); | |
87ecb68b PB |
144 | |
145 | /* cirrus_vga.c */ | |
fbe1b595 PB |
146 | void pci_cirrus_vga_init(PCIBus *bus); |
147 | void isa_cirrus_vga_init(void); | |
87ecb68b | 148 | |
87ecb68b PB |
149 | /* ne2000.c */ |
150 | ||
9453c5bc | 151 | void isa_ne2000_init(int base, int irq, NICInfo *nd); |
87ecb68b | 152 | |
678e12cc | 153 | int cpu_is_bsp(CPUState *env); |
4c5b10b7 JS |
154 | |
155 | /* e820 types */ | |
156 | #define E820_RAM 1 | |
157 | #define E820_RESERVED 2 | |
158 | #define E820_ACPI 3 | |
159 | #define E820_NVS 4 | |
160 | #define E820_UNUSABLE 5 | |
161 | ||
162 | int e820_add_entry(uint64_t, uint64_t, uint32_t); | |
163 | ||
87ecb68b | 164 | #endif |