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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef HW_PC_H |
2 | #define HW_PC_H | |
376253ec AL |
3 | |
4 | #include "qemu-common.h" | |
5 | ||
87ecb68b PB |
6 | /* PC-style peripherals (also used by other machines). */ |
7 | ||
8 | /* serial.c */ | |
9 | ||
b6cd0ea1 AJ |
10 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
11 | CharDriverState *chr); | |
87ecb68b | 12 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, |
b6cd0ea1 AJ |
13 | qemu_irq irq, int baudbase, |
14 | CharDriverState *chr, int ioregister); | |
87ecb68b PB |
15 | |
16 | /* parallel.c */ | |
17 | ||
18 | typedef struct ParallelState ParallelState; | |
19 | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr); | |
20 | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr); | |
21 | ||
22 | /* i8259.c */ | |
23 | ||
24 | typedef struct PicState2 PicState2; | |
25 | extern PicState2 *isa_pic; | |
26 | void pic_set_irq(int irq, int level); | |
27 | void pic_set_irq_new(void *opaque, int irq, int level); | |
28 | qemu_irq *i8259_init(qemu_irq parent_irq); | |
87ecb68b PB |
29 | int pic_read_irq(PicState2 *s); |
30 | void pic_update_irq(PicState2 *s); | |
31 | uint32_t pic_intack_read(PicState2 *s); | |
376253ec AL |
32 | void pic_info(Monitor *mon); |
33 | void irq_info(Monitor *mon); | |
87ecb68b PB |
34 | |
35 | /* APIC */ | |
36 | typedef struct IOAPICState IOAPICState; | |
610626af AL |
37 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
38 | uint8_t delivery_mode, | |
39 | uint8_t vector_num, uint8_t polarity, | |
40 | uint8_t trigger_mode); | |
87ecb68b PB |
41 | int apic_init(CPUState *env); |
42 | int apic_accept_pic_intr(CPUState *env); | |
1a7de94a | 43 | void apic_deliver_pic_intr(CPUState *env, int level); |
87ecb68b | 44 | int apic_get_interrupt(CPUState *env); |
1632dc6a | 45 | qemu_irq *ioapic_init(void); |
87ecb68b | 46 | void ioapic_set_irq(void *opaque, int vector, int level); |
73822ec8 AL |
47 | void apic_reset_irq_delivered(void); |
48 | int apic_get_irq_delivered(void); | |
87ecb68b PB |
49 | |
50 | /* i8254.c */ | |
51 | ||
52 | #define PIT_FREQ 1193182 | |
53 | ||
54 | typedef struct PITState PITState; | |
55 | ||
56 | PITState *pit_init(int base, qemu_irq irq); | |
57 | void pit_set_gate(PITState *pit, int channel, int val); | |
58 | int pit_get_gate(PITState *pit, int channel); | |
59 | int pit_get_initial_count(PITState *pit, int channel); | |
60 | int pit_get_mode(PITState *pit, int channel); | |
61 | int pit_get_out(PITState *pit, int channel, int64_t current_time); | |
62 | ||
bf4f74c0 AJ |
63 | void hpet_pit_disable(void); |
64 | void hpet_pit_enable(void); | |
65 | ||
87ecb68b | 66 | /* vmport.c */ |
26fb5e48 | 67 | void vmport_init(void); |
87ecb68b PB |
68 | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); |
69 | ||
70 | /* vmmouse.c */ | |
71 | void *vmmouse_init(void *m); | |
72 | ||
73 | /* pckbd.c */ | |
74 | ||
75 | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); | |
76 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, | |
4efbe58f AJ |
77 | target_phys_addr_t base, ram_addr_t size, |
78 | target_phys_addr_t mask); | |
87ecb68b PB |
79 | |
80 | /* mc146818rtc.c */ | |
81 | ||
82 | typedef struct RTCState RTCState; | |
83 | ||
42fc73a1 | 84 | RTCState *rtc_init(int base, qemu_irq irq, int base_year); |
100d9891 | 85 | RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year); |
42fc73a1 AJ |
86 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, |
87 | int base_year); | |
87ecb68b PB |
88 | void rtc_set_memory(RTCState *s, int addr, int val); |
89 | void rtc_set_date(RTCState *s, const struct tm *tm); | |
0bacd130 | 90 | void cmos_set_s3_resume(void); |
87ecb68b PB |
91 | |
92 | /* pc.c */ | |
93 | extern int fd_bootchk; | |
94 | ||
95 | void ioport_set_a20(int enable); | |
96 | int ioport_get_a20(void); | |
97 | ||
98 | /* acpi.c */ | |
99 | extern int acpi_enabled; | |
80deece2 BS |
100 | extern char *acpi_tables; |
101 | extern size_t acpi_tables_len; | |
102 | ||
9d5e77a2 IY |
103 | void acpi_bios_init(void); |
104 | int acpi_table_add(const char *table_desc); | |
105 | ||
106 | /* acpi_piix.c */ | |
cf7a2fe2 AJ |
107 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
108 | qemu_irq sci_irq); | |
87ecb68b | 109 | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); |
9d5e77a2 | 110 | void piix4_acpi_system_hot_add_init(void); |
87ecb68b | 111 | |
16b29ae1 AL |
112 | /* hpet.c */ |
113 | extern int no_hpet; | |
114 | ||
87ecb68b PB |
115 | /* pcspk.c */ |
116 | void pcspk_init(PITState *); | |
22d83b14 | 117 | int pcspk_audio_init(qemu_irq *pic); |
87ecb68b PB |
118 | |
119 | /* piix_pci.c */ | |
0a3bacf3 JQ |
120 | struct PCII440FXState; |
121 | typedef struct PCII440FXState PCII440FXState; | |
122 | ||
85a750ca | 123 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic); |
0a3bacf3 | 124 | void i440fx_set_smm(PCII440FXState *d, int val); |
0a3bacf3 | 125 | void i440fx_init_memory_mappings(PCII440FXState *d); |
87ecb68b | 126 | |
823e675a | 127 | /* piix4.c */ |
b1d8e52e | 128 | extern PCIDevice *piix4_dev; |
87ecb68b PB |
129 | int piix4_init(PCIBus *bus, int devfn); |
130 | ||
131 | /* vga.c */ | |
cb5a7aa8 | 132 | enum vga_retrace_method { |
133 | VGA_RETRACE_DUMB, | |
134 | VGA_RETRACE_PRECISE | |
135 | }; | |
136 | ||
137 | extern enum vga_retrace_method vga_retrace_method; | |
87ecb68b | 138 | |
fbe1b595 PB |
139 | int isa_vga_init(void); |
140 | int pci_vga_init(PCIBus *bus, | |
87ecb68b | 141 | unsigned long vga_bios_offset, int vga_bios_size); |
fbe1b595 | 142 | int isa_vga_mm_init(target_phys_addr_t vram_base, |
b584726d | 143 | target_phys_addr_t ctrl_base, int it_shift); |
87ecb68b PB |
144 | |
145 | /* cirrus_vga.c */ | |
fbe1b595 PB |
146 | void pci_cirrus_vga_init(PCIBus *bus); |
147 | void isa_cirrus_vga_init(void); | |
87ecb68b | 148 | |
87ecb68b PB |
149 | /* ne2000.c */ |
150 | ||
151 | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); | |
152 | ||
678e12cc | 153 | int cpu_is_bsp(CPUState *env); |
87ecb68b | 154 | #endif |