[mirror_qemu.git] / hw / pc.h

#ifndef HW_PC_H
#define HW_PC_H

#include "qemu-common.h"
#include "ioport.h"
#include "isa.h"
#include "fdc.h"
#include "net.h"

/* PC-style peripherals (also used by other machines).  */

/* serial.c */

SerialState *serial_init(int base, qemu_irq irq, int baudbase,
                         CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, int baudbase,
                             CharDriverState *chr, int ioregister,
                             int be);
static inline bool serial_isa_init(int index, CharDriverState *chr)
{
    ISADevice *dev;

    dev = isa_try_create("isa-serial");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "index", index);
    qdev_prop_set_chr(&dev->qdev, "chardev", chr);
    if (qdev_init(&dev->qdev) < 0) {
        return false;
    }
    return true;
}

void serial_set_frequency(SerialState *s, uint32_t frequency);

/* parallel.c */
static inline bool parallel_init(int index, CharDriverState *chr)
{
    ISADevice *dev;

    dev = isa_try_create("isa-parallel");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "index", index);
    qdev_prop_set_chr(&dev->qdev, "chardev", chr);
    if (qdev_init(&dev->qdev) < 0) {
        return false;
    }
    return true;
}

bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
                      CharDriverState *chr);

/* i8259.c */

typedef struct PicState2 PicState2;
extern PicState2 *isa_pic;
void pic_set_irq(int irq, int level);
void pic_set_irq_new(void *opaque, int irq, int level);
qemu_irq *i8259_init(qemu_irq parent_irq);
int pic_read_irq(PicState2 *s);
void pic_update_irq(PicState2 *s);
uint32_t pic_intack_read(PicState2 *s);
void pic_info(Monitor *mon);
void irq_info(Monitor *mon);

/* ISA */
#define IOAPIC_NUM_PINS 0x18

typedef struct isa_irq_state {
    qemu_irq *i8259;
    qemu_irq ioapic[IOAPIC_NUM_PINS];
} IsaIrqState;

void isa_irq_handler(void *opaque, int n, int level);

/* i8254.c */

#define PIT_FREQ 1193182

typedef struct PITState PITState;

PITState *pit_init(int base, qemu_irq irq);
void pit_set_gate(PITState *pit, int channel, int val);
int pit_get_gate(PITState *pit, int channel);
int pit_get_initial_count(PITState *pit, int channel);
int pit_get_mode(PITState *pit, int channel);
int pit_get_out(PITState *pit, int channel, int64_t current_time);

void hpet_pit_disable(void);
void hpet_pit_enable(void);

/* vmport.c */
static inline void vmport_init(void)
{
    isa_create_simple("vmport");
}
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   target_phys_addr_t base, ram_addr_t size,
                   target_phys_addr_t mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);

/* pc.c */
extern int fd_bootchk;

void pc_register_ferr_irq(qemu_irq irq);
void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);

void pc_cpus_init(const char *cpu_model);
void pc_memory_init(ram_addr_t ram_size,
                    const char *kernel_filename,
                    const char *kernel_cmdline,
                    const char *initrd_filename,
                    ram_addr_t *below_4g_mem_size_p,
                    ram_addr_t *above_4g_mem_size_p);
qemu_irq *pc_allocate_cpu_irq(void);
void pc_vga_init(PCIBus *pci_bus);
void pc_basic_device_init(qemu_irq *isa_irq,
                          FDCtrl **floppy_controller,
                          ISADevice **rtc_state);
void pc_init_ne2k_isa(NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                  const char *boot_device,
                  BusState *ide0, BusState *ide1,
                  FDCtrl *floppy_controller, ISADevice *s);
void pc_pci_device_init(PCIBus *pci_bus);

typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);

/* acpi.c */
extern int acpi_enabled;
extern char *acpi_tables;
extern size_t acpi_tables_len;

void acpi_bios_init(void);
int acpi_table_add(const char *table_desc);

/* acpi_piix.c */

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                       int kvm_enabled);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);

/* hpet.c */
extern int no_hpet;

/* pcspk.c */
void pcspk_init(PITState *);
int pcspk_audio_init(qemu_irq *pic);

/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
void i440fx_init_memory_mappings(PCII440FXState *d);

/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, int devfn);

/* vga.c */
enum vga_retrace_method {
    VGA_RETRACE_DUMB,
    VGA_RETRACE_PRECISE
};

extern enum vga_retrace_method vga_retrace_method;

int isa_vga_init(void);
int pci_vga_init(PCIBus *bus);
int isa_vga_mm_init(target_phys_addr_t vram_base,
                    target_phys_addr_t ctrl_base, int it_shift);

/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
void isa_cirrus_vga_init(void);

/* ne2000.c */
static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
{
    ISADevice *dev;

    qemu_check_nic_model(nd, "ne2k_isa");

    dev = isa_try_create("ne2k_isa");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "iobase", base);
    qdev_prop_set_uint32(&dev->qdev, "irq",    irq);
    qdev_set_nic_properties(&dev->qdev, nd);
    qdev_init_nofail(&dev->qdev);
    return true;
}

/* e820 types */
#define E820_RAM        1
#define E820_RESERVED   2
#define E820_ACPI       3
#define E820_NVS        4
#define E820_UNUSABLE   5

int e820_add_entry(uint64_t, uint64_t, uint32_t);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
87ecb68b PB	2	#define HW_PC_H
376253ec AL	3
376253ec AL	4	#include "qemu-common.h"
35bed8ee	5	#include "ioport.h"
845773ab IY	6	#include "isa.h"
845773ab IY	7	#include "fdc.h"
cd1b8a8b	8	#include "net.h"
376253ec	9
87ecb68b PB	10	/* PC-style peripherals (also used by other machines). */
	11
	12	/* serial.c */
	13
b6cd0ea1 AJ	14	SerialState *serial_init(int base, qemu_irq irq, int baudbase,
b6cd0ea1 AJ	15	CharDriverState *chr);
c227f099	16	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
b6cd0ea1	17	qemu_irq irq, int baudbase,
2d48377a BS	18	CharDriverState *chr, int ioregister,
2d48377a BS	19	int be);
e22cf21e BS	20	static inline bool serial_isa_init(int index, CharDriverState *chr)
	21	{
	22	ISADevice *dev;
	23
9b13ef9f BS	24	dev = isa_try_create("isa-serial");
	25	if (!dev) {
	26	return false;
	27	}
e22cf21e BS	28	qdev_prop_set_uint32(&dev->qdev, "index", index);
	29	qdev_prop_set_chr(&dev->qdev, "chardev", chr);
	30	if (qdev_init(&dev->qdev) < 0) {
	31	return false;
	32	}
	33	return true;
	34	}
	35
038eaf82	36	void serial_set_frequency(SerialState *s, uint32_t frequency);
87ecb68b PB	37
87ecb68b PB	38	/* parallel.c */
defdb20e BS	39	static inline bool parallel_init(int index, CharDriverState *chr)
	40	{
	41	ISADevice *dev;
	42
73531538 BS	43	dev = isa_try_create("isa-parallel");
	44	if (!dev) {
	45	return false;
	46	}
defdb20e BS	47	qdev_prop_set_uint32(&dev->qdev, "index", index);
	48	qdev_prop_set_chr(&dev->qdev, "chardev", chr);
	49	if (qdev_init(&dev->qdev) < 0) {
	50	return false;
	51	}
	52	return true;
	53	}
	54
	55	bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
	56	CharDriverState *chr);
87ecb68b PB	57
	58	/* i8259.c */
	59
	60	typedef struct PicState2 PicState2;
	61	extern PicState2 *isa_pic;
	62	void pic_set_irq(int irq, int level);
	63	void pic_set_irq_new(void *opaque, int irq, int level);
	64	qemu_irq *i8259_init(qemu_irq parent_irq);
87ecb68b PB	65	int pic_read_irq(PicState2 *s);
	66	void pic_update_irq(PicState2 *s);
	67	uint32_t pic_intack_read(PicState2 *s);
376253ec AL	68	void pic_info(Monitor *mon);
376253ec AL	69	void irq_info(Monitor *mon);
87ecb68b	70
845773ab	71	/* ISA */
96051119 BS	72	#define IOAPIC_NUM_PINS 0x18
96051119 BS	73
845773ab IY	74	typedef struct isa_irq_state {
845773ab IY	75	qemu_irq *i8259;
96051119	76	qemu_irq ioapic[IOAPIC_NUM_PINS];
845773ab IY	77	} IsaIrqState;
	78
	79	void isa_irq_handler(void *opaque, int n, int level);
	80
87ecb68b PB	81	/* i8254.c */
	82
	83	#define PIT_FREQ 1193182
	84
	85	typedef struct PITState PITState;
	86
	87	PITState *pit_init(int base, qemu_irq irq);
	88	void pit_set_gate(PITState *pit, int channel, int val);
	89	int pit_get_gate(PITState *pit, int channel);
	90	int pit_get_initial_count(PITState *pit, int channel);
	91	int pit_get_mode(PITState *pit, int channel);
	92	int pit_get_out(PITState *pit, int channel, int64_t current_time);
	93
bf4f74c0 AJ	94	void hpet_pit_disable(void);
	95	void hpet_pit_enable(void);
	96
87ecb68b	97	/* vmport.c */
6872ef61 BS	98	static inline void vmport_init(void)
	99	{
	100	isa_create_simple("vmport");
	101	}
87ecb68b	102	void vmport_register(unsigned char command, IOPortReadFunc func, void opaque);
86d86414 BS	103	void vmmouse_get_data(uint32_t *data);
86d86414 BS	104	void vmmouse_set_data(const uint32_t *data);
87ecb68b	105
87ecb68b PB	106	/* pckbd.c */
	107
	108	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	109	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
c227f099 AL	110	target_phys_addr_t base, ram_addr_t size,
c227f099 AL	111	target_phys_addr_t mask);
956a3e6b BS	112	void i8042_isa_mouse_fake_event(void *opaque);
956a3e6b BS	113	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out);
87ecb68b	114
87ecb68b PB	115	/* pc.c */
	116	extern int fd_bootchk;
	117
8e78eb28	118	void pc_register_ferr_irq(qemu_irq irq);
845773ab IY	119	void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
	120	void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
	121
	122	void pc_cpus_init(const char *cpu_model);
	123	void pc_memory_init(ram_addr_t ram_size,
	124	const char *kernel_filename,
	125	const char *kernel_cmdline,
	126	const char *initrd_filename,
	127	ram_addr_t *below_4g_mem_size_p,
	128	ram_addr_t *above_4g_mem_size_p);
	129	qemu_irq *pc_allocate_cpu_irq(void);
	130	void pc_vga_init(PCIBus *pci_bus);
	131	void pc_basic_device_init(qemu_irq *isa_irq,
	132	FDCtrl **floppy_controller,
1d914fa0	133	ISADevice **rtc_state);
845773ab	134	void pc_init_ne2k_isa(NICInfo *nd);
845773ab	135	void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
c0897e0c MA	136	const char *boot_device,
c0897e0c MA	137	BusState ide0, BusState ide1,
1d914fa0	138	FDCtrl floppy_controller, ISADevice s);
845773ab	139	void pc_pci_device_init(PCIBus *pci_bus);
8e78eb28	140
f885f1ea IY	141	typedef void (cpu_set_smm_t)(int smm, void arg);
	142	void cpu_smm_register(cpu_set_smm_t callback, void *arg);
	143
87ecb68b PB	144	/* acpi.c */
87ecb68b PB	145	extern int acpi_enabled;
80deece2 BS	146	extern char *acpi_tables;
	147	extern size_t acpi_tables_len;
	148
9d5e77a2 IY	149	void acpi_bios_init(void);
	150	int acpi_table_add(const char *table_desc);
	151
	152	/* acpi_piix.c */
53b67b30	153
cf7a2fe2	154	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
53b67b30 BS	155	qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
53b67b30 BS	156	int kvm_enabled);
87ecb68b	157	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
87ecb68b	158
16b29ae1 AL	159	/* hpet.c */
	160	extern int no_hpet;
	161
87ecb68b PB	162	/* pcspk.c */
87ecb68b PB	163	void pcspk_init(PITState *);
22d83b14	164	int pcspk_audio_init(qemu_irq *pic);
87ecb68b PB	165
87ecb68b PB	166	/* piix_pci.c */
0a3bacf3 JQ	167	struct PCII440FXState;
	168	typedef struct PCII440FXState PCII440FXState;
	169
97679527	170	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
0a3bacf3	171	void i440fx_init_memory_mappings(PCII440FXState *d);
87ecb68b	172
823e675a	173	/* piix4.c */
b1d8e52e	174	extern PCIDevice *piix4_dev;
87ecb68b PB	175	int piix4_init(PCIBus *bus, int devfn);
	176
	177	/* vga.c */
cb5a7aa8	178	enum vga_retrace_method {
	179	VGA_RETRACE_DUMB,
	180	VGA_RETRACE_PRECISE
	181	};
	182
	183	extern enum vga_retrace_method vga_retrace_method;
87ecb68b	184
fbe1b595	185	int isa_vga_init(void);
78895427	186	int pci_vga_init(PCIBus *bus);
c227f099 AL	187	int isa_vga_mm_init(target_phys_addr_t vram_base,
c227f099 AL	188	target_phys_addr_t ctrl_base, int it_shift);
87ecb68b PB	189
87ecb68b PB	190	/* cirrus_vga.c */
fbe1b595 PB	191	void pci_cirrus_vga_init(PCIBus *bus);
fbe1b595 PB	192	void isa_cirrus_vga_init(void);
87ecb68b	193
87ecb68b	194	/* ne2000.c */
cd1b8a8b	195	static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
60a14ad3 BS	196	{
60a14ad3 BS	197	ISADevice *dev;
87ecb68b	198
60a14ad3 BS	199	qemu_check_nic_model(nd, "ne2k_isa");
60a14ad3 BS	200
cd1b8a8b BS	201	dev = isa_try_create("ne2k_isa");
	202	if (!dev) {
	203	return false;
	204	}
60a14ad3 BS	205	qdev_prop_set_uint32(&dev->qdev, "iobase", base);
	206	qdev_prop_set_uint32(&dev->qdev, "irq", irq);
	207	qdev_set_nic_properties(&dev->qdev, nd);
	208	qdev_init_nofail(&dev->qdev);
cd1b8a8b	209	return true;
60a14ad3	210	}
87ecb68b	211
4c5b10b7 JS	212	/* e820 types */
	213	#define E820_RAM 1
	214	#define E820_RESERVED 2
	215	#define E820_ACPI 3
	216	#define E820_NVS 4
	217	#define E820_UNUSABLE 5
	218
	219	int e820_add_entry(uint64_t, uint64_t, uint32_t);
	220
87ecb68b	221	#endif