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serial: refactor device creation
[mirror_qemu.git] / hw / pc.h
CommitLineData
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1#ifndef HW_PC_H
2#define HW_PC_H
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3
4#include "qemu-common.h"
35bed8ee 5#include "ioport.h"
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6#include "isa.h"
7#include "fdc.h"
cd1b8a8b 8#include "net.h"
376253ec 9
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10/* PC-style peripherals (also used by other machines). */
11
12/* serial.c */
13
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14SerialState *serial_init(int base, qemu_irq irq, int baudbase,
15 CharDriverState *chr);
c227f099 16SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
b6cd0ea1 17 qemu_irq irq, int baudbase,
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18 CharDriverState *chr, int ioregister,
19 int be);
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20static inline bool serial_isa_init(int index, CharDriverState *chr)
21{
22 ISADevice *dev;
23
24 dev = isa_create("isa-serial");
25 qdev_prop_set_uint32(&dev->qdev, "index", index);
26 qdev_prop_set_chr(&dev->qdev, "chardev", chr);
27 if (qdev_init(&dev->qdev) < 0) {
28 return false;
29 }
30 return true;
31}
32
038eaf82 33void serial_set_frequency(SerialState *s, uint32_t frequency);
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34
35/* parallel.c */
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36static inline bool parallel_init(int index, CharDriverState *chr)
37{
38 ISADevice *dev;
39
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40 dev = isa_try_create("isa-parallel");
41 if (!dev) {
42 return false;
43 }
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44 qdev_prop_set_uint32(&dev->qdev, "index", index);
45 qdev_prop_set_chr(&dev->qdev, "chardev", chr);
46 if (qdev_init(&dev->qdev) < 0) {
47 return false;
48 }
49 return true;
50}
51
52bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
53 CharDriverState *chr);
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54
55/* i8259.c */
56
57typedef struct PicState2 PicState2;
58extern PicState2 *isa_pic;
59void pic_set_irq(int irq, int level);
60void pic_set_irq_new(void *opaque, int irq, int level);
61qemu_irq *i8259_init(qemu_irq parent_irq);
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62int pic_read_irq(PicState2 *s);
63void pic_update_irq(PicState2 *s);
64uint32_t pic_intack_read(PicState2 *s);
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65void pic_info(Monitor *mon);
66void irq_info(Monitor *mon);
87ecb68b 67
845773ab 68/* ISA */
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69#define IOAPIC_NUM_PINS 0x18
70
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71typedef struct isa_irq_state {
72 qemu_irq *i8259;
96051119 73 qemu_irq ioapic[IOAPIC_NUM_PINS];
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74} IsaIrqState;
75
76void isa_irq_handler(void *opaque, int n, int level);
77
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78/* i8254.c */
79
80#define PIT_FREQ 1193182
81
82typedef struct PITState PITState;
83
84PITState *pit_init(int base, qemu_irq irq);
85void pit_set_gate(PITState *pit, int channel, int val);
86int pit_get_gate(PITState *pit, int channel);
87int pit_get_initial_count(PITState *pit, int channel);
88int pit_get_mode(PITState *pit, int channel);
89int pit_get_out(PITState *pit, int channel, int64_t current_time);
90
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91void hpet_pit_disable(void);
92void hpet_pit_enable(void);
93
87ecb68b 94/* vmport.c */
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95static inline void vmport_init(void)
96{
97 isa_create_simple("vmport");
98}
87ecb68b 99void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
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100void vmmouse_get_data(uint32_t *data);
101void vmmouse_set_data(const uint32_t *data);
87ecb68b 102
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103/* pckbd.c */
104
105void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
106void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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107 target_phys_addr_t base, ram_addr_t size,
108 target_phys_addr_t mask);
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109void i8042_isa_mouse_fake_event(void *opaque);
110void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
87ecb68b 111
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112/* pc.c */
113extern int fd_bootchk;
114
8e78eb28 115void pc_register_ferr_irq(qemu_irq irq);
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116void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
117void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
118
119void pc_cpus_init(const char *cpu_model);
120void pc_memory_init(ram_addr_t ram_size,
121 const char *kernel_filename,
122 const char *kernel_cmdline,
123 const char *initrd_filename,
124 ram_addr_t *below_4g_mem_size_p,
125 ram_addr_t *above_4g_mem_size_p);
126qemu_irq *pc_allocate_cpu_irq(void);
127void pc_vga_init(PCIBus *pci_bus);
128void pc_basic_device_init(qemu_irq *isa_irq,
129 FDCtrl **floppy_controller,
1d914fa0 130 ISADevice **rtc_state);
845773ab 131void pc_init_ne2k_isa(NICInfo *nd);
845773ab 132void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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133 const char *boot_device,
134 BusState *ide0, BusState *ide1,
1d914fa0 135 FDCtrl *floppy_controller, ISADevice *s);
845773ab 136void pc_pci_device_init(PCIBus *pci_bus);
8e78eb28 137
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138typedef void (*cpu_set_smm_t)(int smm, void *arg);
139void cpu_smm_register(cpu_set_smm_t callback, void *arg);
140
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141/* acpi.c */
142extern int acpi_enabled;
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143extern char *acpi_tables;
144extern size_t acpi_tables_len;
145
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146void acpi_bios_init(void);
147int acpi_table_add(const char *table_desc);
148
149/* acpi_piix.c */
53b67b30 150
cf7a2fe2 151i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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152 qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
153 int kvm_enabled);
87ecb68b 154void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
87ecb68b 155
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156/* hpet.c */
157extern int no_hpet;
158
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159/* pcspk.c */
160void pcspk_init(PITState *);
22d83b14 161int pcspk_audio_init(qemu_irq *pic);
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162
163/* piix_pci.c */
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164struct PCII440FXState;
165typedef struct PCII440FXState PCII440FXState;
166
97679527 167PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
0a3bacf3 168void i440fx_init_memory_mappings(PCII440FXState *d);
87ecb68b 169
823e675a 170/* piix4.c */
b1d8e52e 171extern PCIDevice *piix4_dev;
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172int piix4_init(PCIBus *bus, int devfn);
173
174/* vga.c */
cb5a7aa8 175enum vga_retrace_method {
176 VGA_RETRACE_DUMB,
177 VGA_RETRACE_PRECISE
178};
179
180extern enum vga_retrace_method vga_retrace_method;
87ecb68b 181
fbe1b595 182int isa_vga_init(void);
78895427 183int pci_vga_init(PCIBus *bus);
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184int isa_vga_mm_init(target_phys_addr_t vram_base,
185 target_phys_addr_t ctrl_base, int it_shift);
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186
187/* cirrus_vga.c */
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188void pci_cirrus_vga_init(PCIBus *bus);
189void isa_cirrus_vga_init(void);
87ecb68b 190
87ecb68b 191/* ne2000.c */
cd1b8a8b 192static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
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193{
194 ISADevice *dev;
87ecb68b 195
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196 qemu_check_nic_model(nd, "ne2k_isa");
197
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198 dev = isa_try_create("ne2k_isa");
199 if (!dev) {
200 return false;
201 }
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202 qdev_prop_set_uint32(&dev->qdev, "iobase", base);
203 qdev_prop_set_uint32(&dev->qdev, "irq", irq);
204 qdev_set_nic_properties(&dev->qdev, nd);
205 qdev_init_nofail(&dev->qdev);
cd1b8a8b 206 return true;
60a14ad3 207}
87ecb68b 208
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209/* e820 types */
210#define E820_RAM 1
211#define E820_RESERVED 2
212#define E820_ACPI 3
213#define E820_NVS 4
214#define E820_UNUSABLE 5
215
216int e820_add_entry(uint64_t, uint64_t, uint32_t);
217
87ecb68b 218#endif