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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c759b24f MT |
24 | #include "hw/hw.h" |
25 | #include "hw/pci/pci.h" | |
26 | #include "hw/pci/pci_bridge.h" | |
06aac7bd | 27 | #include "hw/pci/pci_bus.h" |
83c9089e | 28 | #include "monitor/monitor.h" |
1422e32d | 29 | #include "net/net.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
c759b24f | 31 | #include "hw/loader.h" |
1de7afc9 | 32 | #include "qemu/range.h" |
79627472 | 33 | #include "qmp-commands.h" |
c759b24f MT |
34 | #include "hw/pci/msi.h" |
35 | #include "hw/pci/msix.h" | |
022c62cb | 36 | #include "exec/address-spaces.h" |
69b91039 FB |
37 | |
38 | //#define DEBUG_PCI | |
d8d2e079 | 39 | #ifdef DEBUG_PCI |
2e49d64a | 40 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
41 | #else |
42 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
43 | #endif | |
69b91039 | 44 | |
10c4c98a | 45 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 46 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 47 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
9bb33586 | 48 | static int pcibus_reset(BusState *qbus); |
10c4c98a | 49 | |
3cb75a7c PB |
50 | static Property pci_props[] = { |
51 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), | |
52 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), | |
53 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), | |
54 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, | |
55 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
56 | DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, | |
57 | QEMU_PCI_CAP_SERR_BITNR, true), | |
58 | DEFINE_PROP_END_OF_LIST() | |
59 | }; | |
60 | ||
0d936928 AL |
61 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
62 | { | |
63 | BusClass *k = BUS_CLASS(klass); | |
64 | ||
65 | k->print_dev = pcibus_dev_print; | |
66 | k->get_dev_path = pcibus_get_dev_path; | |
67 | k->get_fw_dev_path = pcibus_get_fw_dev_path; | |
68 | k->reset = pcibus_reset; | |
69 | } | |
70 | ||
71 | static const TypeInfo pci_bus_info = { | |
72 | .name = TYPE_PCI_BUS, | |
73 | .parent = TYPE_BUS, | |
74 | .instance_size = sizeof(PCIBus), | |
75 | .class_init = pci_bus_class_init, | |
30468f78 | 76 | }; |
69b91039 | 77 | |
d662210a | 78 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
1941d19c | 79 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 80 | static void pci_set_irq(void *opaque, int irq_num, int level); |
ab85ceb1 | 81 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
230741dc | 82 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 83 | |
d350d97d AL |
84 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
85 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
86 | |
87 | struct PCIHostBus { | |
88 | int domain; | |
89 | struct PCIBus *bus; | |
90 | QLIST_ENTRY(PCIHostBus) next; | |
91 | }; | |
92 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 93 | |
2d1e9f96 JQ |
94 | static const VMStateDescription vmstate_pcibus = { |
95 | .name = "PCIBUS", | |
96 | .version_id = 1, | |
97 | .minimum_version_id = 1, | |
98 | .minimum_version_id_old = 1, | |
99 | .fields = (VMStateField []) { | |
100 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 101 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 102 | VMSTATE_END_OF_LIST() |
52fc1d83 | 103 | } |
2d1e9f96 | 104 | }; |
b3b11697 | 105 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 106 | { |
b3b11697 IY |
107 | uint8_t type; |
108 | ||
109 | if (reg != PCI_ROM_SLOT) | |
110 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
111 | ||
112 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
113 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
114 | } |
115 | ||
d036bb21 MT |
116 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
117 | { | |
118 | return (d->irq_state >> irq_num) & 0x1; | |
119 | } | |
120 | ||
121 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
122 | { | |
123 | d->irq_state &= ~(0x1 << irq_num); | |
124 | d->irq_state |= level << irq_num; | |
125 | } | |
126 | ||
127 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
128 | { | |
129 | PCIBus *bus; | |
130 | for (;;) { | |
131 | bus = pci_dev->bus; | |
132 | irq_num = bus->map_irq(pci_dev, irq_num); | |
133 | if (bus->set_irq) | |
134 | break; | |
135 | pci_dev = bus->parent_dev; | |
136 | } | |
137 | bus->irq_count[irq_num] += change; | |
138 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
139 | } | |
140 | ||
9ddf8437 IY |
141 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
142 | { | |
143 | assert(irq_num >= 0); | |
144 | assert(irq_num < bus->nirq); | |
145 | return !!bus->irq_count[irq_num]; | |
146 | } | |
147 | ||
f9bf77dd MT |
148 | /* Update interrupt status bit in config space on interrupt |
149 | * state change. */ | |
150 | static void pci_update_irq_status(PCIDevice *dev) | |
151 | { | |
152 | if (dev->irq_state) { | |
153 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
154 | } else { | |
155 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
156 | } | |
157 | } | |
158 | ||
4c92325b IY |
159 | void pci_device_deassert_intx(PCIDevice *dev) |
160 | { | |
161 | int i; | |
162 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
163 | qemu_set_irq(dev->irq[i], 0); | |
164 | } | |
165 | } | |
166 | ||
0ead87c8 IY |
167 | /* |
168 | * This function is called on #RST and FLR. | |
169 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
170 | */ | |
171 | void pci_device_reset(PCIDevice *dev) | |
5330de09 | 172 | { |
c0b1905b | 173 | int r; |
6fc4925b AL |
174 | |
175 | qdev_reset_all(&dev->qdev); | |
c0b1905b | 176 | |
d036bb21 | 177 | dev->irq_state = 0; |
f9bf77dd | 178 | pci_update_irq_status(dev); |
4c92325b | 179 | pci_device_deassert_intx(dev); |
ebabb67a | 180 | /* Clear all writable bits */ |
99443c21 | 181 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
182 | pci_get_word(dev->wmask + PCI_COMMAND) | |
183 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
184 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
185 | pci_get_word(dev->wmask + PCI_STATUS) | | |
186 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
c0b1905b MT |
187 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
188 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
189 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
190 | PCIIORegion *region = &dev->io_regions[r]; |
191 | if (!region->size) { | |
c0b1905b MT |
192 | continue; |
193 | } | |
71ebd6dc IY |
194 | |
195 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
196 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
197 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
198 | } else { | |
199 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
200 | } | |
c0b1905b MT |
201 | } |
202 | pci_update_mappings(dev); | |
cbd2d434 JK |
203 | |
204 | msi_reset(dev); | |
205 | msix_reset(dev); | |
5330de09 MT |
206 | } |
207 | ||
9bb33586 IY |
208 | /* |
209 | * Trigger pci bus reset under a given bus. | |
210 | * To be called on RST# assert. | |
211 | */ | |
212 | void pci_bus_reset(PCIBus *bus) | |
6eaa6847 | 213 | { |
6eaa6847 GN |
214 | int i; |
215 | ||
216 | for (i = 0; i < bus->nirq; i++) { | |
217 | bus->irq_count[i] = 0; | |
218 | } | |
5330de09 MT |
219 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
220 | if (bus->devices[i]) { | |
221 | pci_device_reset(bus->devices[i]); | |
222 | } | |
6eaa6847 GN |
223 | } |
224 | } | |
225 | ||
9bb33586 IY |
226 | static int pcibus_reset(BusState *qbus) |
227 | { | |
228 | pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); | |
229 | ||
230 | /* topology traverse is done by pci_bus_reset(). | |
231 | Tell qbus/qdev walker not to traverse the tree */ | |
232 | return 1; | |
233 | } | |
234 | ||
e822a52a IY |
235 | static void pci_host_bus_register(int domain, PCIBus *bus) |
236 | { | |
237 | struct PCIHostBus *host; | |
7267c094 | 238 | host = g_malloc0(sizeof(*host)); |
e822a52a IY |
239 | host->domain = domain; |
240 | host->bus = bus; | |
241 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
242 | } | |
243 | ||
c469e1dd | 244 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
245 | { |
246 | struct PCIHostBus *host; | |
247 | ||
248 | QLIST_FOREACH(host, &host_buses, next) { | |
249 | if (host->domain == domain) { | |
250 | return host->bus; | |
251 | } | |
252 | } | |
253 | ||
254 | return NULL; | |
255 | } | |
256 | ||
e075e788 IY |
257 | int pci_find_domain(const PCIBus *bus) |
258 | { | |
259 | PCIDevice *d; | |
260 | struct PCIHostBus *host; | |
261 | ||
262 | /* obtain root bus */ | |
263 | while ((d = bus->parent_dev) != NULL) { | |
264 | bus = d->bus; | |
265 | } | |
266 | ||
267 | QLIST_FOREACH(host, &host_buses, next) { | |
268 | if (host->bus == bus) { | |
269 | return host->domain; | |
270 | } | |
271 | } | |
272 | ||
273 | abort(); /* should not be reached */ | |
274 | return -1; | |
275 | } | |
276 | ||
4fec6404 | 277 | static void pci_bus_init(PCIBus *bus, DeviceState *parent, |
1e39101c | 278 | const char *name, |
aee97b84 AK |
279 | MemoryRegion *address_space_mem, |
280 | MemoryRegion *address_space_io, | |
1e39101c | 281 | uint8_t devfn_min) |
30468f78 | 282 | { |
6fa84913 | 283 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 284 | bus->devfn_min = devfn_min; |
5968eca3 AK |
285 | bus->address_space_mem = address_space_mem; |
286 | bus->address_space_io = address_space_io; | |
e822a52a IY |
287 | |
288 | /* host bridge */ | |
289 | QLIST_INIT(&bus->child); | |
290 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
291 | ||
0be71e32 | 292 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
21eea4b3 GH |
293 | } |
294 | ||
4fec6404 PB |
295 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
296 | const char *name, | |
297 | MemoryRegion *address_space_mem, | |
298 | MemoryRegion *address_space_io, | |
299 | uint8_t devfn_min) | |
300 | { | |
301 | qbus_create_inplace(bus, TYPE_PCI_BUS, parent, name); | |
302 | pci_bus_init(bus, parent, name, address_space_mem, | |
303 | address_space_io, devfn_min); | |
304 | } | |
305 | ||
1e39101c | 306 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
307 | MemoryRegion *address_space_mem, |
308 | MemoryRegion *address_space_io, | |
309 | uint8_t devfn_min) | |
21eea4b3 GH |
310 | { |
311 | PCIBus *bus; | |
312 | ||
4fec6404 PB |
313 | bus = PCI_BUS(qbus_create(TYPE_PCI_BUS, parent, name)); |
314 | pci_bus_init(bus, parent, name, address_space_mem, | |
315 | address_space_io, devfn_min); | |
21eea4b3 GH |
316 | return bus; |
317 | } | |
318 | ||
319 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
320 | void *irq_opaque, int nirq) | |
321 | { | |
322 | bus->set_irq = set_irq; | |
323 | bus->map_irq = map_irq; | |
324 | bus->irq_opaque = irq_opaque; | |
325 | bus->nirq = nirq; | |
7267c094 | 326 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
21eea4b3 GH |
327 | } |
328 | ||
87c30546 | 329 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
330 | { |
331 | bus->qbus.allow_hotplug = 1; | |
332 | bus->hotplug = hotplug; | |
87c30546 | 333 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
334 | } |
335 | ||
21eea4b3 GH |
336 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
337 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 338 | void *irq_opaque, |
aee97b84 AK |
339 | MemoryRegion *address_space_mem, |
340 | MemoryRegion *address_space_io, | |
1e39101c | 341 | uint8_t devfn_min, int nirq) |
21eea4b3 GH |
342 | { |
343 | PCIBus *bus; | |
344 | ||
aee97b84 AK |
345 | bus = pci_bus_new(parent, name, address_space_mem, |
346 | address_space_io, devfn_min); | |
21eea4b3 | 347 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
30468f78 FB |
348 | return bus; |
349 | } | |
69b91039 | 350 | |
502a5395 PB |
351 | int pci_bus_num(PCIBus *s) |
352 | { | |
e94ff650 IY |
353 | if (!s->parent_dev) |
354 | return 0; /* pci host bridge */ | |
355 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
356 | } |
357 | ||
73534f2f | 358 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 359 | { |
73534f2f | 360 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 361 | uint8_t *config; |
52fc1d83 AZ |
362 | int i; |
363 | ||
a9f49946 | 364 | assert(size == pci_config_size(s)); |
7267c094 | 365 | config = g_malloc(size); |
a9f49946 IY |
366 | |
367 | qemu_get_buffer(f, config, size); | |
368 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
369 | if ((config[i] ^ s->config[i]) & |
370 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
7267c094 | 371 | g_free(config); |
bd4b65ee | 372 | return -EINVAL; |
a9f49946 IY |
373 | } |
374 | } | |
375 | memcpy(s->config, config, size); | |
bd4b65ee | 376 | |
1941d19c | 377 | pci_update_mappings(s); |
52fc1d83 | 378 | |
4ea375bf GH |
379 | memory_region_set_enabled(&s->bus_master_enable_region, |
380 | pci_get_word(s->config + PCI_COMMAND) | |
381 | & PCI_COMMAND_MASTER); | |
382 | ||
7267c094 | 383 | g_free(config); |
30ca2aab FB |
384 | return 0; |
385 | } | |
386 | ||
73534f2f | 387 | /* just put buffer */ |
84e2e3eb | 388 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 389 | { |
dbe73d7f | 390 | const uint8_t **v = pv; |
a9f49946 | 391 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 392 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
393 | } |
394 | ||
395 | static VMStateInfo vmstate_info_pci_config = { | |
396 | .name = "pci config", | |
397 | .get = get_pci_config_device, | |
398 | .put = put_pci_config_device, | |
399 | }; | |
400 | ||
d036bb21 MT |
401 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
402 | { | |
c3f8f611 | 403 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
404 | uint32_t irq_state[PCI_NUM_PINS]; |
405 | int i; | |
406 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
407 | irq_state[i] = qemu_get_be32(f); | |
408 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
409 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
410 | irq_state[i]); | |
411 | return -EINVAL; | |
412 | } | |
413 | } | |
414 | ||
415 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
416 | pci_set_irq_state(s, i, irq_state[i]); | |
417 | } | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
423 | { | |
424 | int i; | |
c3f8f611 | 425 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
426 | |
427 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
428 | qemu_put_be32(f, pci_irq_state(s, i)); | |
429 | } | |
430 | } | |
431 | ||
432 | static VMStateInfo vmstate_info_pci_irq_state = { | |
433 | .name = "pci irq state", | |
434 | .get = get_pci_irq_state, | |
435 | .put = put_pci_irq_state, | |
436 | }; | |
437 | ||
73534f2f JQ |
438 | const VMStateDescription vmstate_pci_device = { |
439 | .name = "PCIDevice", | |
440 | .version_id = 2, | |
441 | .minimum_version_id = 1, | |
442 | .minimum_version_id_old = 1, | |
443 | .fields = (VMStateField []) { | |
444 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
445 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
446 | vmstate_info_pci_config, | |
447 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
448 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
449 | vmstate_info_pci_irq_state, | |
450 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
451 | VMSTATE_END_OF_LIST() |
452 | } | |
453 | }; | |
454 | ||
455 | const VMStateDescription vmstate_pcie_device = { | |
1de53459 | 456 | .name = "PCIEDevice", |
a9f49946 IY |
457 | .version_id = 2, |
458 | .minimum_version_id = 1, | |
459 | .minimum_version_id_old = 1, | |
460 | .fields = (VMStateField []) { | |
461 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
462 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
463 | vmstate_info_pci_config, | |
464 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
465 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
466 | vmstate_info_pci_irq_state, | |
467 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
468 | VMSTATE_END_OF_LIST() |
469 | } | |
470 | }; | |
471 | ||
a9f49946 IY |
472 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
473 | { | |
474 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
475 | } | |
476 | ||
73534f2f JQ |
477 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
478 | { | |
f9bf77dd MT |
479 | /* Clear interrupt status bit: it is implicit |
480 | * in irq_state which we are saving. | |
481 | * This makes us compatible with old devices | |
482 | * which never set or clear this bit. */ | |
483 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 484 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
485 | /* Restore the interrupt status bit. */ |
486 | pci_update_irq_status(s); | |
73534f2f JQ |
487 | } |
488 | ||
489 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
490 | { | |
f9bf77dd MT |
491 | int ret; |
492 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
493 | /* Restore the interrupt status bit. */ | |
494 | pci_update_irq_status(s); | |
495 | return ret; | |
73534f2f JQ |
496 | } |
497 | ||
5e434f4e | 498 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 499 | { |
5e434f4e IY |
500 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
501 | pci_default_sub_vendor_id); | |
502 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
503 | pci_default_sub_device_id); | |
d350d97d AL |
504 | } |
505 | ||
880345c4 | 506 | /* |
43c945f1 IY |
507 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
508 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 509 | */ |
94a09e2c | 510 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
43c945f1 | 511 | unsigned int *slotp, unsigned int *funcp) |
880345c4 AL |
512 | { |
513 | const char *p; | |
514 | char *e; | |
515 | unsigned long val; | |
516 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
517 | unsigned int slot = 0; |
518 | unsigned int func = 0; | |
880345c4 AL |
519 | |
520 | p = addr; | |
521 | val = strtoul(p, &e, 16); | |
522 | if (e == p) | |
523 | return -1; | |
524 | if (*e == ':') { | |
525 | bus = val; | |
526 | p = e + 1; | |
527 | val = strtoul(p, &e, 16); | |
528 | if (e == p) | |
529 | return -1; | |
530 | if (*e == ':') { | |
531 | dom = bus; | |
532 | bus = val; | |
533 | p = e + 1; | |
534 | val = strtoul(p, &e, 16); | |
535 | if (e == p) | |
536 | return -1; | |
537 | } | |
538 | } | |
539 | ||
880345c4 AL |
540 | slot = val; |
541 | ||
43c945f1 IY |
542 | if (funcp != NULL) { |
543 | if (*e != '.') | |
544 | return -1; | |
545 | ||
546 | p = e + 1; | |
547 | val = strtoul(p, &e, 16); | |
548 | if (e == p) | |
549 | return -1; | |
550 | ||
551 | func = val; | |
552 | } | |
553 | ||
554 | /* if funcp == NULL func is 0 */ | |
555 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
556 | return -1; | |
557 | ||
880345c4 AL |
558 | if (*e) |
559 | return -1; | |
560 | ||
880345c4 AL |
561 | *domp = dom; |
562 | *busp = bus; | |
563 | *slotp = slot; | |
43c945f1 IY |
564 | if (funcp != NULL) |
565 | *funcp = func; | |
880345c4 AL |
566 | return 0; |
567 | } | |
568 | ||
e9283f8b JK |
569 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
570 | unsigned *slotp) | |
880345c4 | 571 | { |
e9283f8b JK |
572 | /* strip legacy tag */ |
573 | if (!strncmp(addr, "pci_addr=", 9)) { | |
574 | addr += 9; | |
575 | } | |
43c945f1 | 576 | if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { |
e9283f8b | 577 | monitor_printf(mon, "Invalid pci address\n"); |
880345c4 | 578 | return -1; |
e9283f8b JK |
579 | } |
580 | return 0; | |
880345c4 AL |
581 | } |
582 | ||
49bd1458 | 583 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
584 | { |
585 | int dom, bus; | |
586 | unsigned slot; | |
587 | ||
588 | if (!devaddr) { | |
589 | *devfnp = -1; | |
d662210a | 590 | return pci_find_bus_nr(pci_find_root_bus(0), 0); |
5607c388 MA |
591 | } |
592 | ||
43c945f1 | 593 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
594 | return NULL; |
595 | } | |
596 | ||
6ff534b6 | 597 | *devfnp = PCI_DEVFN(slot, 0); |
d662210a | 598 | return pci_find_bus_nr(pci_find_root_bus(dom), bus); |
5607c388 MA |
599 | } |
600 | ||
bd4b65ee MT |
601 | static void pci_init_cmask(PCIDevice *dev) |
602 | { | |
603 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
604 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
605 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
606 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
607 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
608 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
609 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
610 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
611 | } | |
612 | ||
b7ee1603 MT |
613 | static void pci_init_wmask(PCIDevice *dev) |
614 | { | |
a9f49946 IY |
615 | int config_size = pci_config_size(dev); |
616 | ||
b7ee1603 MT |
617 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
618 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 619 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
620 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
621 | PCI_COMMAND_INTX_DISABLE); | |
b1aeb926 IY |
622 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
623 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); | |
624 | } | |
3e21ffc9 IY |
625 | |
626 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
627 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
628 | } |
629 | ||
89d437df IY |
630 | static void pci_init_w1cmask(PCIDevice *dev) |
631 | { | |
632 | /* | |
f6bdfcc9 | 633 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
634 | * long as their value is hardwired to 0. |
635 | */ | |
636 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
637 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
638 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
639 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
640 | } | |
641 | ||
d5f27e88 | 642 | static void pci_init_mask_bridge(PCIDevice *d) |
fb231628 IY |
643 | { |
644 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
645 | PCI_SEC_LETENCY_TIMER */ | |
646 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
647 | ||
648 | /* base and limit */ | |
649 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
650 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
651 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
652 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
653 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
654 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
655 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
656 | PCI_PREF_RANGE_MASK & 0xffff); | |
657 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
658 | PCI_PREF_RANGE_MASK & 0xffff); | |
659 | ||
660 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
661 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
662 | ||
d5f27e88 | 663 | /* Supported memory and i/o types */ |
68917102 MT |
664 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
665 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; | |
d5f27e88 MT |
666 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
667 | PCI_PREF_RANGE_TYPE_64); | |
668 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, | |
669 | PCI_PREF_RANGE_TYPE_64); | |
670 | ||
45eb768c MT |
671 | /* |
672 | * TODO: Bridges default to 10-bit VGA decoding but we currently only | |
673 | * implement 16-bit decoding (no alias support). | |
674 | */ | |
f6bdfcc9 MT |
675 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
676 | PCI_BRIDGE_CTL_PARITY | | |
677 | PCI_BRIDGE_CTL_SERR | | |
678 | PCI_BRIDGE_CTL_ISA | | |
679 | PCI_BRIDGE_CTL_VGA | | |
680 | PCI_BRIDGE_CTL_VGA_16BIT | | |
681 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
682 | PCI_BRIDGE_CTL_BUS_RESET | | |
683 | PCI_BRIDGE_CTL_FAST_BACK | | |
684 | PCI_BRIDGE_CTL_DISCARD | | |
685 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
686 | PCI_BRIDGE_CTL_DISCARD_SERR); |
687 | /* Below does not do anything as we never set this bit, put here for | |
688 | * completeness. */ | |
689 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
690 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
d5f27e88 | 691 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
15ab7a75 | 692 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
d5f27e88 MT |
693 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
694 | PCI_PREF_RANGE_TYPE_MASK); | |
15ab7a75 MT |
695 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
696 | PCI_PREF_RANGE_TYPE_MASK); | |
fb231628 IY |
697 | } |
698 | ||
6eab3de1 IY |
699 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
700 | { | |
701 | uint8_t slot = PCI_SLOT(dev->devfn); | |
702 | uint8_t func; | |
703 | ||
704 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
705 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
706 | } | |
707 | ||
708 | /* | |
b0cd712c | 709 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
710 | * - all functions must set the bit to 1. |
711 | * Example: Intel X53 | |
712 | * - function 0 must set the bit, but the rest function (> 0) | |
713 | * is allowed to leave the bit to 0. | |
714 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
715 | * | |
716 | * So OS (at least Linux) checks the bit of only function 0, | |
717 | * and doesn't see the bit of function > 0. | |
718 | * | |
719 | * The below check allows both interpretation. | |
720 | */ | |
721 | if (PCI_FUNC(dev->devfn)) { | |
722 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
723 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
724 | /* function 0 should set multifunction bit */ | |
725 | error_report("PCI: single function device can't be populated " | |
726 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
727 | return -1; | |
728 | } | |
729 | return 0; | |
730 | } | |
731 | ||
732 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
733 | return 0; | |
734 | } | |
735 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
736 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
737 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
738 | error_report("PCI: %x.0 indicates single function, " | |
739 | "but %x.%x is already populated.", | |
740 | slot, slot, func); | |
741 | return -1; | |
742 | } | |
743 | } | |
744 | return 0; | |
745 | } | |
746 | ||
a9f49946 IY |
747 | static void pci_config_alloc(PCIDevice *pci_dev) |
748 | { | |
749 | int config_size = pci_config_size(pci_dev); | |
750 | ||
7267c094 AL |
751 | pci_dev->config = g_malloc0(config_size); |
752 | pci_dev->cmask = g_malloc0(config_size); | |
753 | pci_dev->wmask = g_malloc0(config_size); | |
754 | pci_dev->w1cmask = g_malloc0(config_size); | |
755 | pci_dev->used = g_malloc0(config_size); | |
a9f49946 IY |
756 | } |
757 | ||
758 | static void pci_config_free(PCIDevice *pci_dev) | |
759 | { | |
7267c094 AL |
760 | g_free(pci_dev->config); |
761 | g_free(pci_dev->cmask); | |
762 | g_free(pci_dev->wmask); | |
763 | g_free(pci_dev->w1cmask); | |
764 | g_free(pci_dev->used); | |
a9f49946 IY |
765 | } |
766 | ||
69b91039 | 767 | /* -1 for devfn means auto assign */ |
6b1b92d3 | 768 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
40021f08 | 769 | const char *name, int devfn) |
69b91039 | 770 | { |
40021f08 AL |
771 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
772 | PCIConfigReadFunc *config_read = pc->config_read; | |
773 | PCIConfigWriteFunc *config_write = pc->config_write; | |
113f89df | 774 | |
69b91039 | 775 | if (devfn < 0) { |
b47b0706 | 776 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 777 | devfn += PCI_FUNC_MAX) { |
30468f78 | 778 | if (!bus->devices[devfn]) |
69b91039 FB |
779 | goto found; |
780 | } | |
3709c1b7 | 781 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 782 | return NULL; |
69b91039 | 783 | found: ; |
07b7d053 | 784 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
785 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
786 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 787 | return NULL; |
69b91039 | 788 | } |
30468f78 | 789 | pci_dev->bus = bus; |
5fa45de5 DG |
790 | if (bus->dma_context_fn) { |
791 | pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn); | |
817dcc53 AK |
792 | } else { |
793 | /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is | |
794 | * taken unconditionally */ | |
795 | /* FIXME: inherit memory region from bus creator */ | |
1c380f94 AK |
796 | memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master", |
797 | get_system_memory(), 0, | |
798 | memory_region_size(get_system_memory())); | |
799 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); | |
800 | address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region); | |
817dcc53 AK |
801 | pci_dev->dma = g_new(DMAContext, 1); |
802 | dma_context_init(pci_dev->dma, &pci_dev->bus_master_as, NULL, NULL, NULL); | |
5fa45de5 | 803 | } |
69b91039 FB |
804 | pci_dev->devfn = devfn; |
805 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 806 | pci_dev->irq_state = 0; |
a9f49946 | 807 | pci_config_alloc(pci_dev); |
fb231628 | 808 | |
40021f08 AL |
809 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
810 | pci_config_set_device_id(pci_dev->config, pc->device_id); | |
811 | pci_config_set_revision(pci_dev->config, pc->revision); | |
812 | pci_config_set_class(pci_dev->config, pc->class_id); | |
113f89df | 813 | |
40021f08 AL |
814 | if (!pc->is_bridge) { |
815 | if (pc->subsystem_vendor_id || pc->subsystem_id) { | |
113f89df | 816 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
40021f08 | 817 | pc->subsystem_vendor_id); |
113f89df | 818 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
40021f08 | 819 | pc->subsystem_id); |
113f89df IY |
820 | } else { |
821 | pci_set_default_subsystem_id(pci_dev); | |
822 | } | |
823 | } else { | |
824 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
40021f08 AL |
825 | assert(!pc->subsystem_vendor_id); |
826 | assert(!pc->subsystem_id); | |
fb231628 | 827 | } |
bd4b65ee | 828 | pci_init_cmask(pci_dev); |
b7ee1603 | 829 | pci_init_wmask(pci_dev); |
89d437df | 830 | pci_init_w1cmask(pci_dev); |
40021f08 | 831 | if (pc->is_bridge) { |
d5f27e88 | 832 | pci_init_mask_bridge(pci_dev); |
fb231628 | 833 | } |
6eab3de1 IY |
834 | if (pci_init_multifunction(bus, pci_dev)) { |
835 | pci_config_free(pci_dev); | |
836 | return NULL; | |
837 | } | |
0ac32c83 FB |
838 | |
839 | if (!config_read) | |
840 | config_read = pci_default_read_config; | |
841 | if (!config_write) | |
842 | config_write = pci_default_write_config; | |
69b91039 FB |
843 | pci_dev->config_read = config_read; |
844 | pci_dev->config_write = config_write; | |
30468f78 | 845 | bus->devices[devfn] = pci_dev; |
e369cad7 | 846 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 847 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
848 | return pci_dev; |
849 | } | |
850 | ||
925fe64a AW |
851 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
852 | { | |
853 | qemu_free_irqs(pci_dev->irq); | |
854 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
855 | pci_config_free(pci_dev); | |
817dcc53 AK |
856 | |
857 | if (!pci_dev->bus->dma_context_fn) { | |
858 | address_space_destroy(&pci_dev->bus_master_as); | |
1c380f94 | 859 | memory_region_destroy(&pci_dev->bus_master_enable_region); |
817dcc53 AK |
860 | g_free(pci_dev->dma); |
861 | pci_dev->dma = NULL; | |
862 | } | |
925fe64a AW |
863 | } |
864 | ||
5851e08c AL |
865 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
866 | { | |
867 | PCIIORegion *r; | |
868 | int i; | |
869 | ||
870 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
871 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 872 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 873 | continue; |
03952339 | 874 | memory_region_del_subregion(r->address_space, r->memory); |
5851e08c | 875 | } |
e01fd687 AW |
876 | |
877 | pci_unregister_vga(pci_dev); | |
5851e08c AL |
878 | } |
879 | ||
a36a344d | 880 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 881 | { |
40021f08 AL |
882 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
883 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); | |
5851e08c AL |
884 | |
885 | pci_unregister_io_regions(pci_dev); | |
230741dc | 886 | pci_del_option_rom(pci_dev); |
7cf1b0fd | 887 | |
f90c2bcd AW |
888 | if (pc->exit) { |
889 | pc->exit(pci_dev); | |
890 | } | |
5851e08c | 891 | |
925fe64a | 892 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
893 | return 0; |
894 | } | |
895 | ||
e824b2cc AK |
896 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
897 | uint8_t type, MemoryRegion *memory) | |
69b91039 FB |
898 | { |
899 | PCIIORegion *r; | |
d7ce493a | 900 | uint32_t addr; |
5a9ff381 | 901 | uint64_t wmask; |
cfc0be25 | 902 | pcibus_t size = memory_region_size(memory); |
a4c20c6a | 903 | |
2bbb9c2f IY |
904 | assert(region_num >= 0); |
905 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
906 | if (size & (size-1)) { |
907 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 908 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
909 | exit(1); |
910 | } | |
911 | ||
69b91039 | 912 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 913 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
914 | r->size = size; |
915 | r->type = type; | |
79ff8cb0 | 916 | r->memory = NULL; |
b7ee1603 MT |
917 | |
918 | wmask = ~(size - 1); | |
b3b11697 | 919 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 920 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 921 | /* ROM enable bit is writable */ |
5330de09 | 922 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 923 | } |
b0ff8eb2 | 924 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
925 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
926 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
927 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
928 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
929 | } else { | |
930 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
931 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
932 | } | |
79ff8cb0 | 933 | pci_dev->io_regions[region_num].memory = memory; |
5968eca3 | 934 | pci_dev->io_regions[region_num].address_space |
cfc0be25 | 935 | = type & PCI_BASE_ADDRESS_SPACE_IO |
5968eca3 AK |
936 | ? pci_dev->bus->address_space_io |
937 | : pci_dev->bus->address_space_mem; | |
79ff8cb0 AK |
938 | } |
939 | ||
e01fd687 AW |
940 | static void pci_update_vga(PCIDevice *pci_dev) |
941 | { | |
942 | uint16_t cmd; | |
943 | ||
944 | if (!pci_dev->has_vga) { | |
945 | return; | |
946 | } | |
947 | ||
948 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
949 | ||
950 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], | |
951 | cmd & PCI_COMMAND_MEMORY); | |
952 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], | |
953 | cmd & PCI_COMMAND_IO); | |
954 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], | |
955 | cmd & PCI_COMMAND_IO); | |
956 | } | |
957 | ||
958 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, | |
959 | MemoryRegion *io_lo, MemoryRegion *io_hi) | |
960 | { | |
961 | assert(!pci_dev->has_vga); | |
962 | ||
963 | assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); | |
964 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; | |
965 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, | |
966 | QEMU_PCI_VGA_MEM_BASE, mem, 1); | |
967 | ||
968 | assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); | |
969 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; | |
970 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
971 | QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); | |
972 | ||
973 | assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); | |
974 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; | |
975 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
976 | QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); | |
977 | pci_dev->has_vga = true; | |
978 | ||
979 | pci_update_vga(pci_dev); | |
980 | } | |
981 | ||
982 | void pci_unregister_vga(PCIDevice *pci_dev) | |
983 | { | |
984 | if (!pci_dev->has_vga) { | |
985 | return; | |
986 | } | |
987 | ||
988 | memory_region_del_subregion(pci_dev->bus->address_space_mem, | |
989 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); | |
990 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
991 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); | |
992 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
993 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); | |
994 | pci_dev->has_vga = false; | |
995 | } | |
996 | ||
16a96f28 AK |
997 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
998 | { | |
999 | return pci_dev->io_regions[region_num].addr; | |
1000 | } | |
1001 | ||
876a350d MT |
1002 | static pcibus_t pci_bar_address(PCIDevice *d, |
1003 | int reg, uint8_t type, pcibus_t size) | |
1004 | { | |
1005 | pcibus_t new_addr, last_addr; | |
1006 | int bar = pci_bar(d, reg); | |
1007 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
1008 | ||
1009 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1010 | if (!(cmd & PCI_COMMAND_IO)) { | |
1011 | return PCI_BAR_UNMAPPED; | |
1012 | } | |
1013 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
1014 | last_addr = new_addr + size - 1; | |
1015 | /* NOTE: we have only 64K ioports on PC */ | |
1016 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
1017 | return PCI_BAR_UNMAPPED; | |
1018 | } | |
1019 | return new_addr; | |
1020 | } | |
1021 | ||
1022 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
1023 | return PCI_BAR_UNMAPPED; | |
1024 | } | |
1025 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1026 | new_addr = pci_get_quad(d->config + bar); | |
1027 | } else { | |
1028 | new_addr = pci_get_long(d->config + bar); | |
1029 | } | |
1030 | /* the ROM slot has a specific enable bit */ | |
1031 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
1032 | return PCI_BAR_UNMAPPED; | |
1033 | } | |
1034 | new_addr &= ~(size - 1); | |
1035 | last_addr = new_addr + size - 1; | |
1036 | /* NOTE: we do not support wrapping */ | |
1037 | /* XXX: as we cannot support really dynamic | |
1038 | mappings, we handle specific values as invalid | |
1039 | mappings. */ | |
1040 | if (last_addr <= new_addr || new_addr == 0 || | |
1041 | last_addr == PCI_BAR_UNMAPPED) { | |
1042 | return PCI_BAR_UNMAPPED; | |
1043 | } | |
1044 | ||
1045 | /* Now pcibus_t is 64bit. | |
1046 | * Check if 32 bit BAR wraps around explicitly. | |
1047 | * Without this, PC ide doesn't work well. | |
1048 | * TODO: remove this work around. | |
1049 | */ | |
1050 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
1051 | return PCI_BAR_UNMAPPED; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * OS is allowed to set BAR beyond its addressable | |
1056 | * bits. For example, 32 bit OS can set 64bit bar | |
1057 | * to >4G. Check it. TODO: we might need to support | |
1058 | * it in the future for e.g. PAE. | |
1059 | */ | |
a8170e5e | 1060 | if (last_addr >= HWADDR_MAX) { |
876a350d MT |
1061 | return PCI_BAR_UNMAPPED; |
1062 | } | |
1063 | ||
1064 | return new_addr; | |
1065 | } | |
1066 | ||
0ac32c83 FB |
1067 | static void pci_update_mappings(PCIDevice *d) |
1068 | { | |
1069 | PCIIORegion *r; | |
876a350d | 1070 | int i; |
7df32ca0 | 1071 | pcibus_t new_addr; |
3b46e624 | 1072 | |
8a8696a3 | 1073 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1074 | r = &d->io_regions[i]; |
a9688570 IY |
1075 | |
1076 | /* this region isn't registered */ | |
ec503442 | 1077 | if (!r->size) |
a9688570 IY |
1078 | continue; |
1079 | ||
876a350d | 1080 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 IY |
1081 | |
1082 | /* This bar isn't changed */ | |
7df32ca0 | 1083 | if (new_addr == r->addr) |
a9688570 IY |
1084 | continue; |
1085 | ||
1086 | /* now do the real mapping */ | |
1087 | if (r->addr != PCI_BAR_UNMAPPED) { | |
03952339 | 1088 | memory_region_del_subregion(r->address_space, r->memory); |
0ac32c83 | 1089 | } |
a9688570 IY |
1090 | r->addr = new_addr; |
1091 | if (r->addr != PCI_BAR_UNMAPPED) { | |
8b881e77 AK |
1092 | memory_region_add_subregion_overlap(r->address_space, |
1093 | r->addr, r->memory, 1); | |
a9688570 | 1094 | } |
0ac32c83 | 1095 | } |
e01fd687 AW |
1096 | |
1097 | pci_update_vga(d); | |
0ac32c83 FB |
1098 | } |
1099 | ||
a7b15a5c MT |
1100 | static inline int pci_irq_disabled(PCIDevice *d) |
1101 | { | |
1102 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1103 | } | |
1104 | ||
1105 | /* Called after interrupt disabled field update in config space, | |
1106 | * assert/deassert interrupts if necessary. | |
1107 | * Gets original interrupt disable bit value (before update). */ | |
1108 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1109 | { | |
1110 | int i, disabled = pci_irq_disabled(d); | |
1111 | if (disabled == was_irq_disabled) | |
1112 | return; | |
1113 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1114 | int state = pci_irq_state(d, i); | |
1115 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1116 | } | |
1117 | } | |
1118 | ||
5fafdf24 | 1119 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1120 | uint32_t address, int len) |
69b91039 | 1121 | { |
5029fe12 | 1122 | uint32_t val = 0; |
42e4126b | 1123 | |
5029fe12 IY |
1124 | memcpy(&val, d->config + address, len); |
1125 | return le32_to_cpu(val); | |
0ac32c83 FB |
1126 | } |
1127 | ||
b7ee1603 | 1128 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 1129 | { |
a7b15a5c | 1130 | int i, was_irq_disabled = pci_irq_disabled(d); |
0ac32c83 | 1131 | |
42e4126b | 1132 | for (i = 0; i < l; val >>= 8, ++i) { |
91011d4f | 1133 | uint8_t wmask = d->wmask[addr + i]; |
92ba5f51 IY |
1134 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1135 | assert(!(wmask & w1cmask)); | |
91011d4f | 1136 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1137 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1138 | } |
260c0cd3 | 1139 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1140 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1141 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1142 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1143 | pci_update_mappings(d); |
a7b15a5c | 1144 | |
1c380f94 | 1145 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
a7b15a5c | 1146 | pci_update_irq_disabled(d, was_irq_disabled); |
1c380f94 AK |
1147 | memory_region_set_enabled(&d->bus_master_enable_region, |
1148 | pci_get_word(d->config + PCI_COMMAND) | |
1149 | & PCI_COMMAND_MASTER); | |
1150 | } | |
95d65800 JK |
1151 | |
1152 | msi_write_config(d, addr, val, l); | |
1153 | msix_write_config(d, addr, val, l); | |
69b91039 FB |
1154 | } |
1155 | ||
502a5395 PB |
1156 | /***********************************************************/ |
1157 | /* generic PCI irq support */ | |
30468f78 | 1158 | |
502a5395 | 1159 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1160 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1161 | { |
a60380a5 | 1162 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1163 | int change; |
3b46e624 | 1164 | |
d036bb21 | 1165 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1166 | if (!change) |
1167 | return; | |
d2b59317 | 1168 | |
d036bb21 | 1169 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1170 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1171 | if (pci_irq_disabled(pci_dev)) |
1172 | return; | |
d036bb21 | 1173 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1174 | } |
1175 | ||
3afa9bb4 MT |
1176 | /* Special hooks used by device assignment */ |
1177 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) | |
1178 | { | |
1179 | assert(!bus->parent_dev); | |
1180 | bus->route_intx_to_irq = route_intx_to_irq; | |
1181 | } | |
1182 | ||
1183 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) | |
1184 | { | |
1185 | PCIBus *bus; | |
1186 | ||
1187 | do { | |
1188 | bus = dev->bus; | |
1189 | pin = bus->map_irq(dev, pin); | |
1190 | dev = bus->parent_dev; | |
1191 | } while (dev); | |
05c0621e AW |
1192 | |
1193 | if (!bus->route_intx_to_irq) { | |
312fd5f2 | 1194 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", |
05c0621e AW |
1195 | object_get_typename(OBJECT(bus->qbus.parent))); |
1196 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; | |
1197 | } | |
1198 | ||
3afa9bb4 | 1199 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
0ae16251 JK |
1200 | } |
1201 | ||
d6e65d54 AW |
1202 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1203 | { | |
1204 | return old->mode != new->mode || old->irq != new->irq; | |
1205 | } | |
1206 | ||
0ae16251 JK |
1207 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1208 | { | |
1209 | PCIDevice *dev; | |
1210 | PCIBus *sec; | |
1211 | int i; | |
1212 | ||
1213 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1214 | dev = bus->devices[i]; | |
1215 | if (dev && dev->intx_routing_notifier) { | |
1216 | dev->intx_routing_notifier(dev); | |
1217 | } | |
e5368f0d AW |
1218 | } |
1219 | ||
1220 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1221 | pci_bus_fire_intx_routing_notifier(sec); | |
0ae16251 JK |
1222 | } |
1223 | } | |
1224 | ||
1225 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
1226 | PCIINTxRoutingNotifier notifier) | |
1227 | { | |
1228 | dev->intx_routing_notifier = notifier; | |
69b91039 FB |
1229 | } |
1230 | ||
91e56159 IY |
1231 | /* |
1232 | * PCI-to-PCI bridge specification | |
1233 | * 9.1: Interrupt routing. Table 9-1 | |
1234 | * | |
1235 | * the PCI Express Base Specification, Revision 2.1 | |
1236 | * 2.2.8.1: INTx interrutp signaling - Rules | |
1237 | * the Implementation Note | |
1238 | * Table 2-20 | |
1239 | */ | |
1240 | /* | |
1241 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD | |
1242 | * 0-origin unlike PCI interrupt pin register. | |
1243 | */ | |
1244 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) | |
1245 | { | |
1246 | return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; | |
1247 | } | |
1248 | ||
502a5395 PB |
1249 | /***********************************************************/ |
1250 | /* monitor info on PCI */ | |
0ac32c83 | 1251 | |
6650ee6d PB |
1252 | typedef struct { |
1253 | uint16_t class; | |
1254 | const char *desc; | |
5e0259e7 GN |
1255 | const char *fw_name; |
1256 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1257 | } pci_class_desc; |
1258 | ||
09bc878a | 1259 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1260 | { |
5e0259e7 GN |
1261 | { 0x0001, "VGA controller", "display"}, |
1262 | { 0x0100, "SCSI controller", "scsi"}, | |
1263 | { 0x0101, "IDE controller", "ide"}, | |
1264 | { 0x0102, "Floppy controller", "fdc"}, | |
1265 | { 0x0103, "IPI controller", "ipi"}, | |
1266 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1267 | { 0x0106, "SATA controller"}, |
1268 | { 0x0107, "SAS controller"}, | |
1269 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1270 | { 0x0200, "Ethernet controller", "ethernet"}, |
1271 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1272 | { 0x0202, "FDDI controller", "fddi"}, | |
1273 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1274 | { 0x0280, "Network controller"}, |
5e0259e7 | 1275 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1276 | { 0x0301, "XGA controller"}, |
1277 | { 0x0302, "3D controller"}, | |
1278 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1279 | { 0x0400, "Video controller", "video"}, |
1280 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1281 | { 0x0402, "Phone"}, |
602ef4d9 | 1282 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1283 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1284 | { 0x0500, "RAM controller", "memory"}, |
1285 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1286 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1287 | { 0x0600, "Host bridge", "host"}, |
1288 | { 0x0601, "ISA bridge", "isa"}, | |
1289 | { 0x0602, "EISA bridge", "eisa"}, | |
1290 | { 0x0603, "MC bridge", "mca"}, | |
1291 | { 0x0604, "PCI bridge", "pci"}, | |
1292 | { 0x0605, "PCMCIA bridge", "pcmcia"}, | |
1293 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1294 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1295 | { 0x0608, "RACEWAY bridge"}, |
1296 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1297 | { 0x0700, "Serial port", "serial"}, |
1298 | { 0x0701, "Parallel port", "parallel"}, | |
1299 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1300 | { 0x0801, "DMA controller", "dma-controller"}, | |
1301 | { 0x0802, "Timer", "timer"}, | |
1302 | { 0x0803, "RTC", "rtc"}, | |
1303 | { 0x0900, "Keyboard", "keyboard"}, | |
1304 | { 0x0901, "Pen", "pen"}, | |
1305 | { 0x0902, "Mouse", "mouse"}, | |
1306 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1307 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
1308 | { 0x0c00, "Fireware contorller", "fireware"}, | |
1309 | { 0x0c01, "Access bus controller", "access-bus"}, | |
1310 | { 0x0c02, "SSA controller", "ssa"}, | |
1311 | { 0x0c03, "USB controller", "usb"}, | |
1312 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
f7748569 | 1313 | { 0x0c05, "SMBus"}, |
6650ee6d PB |
1314 | { 0, NULL} |
1315 | }; | |
1316 | ||
163c8a59 | 1317 | static void pci_for_each_device_under_bus(PCIBus *bus, |
7aa8cbb9 AP |
1318 | void (*fn)(PCIBus *b, PCIDevice *d, |
1319 | void *opaque), | |
1320 | void *opaque) | |
30468f78 | 1321 | { |
163c8a59 LC |
1322 | PCIDevice *d; |
1323 | int devfn; | |
30468f78 | 1324 | |
163c8a59 LC |
1325 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1326 | d = bus->devices[devfn]; | |
1327 | if (d) { | |
7aa8cbb9 | 1328 | fn(bus, d, opaque); |
163c8a59 LC |
1329 | } |
1330 | } | |
1331 | } | |
1332 | ||
1333 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
7aa8cbb9 AP |
1334 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1335 | void *opaque) | |
163c8a59 | 1336 | { |
d662210a | 1337 | bus = pci_find_bus_nr(bus, bus_num); |
163c8a59 LC |
1338 | |
1339 | if (bus) { | |
7aa8cbb9 | 1340 | pci_for_each_device_under_bus(bus, fn, opaque); |
163c8a59 LC |
1341 | } |
1342 | } | |
1343 | ||
79627472 | 1344 | static const pci_class_desc *get_class_desc(int class) |
163c8a59 | 1345 | { |
79627472 | 1346 | const pci_class_desc *desc; |
163c8a59 | 1347 | |
79627472 LC |
1348 | desc = pci_class_descriptions; |
1349 | while (desc->desc && class != desc->class) { | |
1350 | desc++; | |
30468f78 | 1351 | } |
b4dccd8d | 1352 | |
79627472 LC |
1353 | return desc; |
1354 | } | |
14421258 | 1355 | |
79627472 | 1356 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
163c8a59 | 1357 | |
79627472 LC |
1358 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1359 | { | |
1360 | PciMemoryRegionList *head = NULL, *cur_item = NULL; | |
1361 | int i; | |
163c8a59 | 1362 | |
79627472 LC |
1363 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1364 | const PCIIORegion *r = &dev->io_regions[i]; | |
1365 | PciMemoryRegionList *region; | |
1366 | ||
1367 | if (!r->size) { | |
1368 | continue; | |
502a5395 | 1369 | } |
163c8a59 | 1370 | |
79627472 LC |
1371 | region = g_malloc0(sizeof(*region)); |
1372 | region->value = g_malloc0(sizeof(*region->value)); | |
163c8a59 | 1373 | |
79627472 LC |
1374 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1375 | region->value->type = g_strdup("io"); | |
1376 | } else { | |
1377 | region->value->type = g_strdup("memory"); | |
1378 | region->value->has_prefetch = true; | |
1379 | region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1380 | region->value->has_mem_type_64 = true; | |
1381 | region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
d5e4acf7 | 1382 | } |
163c8a59 | 1383 | |
79627472 LC |
1384 | region->value->bar = i; |
1385 | region->value->address = r->addr; | |
1386 | region->value->size = r->size; | |
163c8a59 | 1387 | |
79627472 LC |
1388 | /* XXX: waiting for the qapi to support GSList */ |
1389 | if (!cur_item) { | |
1390 | head = cur_item = region; | |
1391 | } else { | |
1392 | cur_item->next = region; | |
1393 | cur_item = region; | |
163c8a59 | 1394 | } |
80b3ada7 | 1395 | } |
384d8876 | 1396 | |
79627472 | 1397 | return head; |
163c8a59 LC |
1398 | } |
1399 | ||
79627472 LC |
1400 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1401 | int bus_num) | |
163c8a59 | 1402 | { |
79627472 | 1403 | PciBridgeInfo *info; |
163c8a59 | 1404 | |
79627472 | 1405 | info = g_malloc0(sizeof(*info)); |
163c8a59 | 1406 | |
79627472 LC |
1407 | info->bus.number = dev->config[PCI_PRIMARY_BUS]; |
1408 | info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; | |
1409 | info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
163c8a59 | 1410 | |
79627472 LC |
1411 | info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); |
1412 | info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
1413 | info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
163c8a59 | 1414 | |
79627472 LC |
1415 | info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); |
1416 | info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
1417 | info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
163c8a59 | 1418 | |
79627472 LC |
1419 | info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); |
1420 | info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1421 | info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
163c8a59 | 1422 | |
79627472 | 1423 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
d662210a | 1424 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
79627472 LC |
1425 | if (child_bus) { |
1426 | info->has_devices = true; | |
1427 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); | |
1428 | } | |
163c8a59 LC |
1429 | } |
1430 | ||
79627472 | 1431 | return info; |
163c8a59 LC |
1432 | } |
1433 | ||
79627472 LC |
1434 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1435 | int bus_num) | |
163c8a59 | 1436 | { |
79627472 LC |
1437 | const pci_class_desc *desc; |
1438 | PciDeviceInfo *info; | |
b5937f29 | 1439 | uint8_t type; |
79627472 | 1440 | int class; |
163c8a59 | 1441 | |
79627472 LC |
1442 | info = g_malloc0(sizeof(*info)); |
1443 | info->bus = bus_num; | |
1444 | info->slot = PCI_SLOT(dev->devfn); | |
1445 | info->function = PCI_FUNC(dev->devfn); | |
1446 | ||
1447 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1448 | info->class_info.class = class; | |
1449 | desc = get_class_desc(class); | |
1450 | if (desc->desc) { | |
1451 | info->class_info.has_desc = true; | |
1452 | info->class_info.desc = g_strdup(desc->desc); | |
1453 | } | |
1454 | ||
1455 | info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); | |
1456 | info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); | |
1457 | info->regions = qmp_query_pci_regions(dev); | |
1458 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); | |
163c8a59 LC |
1459 | |
1460 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
79627472 LC |
1461 | info->has_irq = true; |
1462 | info->irq = dev->config[PCI_INTERRUPT_LINE]; | |
163c8a59 LC |
1463 | } |
1464 | ||
b5937f29 IY |
1465 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1466 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
79627472 LC |
1467 | info->has_pci_bridge = true; |
1468 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); | |
163c8a59 LC |
1469 | } |
1470 | ||
79627472 | 1471 | return info; |
163c8a59 LC |
1472 | } |
1473 | ||
79627472 | 1474 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
384d8876 | 1475 | { |
79627472 | 1476 | PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
163c8a59 | 1477 | PCIDevice *dev; |
79627472 | 1478 | int devfn; |
163c8a59 LC |
1479 | |
1480 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1481 | dev = bus->devices[devfn]; | |
1482 | if (dev) { | |
79627472 LC |
1483 | info = g_malloc0(sizeof(*info)); |
1484 | info->value = qmp_query_pci_device(dev, bus, bus_num); | |
1485 | ||
1486 | /* XXX: waiting for the qapi to support GSList */ | |
1487 | if (!cur_item) { | |
1488 | head = cur_item = info; | |
1489 | } else { | |
1490 | cur_item->next = info; | |
1491 | cur_item = info; | |
1492 | } | |
163c8a59 | 1493 | } |
1074df4f | 1494 | } |
163c8a59 | 1495 | |
79627472 | 1496 | return head; |
1074df4f IY |
1497 | } |
1498 | ||
79627472 | 1499 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1074df4f | 1500 | { |
79627472 LC |
1501 | PciInfo *info = NULL; |
1502 | ||
d662210a | 1503 | bus = pci_find_bus_nr(bus, bus_num); |
502a5395 | 1504 | if (bus) { |
79627472 LC |
1505 | info = g_malloc0(sizeof(*info)); |
1506 | info->bus = bus_num; | |
1507 | info->devices = qmp_query_pci_devices(bus, bus_num); | |
f2aa58c6 | 1508 | } |
163c8a59 | 1509 | |
79627472 | 1510 | return info; |
f2aa58c6 FB |
1511 | } |
1512 | ||
79627472 | 1513 | PciInfoList *qmp_query_pci(Error **errp) |
f2aa58c6 | 1514 | { |
79627472 | 1515 | PciInfoList *info, *head = NULL, *cur_item = NULL; |
e822a52a | 1516 | struct PCIHostBus *host; |
163c8a59 | 1517 | |
e822a52a | 1518 | QLIST_FOREACH(host, &host_buses, next) { |
79627472 LC |
1519 | info = g_malloc0(sizeof(*info)); |
1520 | info->value = qmp_query_pci_bus(host->bus, 0); | |
1521 | ||
1522 | /* XXX: waiting for the qapi to support GSList */ | |
1523 | if (!cur_item) { | |
1524 | head = cur_item = info; | |
1525 | } else { | |
1526 | cur_item->next = info; | |
1527 | cur_item = info; | |
163c8a59 | 1528 | } |
e822a52a | 1529 | } |
163c8a59 | 1530 | |
79627472 | 1531 | return head; |
77d4bc34 | 1532 | } |
a41b2ff2 | 1533 | |
cb457d76 AL |
1534 | static const char * const pci_nic_models[] = { |
1535 | "ne2k_pci", | |
1536 | "i82551", | |
1537 | "i82557b", | |
1538 | "i82559er", | |
1539 | "rtl8139", | |
1540 | "e1000", | |
1541 | "pcnet", | |
1542 | "virtio", | |
1543 | NULL | |
1544 | }; | |
1545 | ||
9d07d757 PB |
1546 | static const char * const pci_nic_names[] = { |
1547 | "ne2k_pci", | |
1548 | "i82551", | |
1549 | "i82557b", | |
1550 | "i82559er", | |
1551 | "rtl8139", | |
1552 | "e1000", | |
1553 | "pcnet", | |
53c25cea | 1554 | "virtio-net-pci", |
cb457d76 AL |
1555 | NULL |
1556 | }; | |
1557 | ||
a41b2ff2 | 1558 | /* Initialize a PCI NIC. */ |
33e66b86 | 1559 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1560 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1561 | const char *default_devaddr) | |
a41b2ff2 | 1562 | { |
5607c388 | 1563 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1564 | PCIBus *bus; |
1565 | int devfn; | |
5607c388 | 1566 | PCIDevice *pci_dev; |
9d07d757 | 1567 | DeviceState *dev; |
cb457d76 AL |
1568 | int i; |
1569 | ||
07caea31 MA |
1570 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1571 | if (i < 0) | |
1572 | return NULL; | |
1573 | ||
1574 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1575 | if (!bus) { | |
1ecda02b MA |
1576 | error_report("Invalid PCI device address %s for device %s", |
1577 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1578 | return NULL; |
1579 | } | |
1580 | ||
499cf102 | 1581 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1582 | dev = &pci_dev->qdev; |
1cc33683 | 1583 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1584 | if (qdev_init(dev) < 0) |
1585 | return NULL; | |
9ee05825 | 1586 | return pci_dev; |
a41b2ff2 PB |
1587 | } |
1588 | ||
07caea31 MA |
1589 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1590 | const char *default_devaddr) | |
1591 | { | |
1592 | PCIDevice *res; | |
1593 | ||
1594 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1595 | exit(0); | |
1596 | ||
1597 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1598 | if (!res) | |
1599 | exit(1); | |
1600 | return res; | |
1601 | } | |
1602 | ||
129d42fb AJ |
1603 | PCIDevice *pci_vga_init(PCIBus *bus) |
1604 | { | |
1605 | switch (vga_interface_type) { | |
1606 | case VGA_CIRRUS: | |
1607 | return pci_create_simple(bus, -1, "cirrus-vga"); | |
1608 | case VGA_QXL: | |
1609 | return pci_create_simple(bus, -1, "qxl-vga"); | |
1610 | case VGA_STD: | |
1611 | return pci_create_simple(bus, -1, "VGA"); | |
1612 | case VGA_VMWARE: | |
1613 | return pci_create_simple(bus, -1, "vmware-svga"); | |
1614 | case VGA_NONE: | |
1615 | default: /* Other non-PCI types. Checking for unsupported types is already | |
1616 | done in vl.c. */ | |
1617 | return NULL; | |
1618 | } | |
1619 | } | |
1620 | ||
929176c3 MT |
1621 | /* Whether a given bus number is in range of the secondary |
1622 | * bus of the given bridge device. */ | |
1623 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
1624 | { | |
1625 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
1626 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
1627 | dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1628 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; | |
1629 | } | |
1630 | ||
d662210a | 1631 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
3ae80618 | 1632 | { |
470e6363 | 1633 | PCIBus *sec; |
3ae80618 | 1634 | |
470e6363 | 1635 | if (!bus) { |
e822a52a | 1636 | return NULL; |
470e6363 | 1637 | } |
3ae80618 | 1638 | |
e822a52a IY |
1639 | if (pci_bus_num(bus) == bus_num) { |
1640 | return bus; | |
1641 | } | |
1642 | ||
929176c3 MT |
1643 | /* Consider all bus numbers in range for the host pci bridge. */ |
1644 | if (bus->parent_dev && | |
1645 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { | |
1646 | return NULL; | |
1647 | } | |
1648 | ||
e822a52a | 1649 | /* try child bus */ |
929176c3 MT |
1650 | for (; bus; bus = sec) { |
1651 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1652 | assert(sec->parent_dev); | |
1653 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1654 | return sec; | |
1655 | } | |
1656 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
1657 | break; | |
c021f8e6 | 1658 | } |
e822a52a IY |
1659 | } |
1660 | } | |
1661 | ||
1662 | return NULL; | |
3ae80618 AL |
1663 | } |
1664 | ||
5256d8bf | 1665 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 1666 | { |
d662210a | 1667 | bus = pci_find_bus_nr(bus, bus_num); |
3ae80618 AL |
1668 | |
1669 | if (!bus) | |
1670 | return NULL; | |
1671 | ||
5256d8bf | 1672 | return bus->devices[devfn]; |
3ae80618 AL |
1673 | } |
1674 | ||
d307af79 | 1675 | static int pci_qdev_init(DeviceState *qdev) |
6b1b92d3 PB |
1676 | { |
1677 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
40021f08 | 1678 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
6b1b92d3 | 1679 | PCIBus *bus; |
113f89df | 1680 | int rc; |
ab85ceb1 | 1681 | bool is_default_rom; |
6b1b92d3 | 1682 | |
a9f49946 | 1683 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
40021f08 | 1684 | if (pc->is_express) { |
a9f49946 IY |
1685 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1686 | } | |
1687 | ||
02e2da45 | 1688 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
6e008585 AL |
1689 | pci_dev = do_pci_register_device(pci_dev, bus, |
1690 | object_get_typename(OBJECT(qdev)), | |
1691 | pci_dev->devfn); | |
09e3acc6 GH |
1692 | if (pci_dev == NULL) |
1693 | return -1; | |
40021f08 | 1694 | if (qdev->hotplugged && pc->no_hotplug) { |
f79f2bfc | 1695 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); |
180c22e1 GH |
1696 | do_pci_unregister_device(pci_dev); |
1697 | return -1; | |
1698 | } | |
40021f08 AL |
1699 | if (pc->init) { |
1700 | rc = pc->init(pci_dev); | |
c2afc922 IY |
1701 | if (rc != 0) { |
1702 | do_pci_unregister_device(pci_dev); | |
1703 | return rc; | |
1704 | } | |
925fe64a | 1705 | } |
8c52c8f3 GH |
1706 | |
1707 | /* rom loading */ | |
ab85ceb1 | 1708 | is_default_rom = false; |
40021f08 AL |
1709 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1710 | pci_dev->romfile = g_strdup(pc->romfile); | |
ab85ceb1 SW |
1711 | is_default_rom = true; |
1712 | } | |
1713 | pci_add_option_rom(pci_dev, is_default_rom); | |
8c52c8f3 | 1714 | |
5beb8ad5 | 1715 | if (bus->hotplug) { |
e927d487 MT |
1716 | /* Let buses differentiate between hotplug and when device is |
1717 | * enabled during qemu machine creation. */ | |
1718 | rc = bus->hotplug(bus->hotplug_qdev, pci_dev, | |
1719 | qdev->hotplugged ? PCI_HOTPLUG_ENABLED: | |
1720 | PCI_COLDPLUG_ENABLED); | |
a213ff63 IY |
1721 | if (rc != 0) { |
1722 | int r = pci_unregister_device(&pci_dev->qdev); | |
1723 | assert(!r); | |
1724 | return rc; | |
1725 | } | |
1726 | } | |
ee995ffb GH |
1727 | return 0; |
1728 | } | |
1729 | ||
1730 | static int pci_unplug_device(DeviceState *qdev) | |
1731 | { | |
40021f08 AL |
1732 | PCIDevice *dev = PCI_DEVICE(qdev); |
1733 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
ee995ffb | 1734 | |
40021f08 | 1735 | if (pc->no_hotplug) { |
f79f2bfc | 1736 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); |
180c22e1 GH |
1737 | return -1; |
1738 | } | |
e927d487 MT |
1739 | return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, |
1740 | PCI_HOTPLUG_DISABLED); | |
6b1b92d3 PB |
1741 | } |
1742 | ||
49823868 IY |
1743 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1744 | const char *name) | |
6b1b92d3 PB |
1745 | { |
1746 | DeviceState *dev; | |
1747 | ||
02e2da45 | 1748 | dev = qdev_create(&bus->qbus, name); |
09f1bbcd | 1749 | qdev_prop_set_int32(dev, "addr", devfn); |
49823868 | 1750 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
40021f08 | 1751 | return PCI_DEVICE(dev); |
71077c1c | 1752 | } |
6b1b92d3 | 1753 | |
49823868 IY |
1754 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1755 | bool multifunction, | |
1756 | const char *name) | |
71077c1c | 1757 | { |
49823868 | 1758 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1759 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1760 | return dev; |
6b1b92d3 | 1761 | } |
6f4cbd39 | 1762 | |
49823868 IY |
1763 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1764 | { | |
1765 | return pci_create_multifunction(bus, devfn, false, name); | |
1766 | } | |
1767 | ||
1768 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1769 | { | |
1770 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1771 | } | |
1772 | ||
b56d701f | 1773 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
6f4cbd39 MT |
1774 | { |
1775 | int offset = PCI_CONFIG_HEADER_SIZE; | |
1776 | int i; | |
b56d701f | 1777 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
6f4cbd39 MT |
1778 | if (pdev->used[i]) |
1779 | offset = i + 1; | |
1780 | else if (i - offset + 1 == size) | |
1781 | return offset; | |
b56d701f | 1782 | } |
6f4cbd39 MT |
1783 | return 0; |
1784 | } | |
1785 | ||
1786 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1787 | uint8_t *prev_p) | |
1788 | { | |
1789 | uint8_t next, prev; | |
1790 | ||
1791 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1792 | return 0; | |
1793 | ||
1794 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1795 | prev = next + PCI_CAP_LIST_NEXT) | |
1796 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1797 | break; | |
1798 | ||
1799 | if (prev_p) | |
1800 | *prev_p = prev; | |
1801 | return next; | |
1802 | } | |
1803 | ||
c9abe111 JK |
1804 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
1805 | { | |
1806 | uint8_t next, prev, found = 0; | |
1807 | ||
1808 | if (!(pdev->used[offset])) { | |
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); | |
1813 | ||
1814 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1815 | prev = next + PCI_CAP_LIST_NEXT) { | |
1816 | if (next <= offset && next > found) { | |
1817 | found = next; | |
1818 | } | |
1819 | } | |
1820 | return found; | |
1821 | } | |
1822 | ||
ab85ceb1 SW |
1823 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
1824 | This is needed for an option rom which is used for more than one device. */ | |
1825 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) | |
1826 | { | |
1827 | uint16_t vendor_id; | |
1828 | uint16_t device_id; | |
1829 | uint16_t rom_vendor_id; | |
1830 | uint16_t rom_device_id; | |
1831 | uint16_t rom_magic; | |
1832 | uint16_t pcir_offset; | |
1833 | uint8_t checksum; | |
1834 | ||
1835 | /* Words in rom data are little endian (like in PCI configuration), | |
1836 | so they can be read / written with pci_get_word / pci_set_word. */ | |
1837 | ||
1838 | /* Only a valid rom will be patched. */ | |
1839 | rom_magic = pci_get_word(ptr); | |
1840 | if (rom_magic != 0xaa55) { | |
1841 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
1842 | return; | |
1843 | } | |
1844 | pcir_offset = pci_get_word(ptr + 0x18); | |
1845 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
1846 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
1847 | return; | |
1848 | } | |
1849 | ||
1850 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1851 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1852 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
1853 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
1854 | ||
1855 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
1856 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
1857 | ||
1858 | checksum = ptr[6]; | |
1859 | ||
1860 | if (vendor_id != rom_vendor_id) { | |
1861 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
1862 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
1863 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
1864 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1865 | ptr[6] = checksum; | |
1866 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
1867 | } | |
1868 | ||
1869 | if (device_id != rom_device_id) { | |
1870 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
1871 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
1872 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
1873 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1874 | ptr[6] = checksum; | |
1875 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
1876 | } | |
1877 | } | |
1878 | ||
c2039bd0 | 1879 | /* Add an option rom for the device */ |
ab85ceb1 | 1880 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
c2039bd0 AL |
1881 | { |
1882 | int size; | |
1883 | char *path; | |
1884 | void *ptr; | |
1724f049 | 1885 | char name[32]; |
4be9f0d1 | 1886 | const VMStateDescription *vmsd; |
c2039bd0 | 1887 | |
8c52c8f3 GH |
1888 | if (!pdev->romfile) |
1889 | return 0; | |
1890 | if (strlen(pdev->romfile) == 0) | |
1891 | return 0; | |
1892 | ||
88169ddf GH |
1893 | if (!pdev->rom_bar) { |
1894 | /* | |
1895 | * Load rom via fw_cfg instead of creating a rom bar, | |
1896 | * for 0.11 compatibility. | |
1897 | */ | |
1898 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1899 | if (class == 0x0300) { | |
1900 | rom_add_vga(pdev->romfile); | |
1901 | } else { | |
2e55e842 | 1902 | rom_add_option(pdev->romfile, -1); |
88169ddf GH |
1903 | } |
1904 | return 0; | |
1905 | } | |
1906 | ||
8c52c8f3 | 1907 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1908 | if (path == NULL) { |
7267c094 | 1909 | path = g_strdup(pdev->romfile); |
c2039bd0 AL |
1910 | } |
1911 | ||
1912 | size = get_image_size(path); | |
8c52c8f3 | 1913 | if (size < 0) { |
1ecda02b | 1914 | error_report("%s: failed to find romfile \"%s\"", |
8c7f3dd0 SH |
1915 | __func__, pdev->romfile); |
1916 | g_free(path); | |
1917 | return -1; | |
1918 | } else if (size == 0) { | |
1919 | error_report("%s: ignoring empty romfile \"%s\"", | |
1920 | __func__, pdev->romfile); | |
7267c094 | 1921 | g_free(path); |
8c52c8f3 GH |
1922 | return -1; |
1923 | } | |
c2039bd0 AL |
1924 | if (size & (size - 1)) { |
1925 | size = 1 << qemu_fls(size); | |
1926 | } | |
1927 | ||
4be9f0d1 AL |
1928 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
1929 | ||
1930 | if (vmsd) { | |
1931 | snprintf(name, sizeof(name), "%s.rom", vmsd->name); | |
1932 | } else { | |
f79f2bfc | 1933 | snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
4be9f0d1 | 1934 | } |
14caaf7f | 1935 | pdev->has_rom = true; |
c5705a77 AK |
1936 | memory_region_init_ram(&pdev->rom, name, size); |
1937 | vmstate_register_ram(&pdev->rom, &pdev->qdev); | |
14caaf7f | 1938 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
c2039bd0 | 1939 | load_image(path, ptr); |
7267c094 | 1940 | g_free(path); |
c2039bd0 | 1941 | |
ab85ceb1 SW |
1942 | if (is_default_rom) { |
1943 | /* Only the default rom images will be patched (if needed). */ | |
1944 | pci_patch_ids(pdev, ptr, size); | |
1945 | } | |
1946 | ||
8c12f191 JB |
1947 | qemu_put_ram_ptr(ptr); |
1948 | ||
e824b2cc | 1949 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
c2039bd0 AL |
1950 | |
1951 | return 0; | |
1952 | } | |
1953 | ||
230741dc AW |
1954 | static void pci_del_option_rom(PCIDevice *pdev) |
1955 | { | |
14caaf7f | 1956 | if (!pdev->has_rom) |
230741dc AW |
1957 | return; |
1958 | ||
c5705a77 | 1959 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
14caaf7f AK |
1960 | memory_region_destroy(&pdev->rom); |
1961 | pdev->has_rom = false; | |
230741dc AW |
1962 | } |
1963 | ||
ca77089d IY |
1964 | /* |
1965 | * if !offset | |
1966 | * Reserve space and add capability to the linked list in pci config space | |
1967 | * | |
1968 | * if offset = 0, | |
1969 | * Find and reserve space and add capability to the linked list | |
1970 | * in pci config space */ | |
1971 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
1972 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1973 | { |
ca77089d | 1974 | uint8_t *config; |
c9abe111 JK |
1975 | int i, overlapping_cap; |
1976 | ||
ca77089d IY |
1977 | if (!offset) { |
1978 | offset = pci_find_space(pdev, size); | |
1979 | if (!offset) { | |
1980 | return -ENOSPC; | |
1981 | } | |
c9abe111 JK |
1982 | } else { |
1983 | /* Verify that capabilities don't overlap. Note: device assignment | |
1984 | * depends on this check to verify that the device is not broken. | |
1985 | * Should never trigger for emulated devices, but it's helpful | |
1986 | * for debugging these. */ | |
1987 | for (i = offset; i < offset + size; i++) { | |
1988 | overlapping_cap = pci_find_capability_at_offset(pdev, i); | |
1989 | if (overlapping_cap) { | |
1990 | fprintf(stderr, "ERROR: %04x:%02x:%02x.%x " | |
1991 | "Attempt to add PCI capability %x at offset " | |
1992 | "%x overlaps existing capability %x at offset %x\n", | |
1993 | pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), | |
1994 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1995 | cap_id, offset, overlapping_cap, i); | |
1996 | return -EINVAL; | |
1997 | } | |
1998 | } | |
ca77089d IY |
1999 | } |
2000 | ||
2001 | config = pdev->config + offset; | |
6f4cbd39 MT |
2002 | config[PCI_CAP_LIST_ID] = cap_id; |
2003 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
2004 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
2005 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
e26631b7 | 2006 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2007 | /* Make capability read-only by default */ |
2008 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
2009 | /* Check capability by default */ |
2010 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
2011 | return offset; |
2012 | } | |
2013 | ||
2014 | /* Unlink capability from the pci config space. */ | |
2015 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
2016 | { | |
2017 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
2018 | if (!offset) | |
2019 | return; | |
2020 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 2021 | /* Make capability writable again */ |
6f4cbd39 | 2022 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 2023 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
2024 | /* Clear cmask as device-specific registers can't be checked */ |
2025 | memset(pdev->cmask + offset, 0, size); | |
e26631b7 | 2026 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2027 | |
2028 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
2029 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
2030 | } | |
2031 | ||
6f4cbd39 MT |
2032 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2033 | { | |
2034 | return pci_find_capability_list(pdev, cap_id, NULL); | |
2035 | } | |
10c4c98a GH |
2036 | |
2037 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
2038 | { | |
2039 | PCIDevice *d = (PCIDevice *)dev; | |
2040 | const pci_class_desc *desc; | |
2041 | char ctxt[64]; | |
2042 | PCIIORegion *r; | |
2043 | int i, class; | |
2044 | ||
b0ff8eb2 | 2045 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
2046 | desc = pci_class_descriptions; |
2047 | while (desc->desc && class != desc->class) | |
2048 | desc++; | |
2049 | if (desc->desc) { | |
2050 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
2051 | } else { | |
2052 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
2053 | } | |
2054 | ||
2055 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
2056 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
7f5feab4 | 2057 | indent, "", ctxt, pci_bus_num(d->bus), |
e822a52a | 2058 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
2059 | pci_get_word(d->config + PCI_VENDOR_ID), |
2060 | pci_get_word(d->config + PCI_DEVICE_ID), | |
2061 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
2062 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
2063 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2064 | r = &d->io_regions[i]; | |
2065 | if (!r->size) | |
2066 | continue; | |
89e8b13c IY |
2067 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
2068 | " [0x%"FMT_PCIBUS"]\n", | |
2069 | indent, "", | |
0392a017 | 2070 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
2071 | r->addr, r->addr + r->size - 1); |
2072 | } | |
2073 | } | |
03587182 | 2074 | |
5e0259e7 GN |
2075 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2076 | { | |
2077 | PCIDevice *d = (PCIDevice *)dev; | |
2078 | const char *name = NULL; | |
2079 | const pci_class_desc *desc = pci_class_descriptions; | |
2080 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2081 | ||
2082 | while (desc->desc && | |
2083 | (class & ~desc->fw_ign_bits) != | |
2084 | (desc->class & ~desc->fw_ign_bits)) { | |
2085 | desc++; | |
2086 | } | |
2087 | ||
2088 | if (desc->desc) { | |
2089 | name = desc->fw_name; | |
2090 | } | |
2091 | ||
2092 | if (name) { | |
2093 | pstrcpy(buf, len, name); | |
2094 | } else { | |
2095 | snprintf(buf, len, "pci%04x,%04x", | |
2096 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2097 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2098 | } | |
2099 | ||
2100 | return buf; | |
2101 | } | |
2102 | ||
2103 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2104 | { | |
2105 | PCIDevice *d = (PCIDevice *)dev; | |
2106 | char path[50], name[33]; | |
2107 | int off; | |
2108 | ||
2109 | off = snprintf(path, sizeof(path), "%s@%x", | |
2110 | pci_dev_fw_name(dev, name, sizeof name), | |
2111 | PCI_SLOT(d->devfn)); | |
2112 | if (PCI_FUNC(d->devfn)) | |
2113 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
a5cf8262 | 2114 | return g_strdup(path); |
5e0259e7 GN |
2115 | } |
2116 | ||
4f43c1ff AW |
2117 | static char *pcibus_get_dev_path(DeviceState *dev) |
2118 | { | |
a6a7005d MT |
2119 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2120 | PCIDevice *t; | |
2121 | int slot_depth; | |
2122 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2123 | * 00 is added here to make this format compatible with | |
2124 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2125 | * Slot.Function list specifies the slot and function numbers for all | |
2126 | * devices on the path from root to the specific device. */ | |
2991181a MT |
2127 | char domain[] = "DDDD:00"; |
2128 | char slot[] = ":SS.F"; | |
2129 | int domain_len = sizeof domain - 1 /* For '\0' */; | |
2130 | int slot_len = sizeof slot - 1 /* For '\0' */; | |
a6a7005d MT |
2131 | int path_len; |
2132 | char *path, *p; | |
2991181a | 2133 | int s; |
a6a7005d MT |
2134 | |
2135 | /* Calculate # of slots on path between device and root. */; | |
2136 | slot_depth = 0; | |
2137 | for (t = d; t; t = t->bus->parent_dev) { | |
2138 | ++slot_depth; | |
2139 | } | |
2140 | ||
2141 | path_len = domain_len + slot_len * slot_depth; | |
2142 | ||
2143 | /* Allocate memory, fill in the terminating null byte. */ | |
7267c094 | 2144 | path = g_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2145 | path[path_len] = '\0'; |
2146 | ||
2147 | /* First field is the domain. */ | |
2991181a MT |
2148 | s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); |
2149 | assert(s == domain_len); | |
2150 | memcpy(path, domain, domain_len); | |
a6a7005d MT |
2151 | |
2152 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2153 | * them in the reverse order, last to first. */ | |
2154 | p = path + path_len; | |
2155 | for (t = d; t; t = t->bus->parent_dev) { | |
2156 | p -= slot_len; | |
2991181a | 2157 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2158 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2159 | assert(s == slot_len); |
2160 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2161 | } |
2162 | ||
2163 | return path; | |
4f43c1ff AW |
2164 | } |
2165 | ||
f3006dd1 IY |
2166 | static int pci_qdev_find_recursive(PCIBus *bus, |
2167 | const char *id, PCIDevice **pdev) | |
2168 | { | |
2169 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2170 | if (!qdev) { | |
2171 | return -ENODEV; | |
2172 | } | |
2173 | ||
2174 | /* roughly check if given qdev is pci device */ | |
4be9f0d1 | 2175 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
40021f08 | 2176 | *pdev = PCI_DEVICE(qdev); |
f3006dd1 IY |
2177 | return 0; |
2178 | } | |
2179 | return -EINVAL; | |
2180 | } | |
2181 | ||
2182 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2183 | { | |
2184 | struct PCIHostBus *host; | |
2185 | int rc = -ENODEV; | |
2186 | ||
2187 | QLIST_FOREACH(host, &host_buses, next) { | |
2188 | int tmp = pci_qdev_find_recursive(host->bus, id, pdev); | |
2189 | if (!tmp) { | |
2190 | rc = 0; | |
2191 | break; | |
2192 | } | |
2193 | if (tmp != -ENODEV) { | |
2194 | rc = tmp; | |
2195 | } | |
2196 | } | |
2197 | ||
2198 | return rc; | |
2199 | } | |
f5e6fed8 AK |
2200 | |
2201 | MemoryRegion *pci_address_space(PCIDevice *dev) | |
2202 | { | |
2203 | return dev->bus->address_space_mem; | |
2204 | } | |
e11d6439 RH |
2205 | |
2206 | MemoryRegion *pci_address_space_io(PCIDevice *dev) | |
2207 | { | |
2208 | return dev->bus->address_space_io; | |
2209 | } | |
40021f08 | 2210 | |
39bffca2 AL |
2211 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2212 | { | |
2213 | DeviceClass *k = DEVICE_CLASS(klass); | |
2214 | k->init = pci_qdev_init; | |
2215 | k->unplug = pci_unplug_device; | |
2216 | k->exit = pci_unregister_device; | |
0d936928 | 2217 | k->bus_type = TYPE_PCI_BUS; |
bce54474 | 2218 | k->props = pci_props; |
39bffca2 AL |
2219 | } |
2220 | ||
5fa45de5 DG |
2221 | void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque) |
2222 | { | |
2223 | bus->dma_context_fn = fn; | |
2224 | bus->dma_context_opaque = opaque; | |
2225 | } | |
2226 | ||
8c43a6f0 | 2227 | static const TypeInfo pci_device_type_info = { |
40021f08 AL |
2228 | .name = TYPE_PCI_DEVICE, |
2229 | .parent = TYPE_DEVICE, | |
2230 | .instance_size = sizeof(PCIDevice), | |
2231 | .abstract = true, | |
2232 | .class_size = sizeof(PCIDeviceClass), | |
39bffca2 | 2233 | .class_init = pci_device_class_init, |
40021f08 AL |
2234 | }; |
2235 | ||
83f7d43a | 2236 | static void pci_register_types(void) |
40021f08 | 2237 | { |
0d936928 | 2238 | type_register_static(&pci_bus_info); |
40021f08 AL |
2239 | type_register_static(&pci_device_type_info); |
2240 | } | |
2241 | ||
83f7d43a | 2242 | type_init(pci_register_types) |