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df2d8b3e IY |
1 | /* |
2 | * QEMU MCH/ICH9 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * Copyright (c) 2009, 2010, 2011 | |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
10 | * This is based on piix_pci.c, but heavily modified. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
83c9f4ca | 30 | #include "hw/hw.h" |
0d09e41a | 31 | #include "hw/pci-host/q35.h" |
39848901 | 32 | #include "qapi/visitor.h" |
df2d8b3e IY |
33 | |
34 | /**************************************************************************** | |
35 | * Q35 host | |
36 | */ | |
37 | ||
62d92e43 | 38 | static void q35_host_realize(DeviceState *dev, Error **errp) |
df2d8b3e | 39 | { |
ce88812f HT |
40 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
41 | Q35PCIHost *s = Q35_HOST_DEVICE(dev); | |
62d92e43 | 42 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
df2d8b3e | 43 | |
62d92e43 HT |
44 | sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); |
45 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); | |
df2d8b3e | 46 | |
62d92e43 HT |
47 | sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); |
48 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); | |
df2d8b3e | 49 | |
ce88812f | 50 | if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { |
62d92e43 HT |
51 | error_setg(errp, "failed to initialize pcie host"); |
52 | return; | |
df2d8b3e | 53 | } |
ce88812f HT |
54 | pci->bus = pci_bus_new(DEVICE(s), "pcie.0", |
55 | s->mch.pci_address_space, s->mch.address_space_io, | |
56 | 0, TYPE_PCIE_BUS); | |
57 | qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); | |
df2d8b3e | 58 | qdev_init_nofail(DEVICE(&s->mch)); |
df2d8b3e IY |
59 | } |
60 | ||
568f0690 DG |
61 | static const char *q35_host_root_bus_path(PCIHostState *host_bridge, |
62 | PCIBus *rootbus) | |
63 | { | |
04c7d8b8 CR |
64 | Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); |
65 | ||
66 | /* For backwards compat with old device paths */ | |
67 | if (s->mch.short_root_bus) { | |
68 | return "0000"; | |
69 | } | |
70 | return "0000:00"; | |
568f0690 DG |
71 | } |
72 | ||
39848901 IM |
73 | static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, |
74 | void *opaque, const char *name, | |
75 | Error **errp) | |
76 | { | |
77 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
78 | uint32_t value = s->mch.pci_info.w32.begin; | |
79 | ||
80 | visit_type_uint32(v, &value, name, errp); | |
81 | } | |
82 | ||
83 | static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, | |
84 | void *opaque, const char *name, | |
85 | Error **errp) | |
86 | { | |
87 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
88 | uint32_t value = s->mch.pci_info.w32.end; | |
89 | ||
90 | visit_type_uint32(v, &value, name, errp); | |
91 | } | |
92 | ||
93 | static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, | |
94 | void *opaque, const char *name, | |
95 | Error **errp) | |
96 | { | |
8b42d730 MT |
97 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
98 | Range w64; | |
99 | ||
100 | pci_bus_get_w64_range(h->bus, &w64); | |
39848901 | 101 | |
8b42d730 | 102 | visit_type_uint64(v, &w64.begin, name, errp); |
39848901 IM |
103 | } |
104 | ||
105 | static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, | |
106 | void *opaque, const char *name, | |
107 | Error **errp) | |
108 | { | |
8b42d730 MT |
109 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
110 | Range w64; | |
39848901 | 111 | |
8b42d730 | 112 | pci_bus_get_w64_range(h->bus, &w64); |
39848901 | 113 | |
8b42d730 | 114 | visit_type_uint64(v, &w64.end, name, errp); |
39848901 IM |
115 | } |
116 | ||
cbcaf79e MT |
117 | static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, |
118 | void *opaque, const char *name, | |
119 | Error **errp) | |
120 | { | |
121 | PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); | |
122 | uint32_t value = e->size; | |
123 | ||
124 | visit_type_uint32(v, &value, name, errp); | |
125 | } | |
126 | ||
df2d8b3e | 127 | static Property mch_props[] = { |
87f65245 | 128 | DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, |
df2d8b3e | 129 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), |
39848901 IM |
130 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, |
131 | mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), | |
04c7d8b8 | 132 | DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), |
df2d8b3e IY |
133 | DEFINE_PROP_END_OF_LIST(), |
134 | }; | |
135 | ||
136 | static void q35_host_class_init(ObjectClass *klass, void *data) | |
137 | { | |
138 | DeviceClass *dc = DEVICE_CLASS(klass); | |
568f0690 | 139 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
df2d8b3e | 140 | |
568f0690 | 141 | hc->root_bus_path = q35_host_root_bus_path; |
62d92e43 | 142 | dc->realize = q35_host_realize; |
df2d8b3e | 143 | dc->props = mch_props; |
125ee0ed | 144 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
68c0e134 | 145 | dc->fw_name = "pci"; |
df2d8b3e IY |
146 | } |
147 | ||
148 | static void q35_host_initfn(Object *obj) | |
149 | { | |
150 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
62d92e43 HT |
151 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); |
152 | ||
153 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, | |
154 | "pci-conf-idx", 4); | |
155 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, | |
156 | "pci-conf-data", 4); | |
df2d8b3e | 157 | |
213f0c4f | 158 | object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); |
df2d8b3e IY |
159 | object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); |
160 | qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); | |
161 | qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); | |
39848901 IM |
162 | |
163 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", | |
164 | q35_host_get_pci_hole_start, | |
165 | NULL, NULL, NULL, NULL); | |
166 | ||
167 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", | |
168 | q35_host_get_pci_hole_end, | |
169 | NULL, NULL, NULL, NULL); | |
170 | ||
171 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", | |
172 | q35_host_get_pci_hole64_start, | |
173 | NULL, NULL, NULL, NULL); | |
174 | ||
175 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", | |
176 | q35_host_get_pci_hole64_end, | |
177 | NULL, NULL, NULL, NULL); | |
178 | ||
cbcaf79e MT |
179 | object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", |
180 | q35_host_get_mmcfg_size, | |
181 | NULL, NULL, NULL, NULL); | |
182 | ||
39848901 IM |
183 | /* Leave enough space for the biggest MCFG BAR */ |
184 | /* TODO: this matches current bios behaviour, but | |
185 | * it's not a power of two, which means an MTRR | |
186 | * can't cover it exactly. | |
187 | */ | |
188 | s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + | |
189 | MCH_HOST_BRIDGE_PCIEXBAR_MAX; | |
190 | s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; | |
df2d8b3e IY |
191 | } |
192 | ||
193 | static const TypeInfo q35_host_info = { | |
194 | .name = TYPE_Q35_HOST_DEVICE, | |
195 | .parent = TYPE_PCIE_HOST_BRIDGE, | |
196 | .instance_size = sizeof(Q35PCIHost), | |
197 | .instance_init = q35_host_initfn, | |
198 | .class_init = q35_host_class_init, | |
199 | }; | |
200 | ||
201 | /**************************************************************************** | |
202 | * MCH D0:F0 | |
203 | */ | |
204 | ||
205 | /* PCIe MMCFG */ | |
206 | static void mch_update_pciexbar(MCHPCIState *mch) | |
207 | { | |
ce88812f HT |
208 | PCIDevice *pci_dev = PCI_DEVICE(mch); |
209 | BusState *bus = qdev_get_parent_bus(DEVICE(mch)); | |
210 | PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); | |
df2d8b3e IY |
211 | |
212 | uint64_t pciexbar; | |
213 | int enable; | |
214 | uint64_t addr; | |
215 | uint64_t addr_mask; | |
216 | uint32_t length; | |
217 | ||
218 | pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); | |
219 | enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; | |
220 | addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; | |
221 | switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { | |
222 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: | |
223 | length = 256 * 1024 * 1024; | |
224 | break; | |
225 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: | |
226 | length = 128 * 1024 * 1024; | |
227 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | | |
228 | MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
229 | break; | |
230 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: | |
231 | length = 64 * 1024 * 1024; | |
232 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
233 | break; | |
234 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: | |
235 | default: | |
236 | enable = 0; | |
237 | length = 0; | |
238 | abort(); | |
239 | break; | |
240 | } | |
241 | addr = pciexbar & addr_mask; | |
ce88812f | 242 | pcie_host_mmcfg_update(pehb, enable, addr, length); |
636228a8 MT |
243 | /* Leave enough space for the MCFG BAR */ |
244 | /* | |
245 | * TODO: this matches current bios behaviour, but it's not a power of two, | |
246 | * which means an MTRR can't cover it exactly. | |
247 | */ | |
248 | if (enable) { | |
249 | mch->pci_info.w32.begin = addr + length; | |
250 | } else { | |
251 | mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; | |
252 | } | |
df2d8b3e IY |
253 | } |
254 | ||
255 | /* PAM */ | |
256 | static void mch_update_pam(MCHPCIState *mch) | |
257 | { | |
ce88812f | 258 | PCIDevice *pd = PCI_DEVICE(mch); |
df2d8b3e IY |
259 | int i; |
260 | ||
261 | memory_region_transaction_begin(); | |
262 | for (i = 0; i < 13; i++) { | |
263 | pam_update(&mch->pam_regions[i], i, | |
ce88812f | 264 | pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); |
df2d8b3e IY |
265 | } |
266 | memory_region_transaction_commit(); | |
267 | } | |
268 | ||
269 | /* SMRAM */ | |
270 | static void mch_update_smram(MCHPCIState *mch) | |
271 | { | |
ce88812f HT |
272 | PCIDevice *pd = PCI_DEVICE(mch); |
273 | ||
df2d8b3e | 274 | memory_region_transaction_begin(); |
ce88812f | 275 | smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], |
df2d8b3e IY |
276 | mch->smm_enabled); |
277 | memory_region_transaction_commit(); | |
278 | } | |
279 | ||
280 | static void mch_set_smm(int smm, void *arg) | |
281 | { | |
282 | MCHPCIState *mch = arg; | |
ce88812f | 283 | PCIDevice *pd = PCI_DEVICE(mch); |
df2d8b3e IY |
284 | |
285 | memory_region_transaction_begin(); | |
ce88812f | 286 | smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], |
df2d8b3e IY |
287 | &mch->smram_region); |
288 | memory_region_transaction_commit(); | |
289 | } | |
290 | ||
291 | static void mch_write_config(PCIDevice *d, | |
292 | uint32_t address, uint32_t val, int len) | |
293 | { | |
294 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
295 | ||
296 | /* XXX: implement SMRAM.D_LOCK */ | |
297 | pci_default_write_config(d, address, val, len); | |
298 | ||
299 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, | |
300 | MCH_HOST_BRIDGE_PAM_SIZE)) { | |
301 | mch_update_pam(mch); | |
302 | } | |
303 | ||
304 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, | |
305 | MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { | |
306 | mch_update_pciexbar(mch); | |
307 | } | |
308 | ||
309 | if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, | |
310 | MCH_HOST_BRDIGE_SMRAM_SIZE)) { | |
311 | mch_update_smram(mch); | |
312 | } | |
313 | } | |
314 | ||
315 | static void mch_update(MCHPCIState *mch) | |
316 | { | |
317 | mch_update_pciexbar(mch); | |
318 | mch_update_pam(mch); | |
319 | mch_update_smram(mch); | |
320 | } | |
321 | ||
322 | static int mch_post_load(void *opaque, int version_id) | |
323 | { | |
324 | MCHPCIState *mch = opaque; | |
325 | mch_update(mch); | |
326 | return 0; | |
327 | } | |
328 | ||
329 | static const VMStateDescription vmstate_mch = { | |
330 | .name = "mch", | |
331 | .version_id = 1, | |
332 | .minimum_version_id = 1, | |
333 | .minimum_version_id_old = 1, | |
334 | .post_load = mch_post_load, | |
335 | .fields = (VMStateField []) { | |
ce88812f | 336 | VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), |
df2d8b3e IY |
337 | VMSTATE_UINT8(smm_enabled, MCHPCIState), |
338 | VMSTATE_END_OF_LIST() | |
339 | } | |
340 | }; | |
341 | ||
342 | static void mch_reset(DeviceState *qdev) | |
343 | { | |
344 | PCIDevice *d = PCI_DEVICE(qdev); | |
345 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
346 | ||
347 | pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, | |
348 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); | |
349 | ||
350 | d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; | |
351 | ||
352 | mch_update(mch); | |
353 | } | |
354 | ||
355 | static int mch_init(PCIDevice *d) | |
356 | { | |
357 | int i; | |
df2d8b3e | 358 | MCHPCIState *mch = MCH_PCI_DEVICE(d); |
1466cef3 | 359 | uint64_t pci_hole64_size; |
df2d8b3e IY |
360 | |
361 | /* setup pci memory regions */ | |
40c5dce9 | 362 | memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", |
df2d8b3e IY |
363 | mch->pci_address_space, |
364 | mch->below_4g_mem_size, | |
365 | 0x100000000ULL - mch->below_4g_mem_size); | |
366 | memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, | |
367 | &mch->pci_hole); | |
39848901 | 368 | |
1466cef3 | 369 | pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size); |
39848901 | 370 | pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, |
1466cef3 | 371 | pci_hole64_size); |
40c5dce9 | 372 | memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", |
df2d8b3e | 373 | mch->pci_address_space, |
39848901 | 374 | mch->pci_info.w64.begin, |
1466cef3 MT |
375 | pci_hole64_size); |
376 | if (pci_hole64_size) { | |
df2d8b3e | 377 | memory_region_add_subregion(mch->system_memory, |
39848901 | 378 | mch->pci_info.w64.begin, |
df2d8b3e IY |
379 | &mch->pci_hole_64bit); |
380 | } | |
381 | /* smram */ | |
382 | cpu_smm_register(&mch_set_smm, mch); | |
40c5dce9 | 383 | memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", |
df2d8b3e IY |
384 | mch->pci_address_space, 0xa0000, 0x20000); |
385 | memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, | |
386 | &mch->smram_region, 1); | |
387 | memory_region_set_enabled(&mch->smram_region, false); | |
3cd2cf43 | 388 | init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, |
df2d8b3e IY |
389 | &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
390 | for (i = 0; i < 12; ++i) { | |
3cd2cf43 | 391 | init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, |
df2d8b3e IY |
392 | &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
393 | PAM_EXPAN_SIZE); | |
394 | } | |
395 | return 0; | |
396 | } | |
397 | ||
6f1426ab MT |
398 | uint64_t mch_mcfg_base(void) |
399 | { | |
400 | bool ambiguous; | |
401 | Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); | |
402 | if (!o) { | |
403 | return 0; | |
404 | } | |
405 | return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; | |
406 | } | |
407 | ||
df2d8b3e IY |
408 | static void mch_class_init(ObjectClass *klass, void *data) |
409 | { | |
410 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
411 | DeviceClass *dc = DEVICE_CLASS(klass); | |
412 | ||
413 | k->init = mch_init; | |
414 | k->config_write = mch_write_config; | |
415 | dc->reset = mch_reset; | |
125ee0ed | 416 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
df2d8b3e IY |
417 | dc->desc = "Host bridge"; |
418 | dc->vmsd = &vmstate_mch; | |
419 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
420 | k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; | |
451f7846 | 421 | k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; |
df2d8b3e IY |
422 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
423 | } | |
424 | ||
425 | static const TypeInfo mch_info = { | |
426 | .name = TYPE_MCH_PCI_DEVICE, | |
427 | .parent = TYPE_PCI_DEVICE, | |
428 | .instance_size = sizeof(MCHPCIState), | |
429 | .class_init = mch_class_init, | |
430 | }; | |
431 | ||
432 | static void q35_register(void) | |
433 | { | |
434 | type_register_static(&mch_info); | |
435 | type_register_static(&q35_host_info); | |
436 | } | |
437 | ||
438 | type_init(q35_register); |