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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the LGPL. |
502a5395 PB |
8 | */ |
9 | ||
83c9f4ca PB |
10 | #include "hw/sysbus.h" |
11 | #include "hw/pci/pci.h" | |
0688810b | 12 | #include "hw/pci/pci_bus.h" |
83c9f4ca | 13 | #include "hw/pci/pci_host.h" |
022c62cb | 14 | #include "exec/address-spaces.h" |
0027b06d | 15 | |
66a96d70 PM |
16 | /* Old and buggy versions of QEMU used the wrong mapping from |
17 | * PCI IRQs to system interrupt lines. Unfortunately the Linux | |
18 | * kernel also had the corresponding bug in setting up interrupts | |
19 | * (so older kernels work on QEMU and not on real hardware). | |
20 | * We automatically detect these broken kernels and flip back | |
21 | * to the broken irq mapping by spotting guest writes to the | |
22 | * PCI_INTERRUPT_LINE register to see where the guest thinks | |
23 | * interrupts are going to be routed. So we start in state | |
24 | * ASSUME_OK on reset, and transition to either BROKEN or | |
25 | * FORCE_OK at the first write to an INTERRUPT_LINE register for | |
26 | * a slot where broken and correct interrupt mapping would differ. | |
27 | * Once in either BROKEN or FORCE_OK we never transition again; | |
28 | * this allows a newer kernel to use the INTERRUPT_LINE | |
29 | * registers arbitrarily once it has indicated that it isn't | |
30 | * broken in its init code somewhere. | |
31 | */ | |
32 | enum { | |
33 | PCI_VPB_IRQMAP_ASSUME_OK, | |
34 | PCI_VPB_IRQMAP_BROKEN, | |
35 | PCI_VPB_IRQMAP_FORCE_OK, | |
36 | }; | |
37 | ||
0027b06d | 38 | typedef struct { |
0688810b PM |
39 | PCIHostState parent_obj; |
40 | ||
0027b06d | 41 | qemu_irq irq[4]; |
7468d73a | 42 | MemoryRegion controlregs; |
45de094e AK |
43 | MemoryRegion mem_config; |
44 | MemoryRegion mem_config2; | |
89a32d32 | 45 | /* Containers representing the PCI address spaces */ |
967c2607 | 46 | MemoryRegion pci_io_space; |
89a32d32 PM |
47 | MemoryRegion pci_mem_space; |
48 | /* Alias regions into PCI address spaces which we expose as sysbus regions. | |
49 | * The offsets into pci_mem_space are controlled by the imap registers. | |
50 | */ | |
967c2607 | 51 | MemoryRegion pci_io_window; |
89a32d32 | 52 | MemoryRegion pci_mem_window[3]; |
0688810b PM |
53 | PCIBus pci_bus; |
54 | PCIDevice pci_dev; | |
55 | ||
56 | /* Constant for life of device: */ | |
57 | int realview; | |
89a32d32 | 58 | uint32_t mem_win_size[3]; |
66a96d70 PM |
59 | |
60 | /* Variable state: */ | |
7468d73a PM |
61 | uint32_t imap[3]; |
62 | uint32_t smap[3]; | |
63 | uint32_t selfid; | |
64 | uint32_t flags; | |
66a96d70 | 65 | uint8_t irq_mapping; |
0027b06d | 66 | } PCIVPBState; |
502a5395 | 67 | |
89a32d32 PM |
68 | static void pci_vpb_update_window(PCIVPBState *s, int i) |
69 | { | |
70 | /* Adjust the offset of the alias region we use for | |
71 | * the memory window i to account for a change in the | |
72 | * value of the corresponding IMAP register. | |
73 | * Note that the semantics of the IMAP register differ | |
74 | * for realview and versatile variants of the controller. | |
75 | */ | |
76 | hwaddr offset; | |
77 | if (s->realview) { | |
78 | /* Top bits of register (masked according to window size) provide | |
79 | * top bits of PCI address. | |
80 | */ | |
81 | offset = s->imap[i] & ~(s->mem_win_size[i] - 1); | |
82 | } else { | |
83 | /* Bottom 4 bits of register provide top 4 bits of PCI address */ | |
84 | offset = s->imap[i] << 28; | |
85 | } | |
86 | memory_region_set_alias_offset(&s->pci_mem_window[i], offset); | |
87 | } | |
88 | ||
89 | static void pci_vpb_update_all_windows(PCIVPBState *s) | |
90 | { | |
91 | /* Update all alias windows based on the current register state */ | |
92 | int i; | |
93 | ||
94 | for (i = 0; i < 3; i++) { | |
95 | pci_vpb_update_window(s, i); | |
96 | } | |
97 | } | |
98 | ||
99 | static int pci_vpb_post_load(void *opaque, int version_id) | |
100 | { | |
101 | PCIVPBState *s = opaque; | |
102 | pci_vpb_update_all_windows(s); | |
103 | return 0; | |
104 | } | |
105 | ||
7468d73a PM |
106 | static const VMStateDescription pci_vpb_vmstate = { |
107 | .name = "versatile-pci", | |
108 | .version_id = 1, | |
109 | .minimum_version_id = 1, | |
89a32d32 | 110 | .post_load = pci_vpb_post_load, |
7468d73a PM |
111 | .fields = (VMStateField[]) { |
112 | VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3), | |
113 | VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3), | |
114 | VMSTATE_UINT32(selfid, PCIVPBState), | |
115 | VMSTATE_UINT32(flags, PCIVPBState), | |
116 | VMSTATE_UINT8(irq_mapping, PCIVPBState), | |
117 | VMSTATE_END_OF_LIST() | |
118 | } | |
119 | }; | |
120 | ||
cd93dbf3 PM |
121 | #define TYPE_VERSATILE_PCI "versatile_pci" |
122 | #define PCI_VPB(obj) \ | |
123 | OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI) | |
124 | ||
125 | #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host" | |
126 | #define PCI_VPB_HOST(obj) \ | |
127 | OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST) | |
128 | ||
7468d73a PM |
129 | typedef enum { |
130 | PCI_IMAP0 = 0x0, | |
131 | PCI_IMAP1 = 0x4, | |
132 | PCI_IMAP2 = 0x8, | |
133 | PCI_SELFID = 0xc, | |
134 | PCI_FLAGS = 0x10, | |
135 | PCI_SMAP0 = 0x14, | |
136 | PCI_SMAP1 = 0x18, | |
137 | PCI_SMAP2 = 0x1c, | |
138 | } PCIVPBControlRegs; | |
139 | ||
140 | static void pci_vpb_reg_write(void *opaque, hwaddr addr, | |
141 | uint64_t val, unsigned size) | |
142 | { | |
143 | PCIVPBState *s = opaque; | |
144 | ||
145 | switch (addr) { | |
146 | case PCI_IMAP0: | |
147 | case PCI_IMAP1: | |
148 | case PCI_IMAP2: | |
149 | { | |
150 | int win = (addr - PCI_IMAP0) >> 2; | |
151 | s->imap[win] = val; | |
89a32d32 | 152 | pci_vpb_update_window(s, win); |
7468d73a PM |
153 | break; |
154 | } | |
155 | case PCI_SELFID: | |
156 | s->selfid = val; | |
157 | break; | |
158 | case PCI_FLAGS: | |
159 | s->flags = val; | |
160 | break; | |
161 | case PCI_SMAP0: | |
162 | case PCI_SMAP1: | |
163 | case PCI_SMAP2: | |
164 | { | |
165 | int win = (addr - PCI_SMAP0) >> 2; | |
166 | s->smap[win] = val; | |
167 | break; | |
168 | } | |
169 | default: | |
170 | qemu_log_mask(LOG_GUEST_ERROR, | |
171 | "pci_vpb_reg_write: Bad offset %x\n", (int)addr); | |
172 | break; | |
173 | } | |
174 | } | |
175 | ||
176 | static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr, | |
177 | unsigned size) | |
178 | { | |
179 | PCIVPBState *s = opaque; | |
180 | ||
181 | switch (addr) { | |
182 | case PCI_IMAP0: | |
183 | case PCI_IMAP1: | |
184 | case PCI_IMAP2: | |
185 | { | |
186 | int win = (addr - PCI_IMAP0) >> 2; | |
187 | return s->imap[win]; | |
188 | } | |
189 | case PCI_SELFID: | |
190 | return s->selfid; | |
191 | case PCI_FLAGS: | |
192 | return s->flags; | |
193 | case PCI_SMAP0: | |
194 | case PCI_SMAP1: | |
195 | case PCI_SMAP2: | |
196 | { | |
197 | int win = (addr - PCI_SMAP0) >> 2; | |
198 | return s->smap[win]; | |
199 | } | |
200 | default: | |
201 | qemu_log_mask(LOG_GUEST_ERROR, | |
202 | "pci_vpb_reg_read: Bad offset %x\n", (int)addr); | |
203 | return 0; | |
204 | } | |
205 | } | |
206 | ||
207 | static const MemoryRegionOps pci_vpb_reg_ops = { | |
208 | .read = pci_vpb_reg_read, | |
209 | .write = pci_vpb_reg_write, | |
210 | .endianness = DEVICE_NATIVE_ENDIAN, | |
211 | .valid = { | |
212 | .min_access_size = 4, | |
213 | .max_access_size = 4, | |
214 | }, | |
215 | }; | |
216 | ||
a8170e5e | 217 | static void pci_vpb_config_write(void *opaque, hwaddr addr, |
45de094e | 218 | uint64_t val, unsigned size) |
502a5395 | 219 | { |
66a96d70 PM |
220 | PCIVPBState *s = opaque; |
221 | if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE | |
222 | && s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) { | |
223 | uint8_t devfn = addr >> 8; | |
224 | if ((PCI_SLOT(devfn) % PCI_NUM_PINS) != 2) { | |
225 | if (val == 27) { | |
226 | s->irq_mapping = PCI_VPB_IRQMAP_BROKEN; | |
227 | } else { | |
228 | s->irq_mapping = PCI_VPB_IRQMAP_FORCE_OK; | |
229 | } | |
230 | } | |
231 | } | |
af9277e6 | 232 | pci_data_write(&s->pci_bus, addr, val, size); |
502a5395 PB |
233 | } |
234 | ||
a8170e5e | 235 | static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr, |
45de094e | 236 | unsigned size) |
502a5395 | 237 | { |
66a96d70 | 238 | PCIVPBState *s = opaque; |
502a5395 | 239 | uint32_t val; |
af9277e6 | 240 | val = pci_data_read(&s->pci_bus, addr, size); |
502a5395 PB |
241 | return val; |
242 | } | |
243 | ||
45de094e AK |
244 | static const MemoryRegionOps pci_vpb_config_ops = { |
245 | .read = pci_vpb_config_read, | |
246 | .write = pci_vpb_config_write, | |
247 | .endianness = DEVICE_NATIVE_ENDIAN, | |
502a5395 PB |
248 | }; |
249 | ||
d2b59317 PB |
250 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
251 | { | |
66a96d70 PM |
252 | PCIVPBState *s = container_of(d->bus, PCIVPBState, pci_bus); |
253 | ||
254 | if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) { | |
255 | /* Legacy broken IRQ mapping for compatibility with old and | |
256 | * buggy Linux guests | |
257 | */ | |
258 | return irq_num; | |
259 | } | |
260 | ||
261 | /* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane | |
262 | * name slot IntA IntB IntC IntD | |
263 | * A 31 IRQ28 IRQ29 IRQ30 IRQ27 | |
264 | * B 30 IRQ27 IRQ28 IRQ29 IRQ30 | |
265 | * C 29 IRQ30 IRQ27 IRQ28 IRQ29 | |
266 | * Slot C is for the host bridge; A and B the peripherals. | |
267 | * Our output irqs 0..3 correspond to the baseboard's 27..30. | |
268 | * | |
269 | * This mapping function takes account of an oddity in the PB926 | |
270 | * board wiring, where the FPGA's P_nINTA input is connected to | |
271 | * the INTB connection on the board PCI edge connector, P_nINTB | |
272 | * is connected to INTC, and so on, so everything is one number | |
273 | * further round from where you might expect. | |
274 | */ | |
275 | return pci_swizzle_map_irq_fn(d, irq_num + 2); | |
276 | } | |
277 | ||
278 | static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num) | |
279 | { | |
280 | /* Slot to IRQ mapping for RealView EB and PB1176 backplane | |
281 | * name slot IntA IntB IntC IntD | |
282 | * A 31 IRQ50 IRQ51 IRQ48 IRQ49 | |
283 | * B 30 IRQ49 IRQ50 IRQ51 IRQ48 | |
284 | * C 29 IRQ48 IRQ49 IRQ50 IRQ51 | |
285 | * Slot C is for the host bridge; A and B the peripherals. | |
286 | * Our output irqs 0..3 correspond to the baseboard's 48..51. | |
287 | * | |
288 | * The PB1176 and EB boards don't have the PB926 wiring oddity | |
289 | * described above; P_nINTA connects to INTA, P_nINTB to INTB | |
290 | * and so on, which is why this mapping function is different. | |
291 | */ | |
292 | return pci_swizzle_map_irq_fn(d, irq_num + 3); | |
d2b59317 PB |
293 | } |
294 | ||
5d4e84c8 | 295 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 296 | { |
5d4e84c8 JQ |
297 | qemu_irq *pic = opaque; |
298 | ||
97aff481 | 299 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
300 | } |
301 | ||
66a96d70 PM |
302 | static void pci_vpb_reset(DeviceState *d) |
303 | { | |
304 | PCIVPBState *s = PCI_VPB(d); | |
305 | ||
7468d73a PM |
306 | s->imap[0] = 0; |
307 | s->imap[1] = 0; | |
308 | s->imap[2] = 0; | |
309 | s->smap[0] = 0; | |
310 | s->smap[1] = 0; | |
311 | s->smap[2] = 0; | |
312 | s->selfid = 0; | |
313 | s->flags = 0; | |
66a96d70 | 314 | s->irq_mapping = PCI_VPB_IRQMAP_ASSUME_OK; |
89a32d32 PM |
315 | |
316 | pci_vpb_update_all_windows(s); | |
66a96d70 PM |
317 | } |
318 | ||
0688810b PM |
319 | static void pci_vpb_init(Object *obj) |
320 | { | |
321 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
322 | PCIVPBState *s = PCI_VPB(obj); | |
323 | ||
967c2607 | 324 | memory_region_init(&s->pci_io_space, "pci_io", 1ULL << 32); |
89a32d32 | 325 | memory_region_init(&s->pci_mem_space, "pci_mem", 1ULL << 32); |
967c2607 | 326 | |
0688810b | 327 | pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), "pci", |
89a32d32 | 328 | &s->pci_mem_space, &s->pci_io_space, |
0688810b PM |
329 | PCI_DEVFN(11, 0), TYPE_PCI_BUS); |
330 | h->bus = &s->pci_bus; | |
331 | ||
332 | object_initialize(&s->pci_dev, TYPE_VERSATILE_PCI_HOST); | |
333 | qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus)); | |
5f37ef92 PM |
334 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(29, 0), "addr", |
335 | NULL); | |
89a32d32 PM |
336 | |
337 | /* Window sizes for VersatilePB; realview_pci's init will override */ | |
338 | s->mem_win_size[0] = 0x0c000000; | |
339 | s->mem_win_size[1] = 0x10000000; | |
340 | s->mem_win_size[2] = 0x10000000; | |
0688810b PM |
341 | } |
342 | ||
cd93dbf3 | 343 | static void pci_vpb_realize(DeviceState *dev, Error **errp) |
0027b06d | 344 | { |
cd93dbf3 PM |
345 | PCIVPBState *s = PCI_VPB(dev); |
346 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
66a96d70 | 347 | pci_map_irq_fn mapfn; |
97aff481 | 348 | int i; |
e69954b9 | 349 | |
97aff481 | 350 | for (i = 0; i < 4; i++) { |
cd93dbf3 | 351 | sysbus_init_irq(sbd, &s->irq[i]); |
e69954b9 | 352 | } |
0688810b | 353 | |
66a96d70 PM |
354 | if (s->realview) { |
355 | mapfn = pci_vpb_rv_map_irq; | |
356 | } else { | |
357 | mapfn = pci_vpb_map_irq; | |
358 | } | |
359 | ||
360 | pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); | |
0027b06d | 361 | |
7d6e771f | 362 | /* Our memory regions are: |
7468d73a PM |
363 | * 0 : our control registers |
364 | * 1 : PCI self config window | |
365 | * 2 : PCI config window | |
366 | * 3 : PCI IO window | |
89a32d32 | 367 | * 4..6 : PCI memory windows |
7d6e771f | 368 | */ |
7468d73a PM |
369 | memory_region_init_io(&s->controlregs, &pci_vpb_reg_ops, s, "pci-vpb-regs", |
370 | 0x1000); | |
371 | sysbus_init_mmio(sbd, &s->controlregs); | |
66a96d70 | 372 | memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, s, |
45de094e | 373 | "pci-vpb-selfconfig", 0x1000000); |
cd93dbf3 | 374 | sysbus_init_mmio(sbd, &s->mem_config); |
66a96d70 | 375 | memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, s, |
45de094e | 376 | "pci-vpb-config", 0x1000000); |
cd93dbf3 | 377 | sysbus_init_mmio(sbd, &s->mem_config2); |
967c2607 PM |
378 | |
379 | /* The window into I/O space is always into a fixed base address; | |
380 | * its size is the same for both realview and versatile. | |
381 | */ | |
382 | memory_region_init_alias(&s->pci_io_window, "pci-vbp-io-window", | |
383 | &s->pci_io_space, 0, 0x100000); | |
384 | ||
385 | sysbus_init_mmio(sbd, &s->pci_io_space); | |
45de094e | 386 | |
89a32d32 PM |
387 | /* Create the alias regions corresponding to our three windows onto |
388 | * PCI memory space. The sizes vary from board to board; the base | |
389 | * offsets are guest controllable via the IMAP registers. | |
390 | */ | |
391 | for (i = 0; i < 3; i++) { | |
392 | memory_region_init_alias(&s->pci_mem_window[i], "pci-vbp-window", | |
393 | &s->pci_mem_space, 0, s->mem_win_size[i]); | |
394 | sysbus_init_mmio(sbd, &s->pci_mem_window[i]); | |
395 | } | |
396 | ||
0688810b PM |
397 | /* TODO Remove once realize propagates to child devices. */ |
398 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); | |
0027b06d | 399 | } |
502a5395 | 400 | |
81a322d4 | 401 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 402 | { |
a408b1de | 403 | pci_set_word(d->config + PCI_STATUS, |
c5c86c53 | 404 | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); |
01764fe0 | 405 | pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); |
81a322d4 | 406 | return 0; |
0027b06d | 407 | } |
502a5395 | 408 | |
40021f08 AL |
409 | static void versatile_pci_host_class_init(ObjectClass *klass, void *data) |
410 | { | |
411 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
412 | ||
413 | k->init = versatile_pci_host_init; | |
414 | k->vendor_id = PCI_VENDOR_ID_XILINX; | |
415 | k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30; | |
416 | k->class_id = PCI_CLASS_PROCESSOR_CO; | |
417 | } | |
418 | ||
8c43a6f0 | 419 | static const TypeInfo versatile_pci_host_info = { |
cd93dbf3 | 420 | .name = TYPE_VERSATILE_PCI_HOST, |
39bffca2 AL |
421 | .parent = TYPE_PCI_DEVICE, |
422 | .instance_size = sizeof(PCIDevice), | |
423 | .class_init = versatile_pci_host_class_init, | |
0aab0d3a GH |
424 | }; |
425 | ||
999e12bb AL |
426 | static void pci_vpb_class_init(ObjectClass *klass, void *data) |
427 | { | |
cd93dbf3 | 428 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 429 | |
cd93dbf3 | 430 | dc->realize = pci_vpb_realize; |
66a96d70 | 431 | dc->reset = pci_vpb_reset; |
7468d73a | 432 | dc->vmsd = &pci_vpb_vmstate; |
999e12bb AL |
433 | } |
434 | ||
8c43a6f0 | 435 | static const TypeInfo pci_vpb_info = { |
cd93dbf3 | 436 | .name = TYPE_VERSATILE_PCI, |
0688810b | 437 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 438 | .instance_size = sizeof(PCIVPBState), |
0688810b | 439 | .instance_init = pci_vpb_init, |
39bffca2 | 440 | .class_init = pci_vpb_class_init, |
999e12bb AL |
441 | }; |
442 | ||
cd93dbf3 | 443 | static void pci_realview_init(Object *obj) |
999e12bb | 444 | { |
cd93dbf3 | 445 | PCIVPBState *s = PCI_VPB(obj); |
999e12bb | 446 | |
cd93dbf3 | 447 | s->realview = 1; |
89a32d32 PM |
448 | /* The PCI window sizes are different on Realview boards */ |
449 | s->mem_win_size[0] = 0x01000000; | |
450 | s->mem_win_size[1] = 0x04000000; | |
451 | s->mem_win_size[2] = 0x08000000; | |
999e12bb AL |
452 | } |
453 | ||
8c43a6f0 | 454 | static const TypeInfo pci_realview_info = { |
39bffca2 | 455 | .name = "realview_pci", |
cd93dbf3 PM |
456 | .parent = TYPE_VERSATILE_PCI, |
457 | .instance_init = pci_realview_init, | |
999e12bb AL |
458 | }; |
459 | ||
83f7d43a | 460 | static void versatile_pci_register_types(void) |
0027b06d | 461 | { |
39bffca2 AL |
462 | type_register_static(&pci_vpb_info); |
463 | type_register_static(&pci_realview_info); | |
464 | type_register_static(&versatile_pci_host_info); | |
502a5395 | 465 | } |
0027b06d | 466 | |
83f7d43a | 467 | type_init(versatile_pci_register_types) |