[qemu.git] / hw / pci.c

/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PCI

typedef struct PCIBridge {
    uint32_t config_reg;
    PCIDevice **pci_bus[256];
} PCIBridge;

static PCIBridge pci_bridge;
target_phys_addr_t pci_mem_base;

/* -1 for devfn means auto assign */
PCIDevice *pci_register_device(const char *name, int instance_size,
                               int bus_num, int devfn,
                               PCIConfigReadFunc *config_read, 
                               PCIConfigWriteFunc *config_write)
{
    PCIBridge *s = &pci_bridge;
    PCIDevice *pci_dev, **bus;

    if (!s->pci_bus[bus_num]) {
        s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
        if (!s->pci_bus[bus_num])
            return NULL;
    }
    bus = s->pci_bus[bus_num];
    if (devfn < 0) {
        for(devfn = 0 ; devfn < 256; devfn += 8) {
            if (!bus[devfn])
                goto found;
        }
        return NULL;
    found: ;
    }
    pci_dev = qemu_mallocz(instance_size);
    if (!pci_dev)
        return NULL;
    pci_dev->bus_num = bus_num;
    pci_dev->devfn = devfn;
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
    bus[devfn] = pci_dev;
    return pci_dev;
}

void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
                            uint32_t size, int type, 
                            PCIMapIORegionFunc *map_func)
{
    PCIIORegion *r;

    if ((unsigned int)region_num >= 6)
        return;
    r = &pci_dev->io_regions[region_num];
    r->addr = -1;
    r->size = size;
    r->type = type;
    r->map_func = map_func;
}

static void pci_config_writel(void* opaque, uint32_t addr, uint32_t val)
{
    PCIBridge *s = opaque;
    s->config_reg = val;
}

static uint32_t pci_config_readl(void* opaque, uint32_t addr)
{
    PCIBridge *s = opaque;
    return s->config_reg;
}

static void unmap_region(PCIIORegion *r)
{
    if (r->addr == -1)
        return;
#ifdef DEBUG_PCI
    printf("unmap addr=%08x size=%08x\n", r->addr, r->size);
#endif
    if (r->type & PCI_ADDRESS_SPACE_IO) {
        isa_unassign_ioport(r->addr, r->size);
    } else {
        cpu_register_physical_memory(r->addr + pci_mem_base, r->size, 
                                     IO_MEM_UNASSIGNED);
    }
}

static void pci_data_write(void *opaque, uint32_t addr, 
                           uint32_t val, int len)
{
    PCIBridge *s = opaque;
    PCIDevice **bus, *pci_dev;
    int config_addr, reg;
    
#if defined(DEBUG_PCI) && 0
    printf("pci_data_write: addr=%08x val=%08x len=%d\n",
           s->config_reg, val, len);
#endif
    if (!(s->config_reg & (1 << 31))) {
        return;
    }
    if ((s->config_reg & 0x3) != 0) {
        return;
    }
    bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
    if (!bus)
        return;
    pci_dev = bus[(s->config_reg >> 8) & 0xff];
    if (!pci_dev)
        return;
    config_addr = (s->config_reg & 0xfc) | (addr & 3);

#if defined(DEBUG_PCI)
    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
           pci_dev->name, config_addr, val, len);
#endif
    if (len == 4 && (config_addr >= 0x10 && config_addr < 0x10 + 4 * 6)) {
        PCIIORegion *r;
        reg = (config_addr - 0x10) >> 2;
        r = &pci_dev->io_regions[reg];
        if (r->size == 0)
            goto default_config;
        if (val != 0xffffffff && val != 0) {
            /* XXX: the memory assignment should be global to handle
               overlaps, but it is not needed at this stage */
            /* first unmap the old region */
            unmap_region(r);
            /* change the address */
            if (r->type & PCI_ADDRESS_SPACE_IO) 
                r->addr = val & ~0x3;
            else
                r->addr = val & ~0xf;
#ifdef DEBUG_PCI
            printf("map addr=%08x size=%08x type=%d\n", 
                   r->addr, r->size, r->type);
#endif
            r->map_func(pci_dev, reg, r->addr, r->size, r->type);
        }
        /* now compute the stored value */
        val &= ~(r->size - 1);
        val |= r->type;
        *(uint32_t *)(pci_dev->config + 0x10 + reg * 4) = cpu_to_le32(val);
    } else {
    default_config:
        pci_dev->config_write(pci_dev, config_addr, val, len);
    }
}

static uint32_t pci_data_read(void *opaque, uint32_t addr, 
                              int len)
{
    PCIBridge *s = opaque;
    PCIDevice **bus, *pci_dev;
    int config_addr;
    uint32_t val;

    if (!(s->config_reg & (1 << 31)))
        goto fail;
    if ((s->config_reg & 0x3) != 0)
        goto fail;
    bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
    if (!bus)
        goto fail;
    pci_dev = bus[(s->config_reg >> 8) & 0xff];
    if (!pci_dev) {
    fail:
        val = 0;
        goto the_end;
    }
    config_addr = (s->config_reg & 0xfc) | (addr & 3);
    val = pci_dev->config_read(pci_dev, config_addr, len);
#if defined(DEBUG_PCI)
    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
           pci_dev->name, config_addr, val, len);
#endif
 the_end:
#if defined(DEBUG_PCI) && 0
    printf("pci_data_read: addr=%08x val=%08x len=%d\n",
           s->config_reg, val, len);
#endif
    return val;
}

static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 1);
}

static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 2);
}

static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
{
    pci_data_write(opaque, addr, val, 4);
}

static uint32_t pci_data_readb(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 1);
}

static uint32_t pci_data_readw(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 2);
}

static uint32_t pci_data_readl(void* opaque, uint32_t addr)
{
    return pci_data_read(opaque, addr, 4);
}

/* i440FX PCI bridge */

static uint32_t i440_read_config(PCIDevice *d, 
                                 uint32_t address, int len)
{
    uint32_t val;
    val = 0;
    memcpy(&val, d->config + address, len);
    return val;
}

static void i440_write_config(PCIDevice *d, 
                              uint32_t address, uint32_t val, int len)
{
    memcpy(d->config + address, &val, len);
}

void i440fx_init(void)
{
    PCIBridge *s = &pci_bridge;
    PCIDevice *d;

    register_ioport_write(0xcf8, 4, 4, pci_config_writel, s);
    register_ioport_read(0xcf8, 4, 4, pci_config_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);

    d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0, 
                            i440_read_config, i440_write_config);

    d->config[0x00] = 0x86; // vendor_id
    d->config[0x01] = 0x80;
    d->config[0x02] = 0x37; // device_id
    d->config[0x03] = 0x12;
    d->config[0x08] = 0x02; // revision
    d->config[0x0a] = 0x04; // class_sub = pci2pci
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
    d->config[0x0c] = 0x01; // line_size in 32 bit words
    d->config[0x0e] = 0x01; // header_type
}

/* NOTE: the following should be done by the BIOS */

static uint32_t pci_bios_io_addr;
static uint32_t pci_bios_mem_addr;

static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
{
    PCIBridge *s = &pci_bridge;
    PCIIORegion *r;

    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
        (d->devfn << 8) | (0x10 + region_num * 4);
    pci_data_write(s, 0, addr, 4);
    r = &d->io_regions[region_num];

    /* enable memory mappings */
    if (r->type & PCI_ADDRESS_SPACE_IO)
        d->config[0x04] |= 1;
    else
        d->config[0x04] |= 2;
}


static void pci_bios_init_device(PCIDevice *d)
{
    int class;
    PCIIORegion *r;
    uint32_t *paddr;
    int i;

    class = d->config[0x0a] | (d->config[0x0b] << 8);
    switch(class) {
    case 0x0101:
        /* IDE: we map it as in ISA mode */
        pci_set_io_region_addr(d, 0, 0x1f0);
        pci_set_io_region_addr(d, 1, 0x3f4);
        pci_set_io_region_addr(d, 2, 0x170);
        pci_set_io_region_addr(d, 3, 0x374);
        break;
    default:
        /* default memory mappings */
        for(i = 0; i < 6; i++) {
            r = &d->io_regions[i];
            if (r->size) {
                if (r->type & PCI_ADDRESS_SPACE_IO)
                    paddr = &pci_bios_io_addr;
                else
                    paddr = &pci_bios_mem_addr;
                *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
                pci_set_io_region_addr(d, i, *paddr);
                *paddr += r->size;
            }
        }
        break;
    }
}

/*
 * This function initializes the PCI devices as a normal PCI BIOS
 * would do. It is provided just in case the BIOS has no support for
 * PCI.
 */
void pci_bios_init(void)
{
    PCIBridge *s = &pci_bridge;
    PCIDevice **bus;
    int bus_num, devfn;

    pci_bios_io_addr = 0xc000;
    pci_bios_mem_addr = 0xf0000000;

    for(bus_num = 0; bus_num < 256; bus_num++) {
        bus = s->pci_bus[bus_num];
        if (bus) {
            for(devfn = 0; devfn < 256; devfn++) {
                if (bus[devfn])
                    pci_bios_init_device(bus[devfn]);
            }
        }
    }
}
Commit	Line	Data
69b91039 FB	1	/*
	2	* QEMU PCI bus manager
	3	*
	4	* Copyright (c) 2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	//#define DEBUG_PCI
	27
	28	typedef struct PCIBridge {
	29	uint32_t config_reg;
	30	PCIDevice **pci_bus[256];
	31	} PCIBridge;
	32
	33	static PCIBridge pci_bridge;
	34	target_phys_addr_t pci_mem_base;
	35
	36	/* -1 for devfn means auto assign */
	37	PCIDevice pci_register_device(const char name, int instance_size,
	38	int bus_num, int devfn,
	39	PCIConfigReadFunc *config_read,
	40	PCIConfigWriteFunc *config_write)
	41	{
	42	PCIBridge *s = &pci_bridge;
	43	PCIDevice pci_dev, *bus;
	44
	45	if (!s->pci_bus[bus_num]) {
	46	s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
	47	if (!s->pci_bus[bus_num])
	48	return NULL;
	49	}
	50	bus = s->pci_bus[bus_num];
	51	if (devfn < 0) {
	52	for(devfn = 0 ; devfn < 256; devfn += 8) {
	53	if (!bus[devfn])
	54	goto found;
	55	}
	56	return NULL;
	57	found: ;
	58	}
	59	pci_dev = qemu_mallocz(instance_size);
	60	if (!pci_dev)
	61	return NULL;
	62	pci_dev->bus_num = bus_num;
	63	pci_dev->devfn = devfn;
	64	pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
65	pci_dev->config_read = config_read;
66	pci_dev->config_write = config_write;
67	bus[devfn] = pci_dev;
68	return pci_dev;
69	}
70
71	void pci_register_io_region(PCIDevice *pci_dev, int region_num,
72	uint32_t size, int type,
73	PCIMapIORegionFunc *map_func)
74	{
75	PCIIORegion *r;
76
77	if ((unsigned int)region_num >= 6)
78	return;
79	r = &pci_dev->io_regions[region_num];
80	r->addr = -1;
81	r->size = size;
82	r->type = type;
83	r->map_func = map_func;
84	}
85
86	static void pci_config_writel(void* opaque, uint32_t addr, uint32_t val)
87	{
88	PCIBridge *s = opaque;
89	s->config_reg = val;
90	}
91
92	static uint32_t pci_config_readl(void* opaque, uint32_t addr)
93	{
94	PCIBridge *s = opaque;
95	return s->config_reg;
96	}
97
98	static void unmap_region(PCIIORegion *r)
99	{
100	if (r->addr == -1)
101	return;
102	#ifdef DEBUG_PCI
103	printf("unmap addr=%08x size=%08x\n", r->addr, r->size);
104	#endif
105	if (r->type & PCI_ADDRESS_SPACE_IO) {
106	isa_unassign_ioport(r->addr, r->size);
107	} else {
108	cpu_register_physical_memory(r->addr + pci_mem_base, r->size,
109	IO_MEM_UNASSIGNED);
110	}
111	}
112
113	static void pci_data_write(void *opaque, uint32_t addr,
114	uint32_t val, int len)
115	{
116	PCIBridge *s = opaque;
117	PCIDevice *bus, pci_dev;
118	int config_addr, reg;
119
120	#if defined(DEBUG_PCI) && 0
121	printf("pci_data_write: addr=%08x val=%08x len=%d\n",
122	s->config_reg, val, len);
123	#endif
124	if (!(s->config_reg & (1 << 31))) {
125	return;
126	}
127	if ((s->config_reg & 0x3) != 0) {
128	return;
129	}
130	bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
131	if (!bus)
132	return;
133	pci_dev = bus[(s->config_reg >> 8) & 0xff];
134	if (!pci_dev)
135	return;
136	config_addr = (s->config_reg & 0xfc) \| (addr & 3);
137
138	#if defined(DEBUG_PCI)
139	printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
140	pci_dev->name, config_addr, val, len);
141	#endif
142	if (len == 4 && (config_addr >= 0x10 && config_addr < 0x10 + 4 * 6)) {
143	PCIIORegion *r;
144	reg = (config_addr - 0x10) >> 2;
145	r = &pci_dev->io_regions[reg];
146	if (r->size == 0)
147	goto default_config;
148	if (val != 0xffffffff && val != 0) {
149	/* XXX: the memory assignment should be global to handle
150	overlaps, but it is not needed at this stage */
151	/* first unmap the old region */
152	unmap_region(r);
153	/* change the address */
154	if (r->type & PCI_ADDRESS_SPACE_IO)
155	r->addr = val & ~0x3;
156	else
157	r->addr = val & ~0xf;
158	#ifdef DEBUG_PCI
159	printf("map addr=%08x size=%08x type=%d\n",
160	r->addr, r->size, r->type);
161	#endif
162	r->map_func(pci_dev, reg, r->addr, r->size, r->type);
163	}
164	/* now compute the stored value */
165	val &= ~(r->size - 1);
166	val \|= r->type;
167	(uint32_t )(pci_dev->config + 0x10 + reg * 4) = cpu_to_le32(val);
168	} else {
169	default_config:
170	pci_dev->config_write(pci_dev, config_addr, val, len);
171	}
172	}
173
174	static uint32_t pci_data_read(void *opaque, uint32_t addr,
175	int len)
176	{
177	PCIBridge *s = opaque;
178	PCIDevice *bus, pci_dev;
179	int config_addr;
180	uint32_t val;
181
182	if (!(s->config_reg & (1 << 31)))
183	goto fail;
184	if ((s->config_reg & 0x3) != 0)
185	goto fail;
186	bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
187	if (!bus)
188	goto fail;
189	pci_dev = bus[(s->config_reg >> 8) & 0xff];
190	if (!pci_dev) {
191	fail:
192	val = 0;
193	goto the_end;
194	}
195	config_addr = (s->config_reg & 0xfc) \| (addr & 3);
196	val = pci_dev->config_read(pci_dev, config_addr, len);
197	#if defined(DEBUG_PCI)
198	printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
199	pci_dev->name, config_addr, val, len);
200	#endif
201	the_end:
202	#if defined(DEBUG_PCI) && 0
203	printf("pci_data_read: addr=%08x val=%08x len=%d\n",
204	s->config_reg, val, len);
205	#endif
206	return val;
207	}
208
209	static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
210	{
211	pci_data_write(opaque, addr, val, 1);
212	}
213
214	static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
215	{
216	pci_data_write(opaque, addr, val, 2);
217	}
218
219	static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
220	{
221	pci_data_write(opaque, addr, val, 4);
222	}
223
224	static uint32_t pci_data_readb(void* opaque, uint32_t addr)
225	{
226	return pci_data_read(opaque, addr, 1);
227	}
228
229	static uint32_t pci_data_readw(void* opaque, uint32_t addr)
230	{
231	return pci_data_read(opaque, addr, 2);
232	}
233
234	static uint32_t pci_data_readl(void* opaque, uint32_t addr)
235	{
236	return pci_data_read(opaque, addr, 4);
237	}
238
239	/* i440FX PCI bridge */
240
241	static uint32_t i440_read_config(PCIDevice *d,
242	uint32_t address, int len)
243	{
244	uint32_t val;
245	val = 0;
246	memcpy(&val, d->config + address, len);
247	return val;
248	}
249
250	static void i440_write_config(PCIDevice *d,
251	uint32_t address, uint32_t val, int len)
252	{
253	memcpy(d->config + address, &val, len);
254	}
255
256	void i440fx_init(void)
257	{
258	PCIBridge *s = &pci_bridge;
259	PCIDevice *d;
260
261	register_ioport_write(0xcf8, 4, 4, pci_config_writel, s);
262	register_ioport_read(0xcf8, 4, 4, pci_config_readl, s);
263
264	register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
265	register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
266	register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
267	register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
268	register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
269	register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
270
271	d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
272	i440_read_config, i440_write_config);
273
274	d->config[0x00] = 0x86; // vendor_id
275	d->config[0x01] = 0x80;
276	d->config[0x02] = 0x37; // device_id
277	d->config[0x03] = 0x12;
278	d->config[0x08] = 0x02; // revision
279	d->config[0x0a] = 0x04; // class_sub = pci2pci
280	d->config[0x0b] = 0x06; // class_base = PCI_bridge
281	d->config[0x0c] = 0x01; // line_size in 32 bit words
282	d->config[0x0e] = 0x01; // header_type
283	}
284
285	/* NOTE: the following should be done by the BIOS */
286
287	static uint32_t pci_bios_io_addr;
288	static uint32_t pci_bios_mem_addr;
289
290	static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
291	{
292	PCIBridge *s = &pci_bridge;
293	PCIIORegion *r;
294
295	s->config_reg = 0x80000000 \| (d->bus_num << 16) \|
296	(d->devfn << 8) \| (0x10 + region_num * 4);
297	pci_data_write(s, 0, addr, 4);
298	r = &d->io_regions[region_num];
299
300	/* enable memory mappings */
301	if (r->type & PCI_ADDRESS_SPACE_IO)
302	d->config[0x04] \|= 1;
303	else
304	d->config[0x04] \|= 2;
305	}
306
307
308	static void pci_bios_init_device(PCIDevice *d)
309	{
310	int class;
311	PCIIORegion *r;
312	uint32_t *paddr;
313	int i;
314
315	class = d->config[0x0a] \| (d->config[0x0b] << 8);
316	switch(class) {
317	case 0x0101:
318	/* IDE: we map it as in ISA mode */
319	pci_set_io_region_addr(d, 0, 0x1f0);
320	pci_set_io_region_addr(d, 1, 0x3f4);
321	pci_set_io_region_addr(d, 2, 0x170);
322	pci_set_io_region_addr(d, 3, 0x374);
323	break;
324	default:
325	/* default memory mappings */
326	for(i = 0; i < 6; i++) {
327	r = &d->io_regions[i];
328	if (r->size) {
329	if (r->type & PCI_ADDRESS_SPACE_IO)
330	paddr = &pci_bios_io_addr;
331	else
332	paddr = &pci_bios_mem_addr;
333	paddr = (paddr + r->size - 1) & ~(r->size - 1);
334	pci_set_io_region_addr(d, i, *paddr);
335	*paddr += r->size;
336	}
337	}
338	break;
339	}
340	}
341
342	/*
343	* This function initializes the PCI devices as a normal PCI BIOS
344	* would do. It is provided just in case the BIOS has no support for
345	* PCI.
346	*/
347	void pci_bios_init(void)
348	{
349	PCIBridge *s = &pci_bridge;
350	PCIDevice **bus;
351	int bus_num, devfn;
352
353	pci_bios_io_addr = 0xc000;
354	pci_bios_mem_addr = 0xf0000000;
355
356	for(bus_num = 0; bus_num < 256; bus_num++) {
357	bus = s->pci_bus[bus_num];
358	if (bus) {
359	for(devfn = 0; devfn < 256; devfn++) {
360	if (bus[devfn])
361	pci_bios_init_device(bus[devfn]);
362	}
363	}
364	}
365	}
366
367