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69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "vl.h"
25
26//#define DEBUG_PCI
27
0ac32c83
FB		 28#define PCI_VENDOR_ID 0x00 /* 16 bits */
29#define PCI_DEVICE_ID 0x02 /* 16 bits */
30#define PCI_COMMAND 0x04 /* 16 bits */
31#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33#define PCI_CLASS_DEVICE 0x0a /* Device class */
34#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36#define PCI_MIN_GNT 0x3e /* 8 bits */
37#define PCI_MAX_LAT 0x3f /* 8 bits */
38
39/* just used for simpler irq handling. */
40#define PCI_DEVICES_MAX 64
41#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
42
30468f78
FB		 43struct PCIBus {
44 int bus_num;
45 int devfn_min;
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
48 openpic_t *openpic; /* XXX: suppress */
49 PCIDevice *devices[256];
50};
69b91039 51
69b91039 52target_phys_addr_t pci_mem_base;
0ac32c83
FB		 53static int pci_irq_index;
54static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
30468f78
FB		 55static PCIBus *first_bus;
56
57static PCIBus *pci_register_bus(void)
58{
59 PCIBus *bus;
60 bus = qemu_mallocz(sizeof(PCIBus));
61 first_bus = bus;
62 return bus;
63}
69b91039 64
30ca2aab
FB		 65void generic_pci_save(QEMUFile* f, void *opaque)
66{
67 PCIDevice* s=(PCIDevice*)opaque;
68
69 qemu_put_buffer(f, s->config, 256);
70}
71
72int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
73{
74 PCIDevice* s=(PCIDevice*)opaque;
75
76 if (version_id != 1)
77 return -EINVAL;
78
79 qemu_get_buffer(f, s->config, 256);
80 return 0;
81}
82
69b91039 83/* -1 for devfn means auto assign */
30468f78
FB		 84PCIDevice *pci_register_device(PCIBus *bus, const char *name,
85 int instance_size, int devfn,
69b91039
FB		 86 PCIConfigReadFunc *config_read,
87 PCIConfigWriteFunc *config_write)
88{
30468f78 89 PCIDevice *pci_dev;
69b91039 90
0ac32c83
FB		 91 if (pci_irq_index >= PCI_DEVICES_MAX)
92 return NULL;
93
69b91039 94 if (devfn < 0) {
30468f78
FB		 95 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
96 if (!bus->devices[devfn])
69b91039
FB		 97 goto found;
98 }
99 return NULL;
100 found: ;
101 }
102 pci_dev = qemu_mallocz(instance_size);
103 if (!pci_dev)
104 return NULL;
30468f78 105 pci_dev->bus = bus;
69b91039
FB		 106 pci_dev->devfn = devfn;
107 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
0ac32c83
FB		 108
109 if (!config_read)
110 config_read = pci_default_read_config;
111 if (!config_write)
112 config_write = pci_default_write_config;
69b91039
FB		 113 pci_dev->config_read = config_read;
114 pci_dev->config_write = config_write;
0ac32c83 115 pci_dev->irq_index = pci_irq_index++;
30468f78 116 bus->devices[devfn] = pci_dev;
69b91039
FB		 117 return pci_dev;
118}
119
120void pci_register_io_region(PCIDevice *pci_dev, int region_num,
121 uint32_t size, int type,
122 PCIMapIORegionFunc *map_func)
123{
124 PCIIORegion *r;
125
8a8696a3 126 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
69b91039
FB		 127 return;
128 r = &pci_dev->io_regions[region_num];
129 r->addr = -1;
130 r->size = size;
131 r->type = type;
132 r->map_func = map_func;
133}
134
0ac32c83 135static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
69b91039 136{
30468f78 137 PCIBus *s = opaque;
69b91039
FB		 138 s->config_reg = val;
139}
140
0ac32c83 141static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
69b91039 142{
30468f78 143 PCIBus *s = opaque;
69b91039
FB		 144 return s->config_reg;
145}
146
0ac32c83
FB		 147static void pci_update_mappings(PCIDevice *d)
148{
149 PCIIORegion *r;
150 int cmd, i;
8a8696a3 151 uint32_t last_addr, new_addr, config_ofs;
0ac32c83
FB		 152
153 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
8a8696a3 154 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 155 r = &d->io_regions[i];
8a8696a3
FB		 156 if (i == PCI_ROM_SLOT) {
157 config_ofs = 0x30;
158 } else {
159 config_ofs = 0x10 + i * 4;
160 }
0ac32c83
FB		 161 if (r->size != 0) {
162 if (r->type & PCI_ADDRESS_SPACE_IO) {
163 if (cmd & PCI_COMMAND_IO) {
164 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
8a8696a3 165 config_ofs));
0ac32c83
FB		 166 new_addr = new_addr & ~(r->size - 1);
167 last_addr = new_addr + r->size - 1;
168 /* NOTE: we have only 64K ioports on PC */
169 if (last_addr <= new_addr || new_addr == 0 ||
170 last_addr >= 0x10000) {
171 new_addr = -1;
172 }
173 } else {
174 new_addr = -1;
175 }
176 } else {
177 if (cmd & PCI_COMMAND_MEMORY) {
178 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
8a8696a3
FB		 179 config_ofs));
180 /* the ROM slot has a specific enable bit */
181 if (i == PCI_ROM_SLOT && !(new_addr & 1))
182 goto no_mem_map;
0ac32c83
FB		 183 new_addr = new_addr & ~(r->size - 1);
184 last_addr = new_addr + r->size - 1;
185 /* NOTE: we do not support wrapping */
186 /* XXX: as we cannot support really dynamic
187 mappings, we handle specific values as invalid
188 mappings. */
189 if (last_addr <= new_addr || new_addr == 0 ||
190 last_addr == -1) {
191 new_addr = -1;
192 }
193 } else {
8a8696a3 194 no_mem_map:
0ac32c83
FB		 195 new_addr = -1;
196 }
197 }
198 /* now do the real mapping */
199 if (new_addr != r->addr) {
200 if (r->addr != -1) {
201 if (r->type & PCI_ADDRESS_SPACE_IO) {
202 int class;
203 /* NOTE: specific hack for IDE in PC case:
204 only one byte must be mapped. */
205 class = d->config[0x0a] | (d->config[0x0b] << 8);
206 if (class == 0x0101 && r->size == 4) {
207 isa_unassign_ioport(r->addr + 2, 1);
208 } else {
209 isa_unassign_ioport(r->addr, r->size);
210 }
211 } else {
212 cpu_register_physical_memory(r->addr + pci_mem_base,
213 r->size,
214 IO_MEM_UNASSIGNED);
215 }
216 }
217 r->addr = new_addr;
218 if (r->addr != -1) {
219 r->map_func(d, i, r->addr, r->size, r->type);
220 }
221 }
222 }
223 }
224}
225
226uint32_t pci_default_read_config(PCIDevice *d,
227 uint32_t address, int len)
69b91039 228{
0ac32c83
FB		 229 uint32_t val;
230 switch(len) {
231 case 1:
232 val = d->config[address];
233 break;
234 case 2:
235 val = le16_to_cpu(*(uint16_t *)(d->config + address));
236 break;
237 default:
238 case 4:
239 val = le32_to_cpu(*(uint32_t *)(d->config + address));
240 break;
241 }
242 return val;
243}
244
245void pci_default_write_config(PCIDevice *d,
246 uint32_t address, uint32_t val, int len)
247{
248 int can_write, i;
7bf5be70 249 uint32_t end, addr;
0ac32c83 250
8a8696a3
FB		 251 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
252 (address >= 0x30 && address < 0x34))) {
0ac32c83
FB		 253 PCIIORegion *r;
254 int reg;
255
8a8696a3
FB		 256 if ( address >= 0x30 ) {
257 reg = PCI_ROM_SLOT;
258 }else{
259 reg = (address - 0x10) >> 2;
260 }
0ac32c83
FB		 261 r = &d->io_regions[reg];
262 if (r->size == 0)
263 goto default_config;
264 /* compute the stored value */
8a8696a3
FB		 265 if (reg == PCI_ROM_SLOT) {
266 /* keep ROM enable bit */
267 val &= (~(r->size - 1)) | 1;
268 } else {
269 val &= ~(r->size - 1);
270 val |= r->type;
271 }
272 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
0ac32c83 273 pci_update_mappings(d);
69b91039 274 return;
0ac32c83
FB		 275 }
276 default_config:
277 /* not efficient, but simple */
7bf5be70 278 addr = address;
0ac32c83
FB		 279 for(i = 0; i < len; i++) {
280 /* default read/write accesses */
1f62d938 281 switch(d->config[0x0e]) {
0ac32c83 282 case 0x00:
1f62d938
FB		 283 case 0x80:
284 switch(addr) {
285 case 0x00:
286 case 0x01:
287 case 0x02:
288 case 0x03:
289 case 0x08:
290 case 0x09:
291 case 0x0a:
292 case 0x0b:
293 case 0x0e:
294 case 0x10 ... 0x27: /* base */
295 case 0x30 ... 0x33: /* rom */
296 case 0x3d:
297 can_write = 0;
298 break;
299 default:
300 can_write = 1;
301 break;
302 }
0ac32c83
FB		 303 break;
304 default:
1f62d938
FB		 305 case 0x01:
306 switch(addr) {
307 case 0x00:
308 case 0x01:
309 case 0x02:
310 case 0x03:
311 case 0x08:
312 case 0x09:
313 case 0x0a:
314 case 0x0b:
315 case 0x0e:
316 case 0x38 ... 0x3b: /* rom */
317 case 0x3d:
318 can_write = 0;
319 break;
320 default:
321 can_write = 1;
322 break;
323 }
0ac32c83
FB		 324 break;
325 }
326 if (can_write) {
7bf5be70 327 d->config[addr] = val;
0ac32c83 328 }
7bf5be70 329 addr++;
0ac32c83
FB		 330 val >>= 8;
331 }
332
333 end = address + len;
334 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
335 /* if the command register is modified, we must modify the mappings */
336 pci_update_mappings(d);
69b91039
FB		 337 }
338}
339
340static void pci_data_write(void *opaque, uint32_t addr,
341 uint32_t val, int len)
342{
30468f78
FB		 343 PCIBus *s = opaque;
344 PCIDevice *pci_dev;
345 int config_addr, bus_num;
69b91039
FB		 346
347#if defined(DEBUG_PCI) && 0
348 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
349 s->config_reg, val, len);
350#endif
351 if (!(s->config_reg & (1 << 31))) {
352 return;
353 }
354 if ((s->config_reg & 0x3) != 0) {
355 return;
356 }
30468f78
FB		 357 bus_num = (s->config_reg >> 16) & 0xff;
358 if (bus_num != 0)
69b91039 359 return;
30468f78 360 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
69b91039
FB		 361 if (!pci_dev)
362 return;
363 config_addr = (s->config_reg & 0xfc) | (addr & 3);
69b91039
FB		 364#if defined(DEBUG_PCI)
365 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
366 pci_dev->name, config_addr, val, len);
367#endif
0ac32c83 368 pci_dev->config_write(pci_dev, config_addr, val, len);
69b91039
FB		 369}
370
371static uint32_t pci_data_read(void *opaque, uint32_t addr,
372 int len)
373{
30468f78
FB		 374 PCIBus *s = opaque;
375 PCIDevice *pci_dev;
376 int config_addr, bus_num;
69b91039
FB		 377 uint32_t val;
378
379 if (!(s->config_reg & (1 << 31)))
380 goto fail;
381 if ((s->config_reg & 0x3) != 0)
382 goto fail;
30468f78
FB		 383 bus_num = (s->config_reg >> 16) & 0xff;
384 if (bus_num != 0)
69b91039 385 goto fail;
30468f78 386 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
69b91039
FB		 387 if (!pci_dev) {
388 fail:
63ce9e0a
FB		 389 switch(len) {
390 case 1:
391 val = 0xff;
392 break;
393 case 2:
394 val = 0xffff;
395 break;
396 default:
397 case 4:
398 val = 0xffffffff;
399 break;
400 }
69b91039
FB		 401 goto the_end;
402 }
403 config_addr = (s->config_reg & 0xfc) | (addr & 3);
404 val = pci_dev->config_read(pci_dev, config_addr, len);
405#if defined(DEBUG_PCI)
406 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
407 pci_dev->name, config_addr, val, len);
408#endif
409 the_end:
410#if defined(DEBUG_PCI) && 0
411 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
412 s->config_reg, val, len);
413#endif
414 return val;
415}
416
417static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
418{
419 pci_data_write(opaque, addr, val, 1);
420}
421
422static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
423{
424 pci_data_write(opaque, addr, val, 2);
425}
426
427static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
428{
429 pci_data_write(opaque, addr, val, 4);
430}
431
432static uint32_t pci_data_readb(void* opaque, uint32_t addr)
433{
434 return pci_data_read(opaque, addr, 1);
435}
436
437static uint32_t pci_data_readw(void* opaque, uint32_t addr)
438{
439 return pci_data_read(opaque, addr, 2);
440}
441
442static uint32_t pci_data_readl(void* opaque, uint32_t addr)
443{
444 return pci_data_read(opaque, addr, 4);
445}
446
447/* i440FX PCI bridge */
448
30468f78
FB		 449static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
450
451PCIBus *i440fx_init(void)
69b91039 452{
30468f78 453 PCIBus *s;
69b91039
FB		 454 PCIDevice *d;
455
30468f78
FB		 456 s = pci_register_bus();
457 s->set_irq = piix3_set_irq;
458
0ac32c83
FB		 459 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
460 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
69b91039
FB		 461
462 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
463 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
464 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
465 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
466 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
467 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
468
30468f78 469 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
0ac32c83 470 NULL, NULL);
69b91039
FB		 471
472 d->config[0x00] = 0x86; // vendor_id
473 d->config[0x01] = 0x80;
474 d->config[0x02] = 0x37; // device_id
475 d->config[0x03] = 0x12;
476 d->config[0x08] = 0x02; // revision
358c6407 477 d->config[0x0a] = 0x00; // class_sub = host2pci
69b91039 478 d->config[0x0b] = 0x06; // class_base = PCI_bridge
358c6407 479 d->config[0x0e] = 0x00; // header_type
30468f78 480 return s;
69b91039
FB		 481}
482
0ac32c83
FB		 483/* PIIX3 PCI to ISA bridge */
484
485typedef struct PIIX3State {
486 PCIDevice dev;
487} PIIX3State;
488
489PIIX3State *piix3_state;
490
30468f78
FB		 491/* return the global irq number corresponding to a given device irq
492 pin. We could also use the bus number to have a more precise
493 mapping. */
494static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
495{
496 int slot_addend;
497 slot_addend = (pci_dev->devfn >> 3);
498 return (irq_num + slot_addend) & 3;
499}
500
501static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
502{
503 int irq_index, shift, pic_irq, pic_level;
504 uint32_t *p;
505
506 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
507 irq_index = pci_dev->irq_index;
508 p = &pci_irq_levels[irq_num][irq_index >> 5];
509 shift = (irq_index & 0x1f);
510 *p = (*p & ~(1 << shift)) | (level << shift);
511
512 /* now we change the pic irq level according to the piix irq mappings */
513 pic_irq = piix3_state->dev.config[0x60 + irq_num];
514 if (pic_irq < 16) {
515 /* the pic level is the logical OR of all the PCI irqs mapped
516 to it */
517 pic_level = 0;
518#if (PCI_IRQ_WORDS == 2)
519 pic_level = ((pci_irq_levels[irq_num][0] |
520 pci_irq_levels[irq_num][1]) != 0);
521#else
522 {
523 int i;
524 pic_level = 0;
525 for(i = 0; i < PCI_IRQ_WORDS; i++) {
526 if (pci_irq_levels[irq_num][i]) {
527 pic_level = 1;
528 break;
529 }
530 }
531 }
532#endif
533 pic_set_irq(pic_irq, pic_level);
534 }
535}
536
0ac32c83
FB		 537static void piix3_reset(PIIX3State *d)
538{
539 uint8_t *pci_conf = d->dev.config;
540
541 pci_conf[0x04] = 0x07; // master, memory and I/O
542 pci_conf[0x05] = 0x00;
543 pci_conf[0x06] = 0x00;
544 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
545 pci_conf[0x4c] = 0x4d;
546 pci_conf[0x4e] = 0x03;
547 pci_conf[0x4f] = 0x00;
548 pci_conf[0x60] = 0x80;
549 pci_conf[0x69] = 0x02;
550 pci_conf[0x70] = 0x80;
551 pci_conf[0x76] = 0x0c;
552 pci_conf[0x77] = 0x0c;
553 pci_conf[0x78] = 0x02;
554 pci_conf[0x79] = 0x00;
555 pci_conf[0x80] = 0x00;
556 pci_conf[0x82] = 0x00;
557 pci_conf[0xa0] = 0x08;
558 pci_conf[0xa0] = 0x08;
559 pci_conf[0xa2] = 0x00;
560 pci_conf[0xa3] = 0x00;
561 pci_conf[0xa4] = 0x00;
562 pci_conf[0xa5] = 0x00;
563 pci_conf[0xa6] = 0x00;
564 pci_conf[0xa7] = 0x00;
565 pci_conf[0xa8] = 0x0f;
566 pci_conf[0xaa] = 0x00;
567 pci_conf[0xab] = 0x00;
568 pci_conf[0xac] = 0x00;
569 pci_conf[0xae] = 0x00;
570}
571
30468f78 572void piix3_init(PCIBus *bus)
0ac32c83
FB		 573{
574 PIIX3State *d;
575 uint8_t *pci_conf;
576
30468f78
FB		 577 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
578 -1, NULL, NULL);
30ca2aab
FB		 579 register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
580
0ac32c83
FB		 581 piix3_state = d;
582 pci_conf = d->dev.config;
583
584 pci_conf[0x00] = 0x86; // Intel
585 pci_conf[0x01] = 0x80;
586 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
587 pci_conf[0x03] = 0x70;
588 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
589 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
590 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
591
592 piix3_reset(d);
593}
594
77d4bc34
FB		 595/* PREP pci init */
596
30468f78 597static inline void set_config(PCIBus *s, target_phys_addr_t addr)
77d4bc34
FB		 598{
599 int devfn, i;
600
601 for(i = 0; i < 11; i++) {
602 if ((addr & (1 << (11 + i))) != 0)
603 break;
604 }
605 devfn = ((addr >> 8) & 7) | (i << 3);
606 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
607}
608
8a8696a3 609static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 610{
30468f78 611 PCIBus *s = opaque;
77d4bc34
FB		 612 set_config(s, addr);
613 pci_data_write(s, addr, val, 1);
614}
615
8a8696a3 616static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 617{
30468f78 618 PCIBus *s = opaque;
77d4bc34
FB		 619 set_config(s, addr);
620#ifdef TARGET_WORDS_BIGENDIAN
621 val = bswap16(val);
622#endif
623 pci_data_write(s, addr, val, 2);
624}
625
8a8696a3 626static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 627{
30468f78 628 PCIBus *s = opaque;
77d4bc34
FB		 629 set_config(s, addr);
630#ifdef TARGET_WORDS_BIGENDIAN
631 val = bswap32(val);
632#endif
633 pci_data_write(s, addr, val, 4);
634}
635
8a8696a3 636static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
77d4bc34 637{
30468f78 638 PCIBus *s = opaque;
77d4bc34
FB		 639 uint32_t val;
640 set_config(s, addr);
641 val = pci_data_read(s, addr, 1);
642 return val;
643}
644
8a8696a3 645static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
77d4bc34 646{
30468f78 647 PCIBus *s = opaque;
77d4bc34
FB		 648 uint32_t val;
649 set_config(s, addr);
650 val = pci_data_read(s, addr, 2);
651#ifdef TARGET_WORDS_BIGENDIAN
652 val = bswap16(val);
653#endif
654 return val;
655}
656
8a8696a3 657static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 658{
30468f78 659 PCIBus *s = opaque;
77d4bc34
FB		 660 uint32_t val;
661 set_config(s, addr);
662 val = pci_data_read(s, addr, 4);
663#ifdef TARGET_WORDS_BIGENDIAN
664 val = bswap32(val);
665#endif
666 return val;
667}
668
669static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
670 &PPC_PCIIO_writeb,
671 &PPC_PCIIO_writew,
672 &PPC_PCIIO_writel,
673};
674
675static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
676 &PPC_PCIIO_readb,
677 &PPC_PCIIO_readw,
678 &PPC_PCIIO_readl,
679};
680
30468f78
FB		 681static void prep_set_irq(PCIDevice *d, int irq_num, int level)
682{
683 /* XXX: we do not simulate the hardware - we rely on the BIOS to
684 set correctly for irq line field */
685 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
686}
687
688PCIBus *pci_prep_init(void)
77d4bc34 689{
30468f78 690 PCIBus *s;
77d4bc34
FB		 691 PCIDevice *d;
692 int PPC_io_memory;
693
30468f78
FB		 694 s = pci_register_bus();
695 s->set_irq = prep_set_irq;
696
8a8696a3
FB		 697 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
698 PPC_PCIIO_write, s);
77d4bc34
FB		 699 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
700
30468f78 701 d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
77d4bc34
FB		 702 NULL, NULL);
703
704 /* XXX: put correct IDs */
705 d->config[0x00] = 0x11; // vendor_id
706 d->config[0x01] = 0x10;
707 d->config[0x02] = 0x26; // device_id
708 d->config[0x03] = 0x00;
709 d->config[0x08] = 0x02; // revision
710 d->config[0x0a] = 0x04; // class_sub = pci2pci
711 d->config[0x0b] = 0x06; // class_base = PCI_bridge
712 d->config[0x0e] = 0x01; // header_type
30468f78 713 return s;
77d4bc34
FB		 714}
715
716
717/* pmac pci init */
718
30468f78 719#if 0
f2aa58c6
FB		 720/* Grackle PCI host */
721static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
722 uint32_t val)
77d4bc34 723{
30468f78 724 PCIBus *s = opaque;
77d4bc34
FB		 725#ifdef TARGET_WORDS_BIGENDIAN
726 val = bswap32(val);
727#endif
728 s->config_reg = val;
729}
730
f2aa58c6 731static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 732{
30468f78 733 PCIBus *s = opaque;
77d4bc34
FB		 734 uint32_t val;
735
736 val = s->config_reg;
737#ifdef TARGET_WORDS_BIGENDIAN
738 val = bswap32(val);
739#endif
740 return val;
741}
742
f2aa58c6
FB		 743static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
744 &pci_grackle_config_writel,
745 &pci_grackle_config_writel,
746 &pci_grackle_config_writel,
77d4bc34
FB		 747};
748
f2aa58c6
FB		 749static CPUReadMemoryFunc *pci_grackle_config_read[] = {
750 &pci_grackle_config_readl,
751 &pci_grackle_config_readl,
752 &pci_grackle_config_readl,
77d4bc34
FB		 753};
754
f2aa58c6
FB		 755static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
756 uint32_t val)
77d4bc34 757{
30468f78 758 PCIBus *s = opaque;
77d4bc34
FB		 759 pci_data_write(s, addr, val, 1);
760}
761
f2aa58c6
FB		 762static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
763 uint32_t val)
77d4bc34 764{
30468f78 765 PCIBus *s = opaque;
77d4bc34
FB		 766#ifdef TARGET_WORDS_BIGENDIAN
767 val = bswap16(val);
768#endif
769 pci_data_write(s, addr, val, 2);
770}
771
f2aa58c6
FB		 772static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
773 uint32_t val)
77d4bc34 774{
30468f78 775 PCIBus *s = opaque;
77d4bc34
FB		 776#ifdef TARGET_WORDS_BIGENDIAN
777 val = bswap32(val);
778#endif
779 pci_data_write(s, addr, val, 4);
780}
781
f2aa58c6 782static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
77d4bc34 783{
30468f78 784 PCIBus *s = opaque;
77d4bc34
FB		 785 uint32_t val;
786 val = pci_data_read(s, addr, 1);
787 return val;
788}
789
f2aa58c6 790static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
77d4bc34 791{
30468f78 792 PCIBus *s = opaque;
77d4bc34
FB		 793 uint32_t val;
794 val = pci_data_read(s, addr, 2);
795#ifdef TARGET_WORDS_BIGENDIAN
796 val = bswap16(val);
797#endif
798 return val;
799}
800
f2aa58c6
FB		 801static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
802{
30468f78 803 PCIBus *s = opaque;
f2aa58c6
FB		 804 uint32_t val;
805
806 val = pci_data_read(s, addr, 4);
807#ifdef TARGET_WORDS_BIGENDIAN
808 val = bswap32(val);
809#endif
810 return val;
811}
812
813static CPUWriteMemoryFunc *pci_grackle_write[] = {
814 &pci_grackle_writeb,
815 &pci_grackle_writew,
816 &pci_grackle_writel,
817};
818
819static CPUReadMemoryFunc *pci_grackle_read[] = {
820 &pci_grackle_readb,
821 &pci_grackle_readw,
822 &pci_grackle_readl,
823};
30468f78 824#endif
f2aa58c6
FB		 825
826/* Uninorth PCI host (for all Mac99 and newer machines */
827static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
828 uint32_t val)
829{
30468f78 830 PCIBus *s = opaque;
f2aa58c6
FB		 831 int i;
832
833#ifdef TARGET_WORDS_BIGENDIAN
834 val = bswap32(val);
835#endif
836
837 for (i = 11; i < 32; i++) {
838 if ((val & (1 << i)) != 0)
839 break;
840 }
841#if 0
842 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
843#else
844 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
845#endif
846}
847
848static uint32_t pci_unin_main_config_readl (void *opaque,
849 target_phys_addr_t addr)
850{
30468f78 851 PCIBus *s = opaque;
f2aa58c6
FB		 852 uint32_t val;
853 int devfn;
854
855 devfn = (s->config_reg >> 8) & 0xFF;
856 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
857#ifdef TARGET_WORDS_BIGENDIAN
858 val = bswap32(val);
859#endif
860
861 return val;
862}
863
864static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
865 &pci_unin_main_config_writel,
866 &pci_unin_main_config_writel,
867 &pci_unin_main_config_writel,
868};
869
870static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
871 &pci_unin_main_config_readl,
872 &pci_unin_main_config_readl,
873 &pci_unin_main_config_readl,
874};
875
876static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
877 uint32_t val)
878{
30468f78 879 PCIBus *s = opaque;
f2aa58c6
FB		 880 pci_data_write(s, addr & 7, val, 1);
881}
882
883static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
884 uint32_t val)
885{
30468f78 886 PCIBus *s = opaque;
f2aa58c6
FB		 887#ifdef TARGET_WORDS_BIGENDIAN
888 val = bswap16(val);
889#endif
890 pci_data_write(s, addr & 7, val, 2);
891}
892
893static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
894 uint32_t val)
895{
30468f78 896 PCIBus *s = opaque;
f2aa58c6
FB		 897#ifdef TARGET_WORDS_BIGENDIAN
898 val = bswap32(val);
899#endif
900 pci_data_write(s, addr & 7, val, 4);
901}
902
903static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
904{
30468f78 905 PCIBus *s = opaque;
f2aa58c6
FB		 906 uint32_t val;
907
908 val = pci_data_read(s, addr & 7, 1);
909
910 return val;
911}
912
913static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
914{
30468f78 915 PCIBus *s = opaque;
f2aa58c6
FB		 916 uint32_t val;
917
918 val = pci_data_read(s, addr & 7, 2);
919#ifdef TARGET_WORDS_BIGENDIAN
920 val = bswap16(val);
921#endif
922
923 return val;
924}
925
926static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 927{
30468f78 928 PCIBus *s = opaque;
77d4bc34
FB		 929 uint32_t val;
930
931 val = pci_data_read(s, addr, 4);
932#ifdef TARGET_WORDS_BIGENDIAN
933 val = bswap32(val);
934#endif
f2aa58c6
FB		 935
936 return val;
937}
938
939static CPUWriteMemoryFunc *pci_unin_main_write[] = {
940 &pci_unin_main_writeb,
941 &pci_unin_main_writew,
942 &pci_unin_main_writel,
943};
944
945static CPUReadMemoryFunc *pci_unin_main_read[] = {
946 &pci_unin_main_readb,
947 &pci_unin_main_readw,
948 &pci_unin_main_readl,
949};
950
30468f78
FB		 951#if 0
952
f2aa58c6
FB		 953static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
954 uint32_t val)
955{
30468f78 956 PCIBus *s = opaque;
f2aa58c6
FB		 957
958#ifdef TARGET_WORDS_BIGENDIAN
959 val = bswap32(val);
960#endif
961 s->config_reg = 0x80000000 | (val & ~0x00000001);
962}
963
964static uint32_t pci_unin_config_readl (void *opaque,
965 target_phys_addr_t addr)
966{
30468f78 967 PCIBus *s = opaque;
f2aa58c6
FB		 968 uint32_t val;
969
970 val = (s->config_reg | 0x00000001) & ~0x80000000;
971#ifdef TARGET_WORDS_BIGENDIAN
972 val = bswap32(val);
973#endif
974
975 return val;
976}
977
978static CPUWriteMemoryFunc *pci_unin_config_write[] = {
979 &pci_unin_config_writel,
980 &pci_unin_config_writel,
981 &pci_unin_config_writel,
982};
983
984static CPUReadMemoryFunc *pci_unin_config_read[] = {
985 &pci_unin_config_readl,
986 &pci_unin_config_readl,
987 &pci_unin_config_readl,
988};
989
990static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
991 uint32_t val)
992{
30468f78 993 PCIBus *s = opaque;
f2aa58c6
FB		 994 pci_data_write(s, addr & 3, val, 1);
995}
996
997static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
998 uint32_t val)
999{
30468f78 1000 PCIBus *s = opaque;
f2aa58c6
FB		 1001#ifdef TARGET_WORDS_BIGENDIAN
1002 val = bswap16(val);
1003#endif
1004 pci_data_write(s, addr & 3, val, 2);
1005}
1006
1007static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
1008 uint32_t val)
1009{
30468f78 1010 PCIBus *s = opaque;
f2aa58c6
FB		 1011#ifdef TARGET_WORDS_BIGENDIAN
1012 val = bswap32(val);
1013#endif
1014 pci_data_write(s, addr & 3, val, 4);
1015}
1016
1017static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
1018{
30468f78 1019 PCIBus *s = opaque;
f2aa58c6
FB		 1020 uint32_t val;
1021
1022 val = pci_data_read(s, addr & 3, 1);
1023
1024 return val;
1025}
1026
1027static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1028{
30468f78 1029 PCIBus *s = opaque;
f2aa58c6
FB		 1030 uint32_t val;
1031
1032 val = pci_data_read(s, addr & 3, 2);
1033#ifdef TARGET_WORDS_BIGENDIAN
1034 val = bswap16(val);
1035#endif
1036
1037 return val;
1038}
1039
1040static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1041{
30468f78 1042 PCIBus *s = opaque;
f2aa58c6
FB		 1043 uint32_t val;
1044
1045 val = pci_data_read(s, addr & 3, 4);
1046#ifdef TARGET_WORDS_BIGENDIAN
1047 val = bswap32(val);
1048#endif
1049
77d4bc34
FB		 1050 return val;
1051}
1052
f2aa58c6
FB		 1053static CPUWriteMemoryFunc *pci_unin_write[] = {
1054 &pci_unin_writeb,
1055 &pci_unin_writew,
1056 &pci_unin_writel,
77d4bc34
FB		 1057};
1058
f2aa58c6
FB		 1059static CPUReadMemoryFunc *pci_unin_read[] = {
1060 &pci_unin_readb,
1061 &pci_unin_readw,
1062 &pci_unin_readl,
77d4bc34 1063};
30468f78
FB		 1064#endif
1065
1066static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
1067{
1068 openpic_t *openpic;
1069 /* XXX: we do not simulate the hardware - we rely on the BIOS to
1070 set correctly for irq line field */
1071 openpic = d->bus->openpic;
1072#ifdef TARGET_PPC
1073 if (openpic)
1074 openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
1075#endif
1076}
1077
1078void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
1079{
1080 bus->openpic = openpic;
1081}
77d4bc34 1082
30468f78 1083PCIBus *pci_pmac_init(void)
77d4bc34 1084{
30468f78 1085 PCIBus *s;
77d4bc34
FB		 1086 PCIDevice *d;
1087 int pci_mem_config, pci_mem_data;
1088
f2aa58c6
FB		 1089 /* Use values found on a real PowerMac */
1090 /* Uninorth main bus */
30468f78
FB		 1091 s = pci_register_bus();
1092 s->set_irq = pmac_set_irq;
1093
f2aa58c6
FB		 1094 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1095 pci_unin_main_config_write, s);
1096 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1097 pci_unin_main_write, s);
1098 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1099 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
30468f78
FB		 1100 s->devfn_min = 11 << 3;
1101 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1102 11 << 3, NULL, NULL);
f2aa58c6
FB		 1103 d->config[0x00] = 0x6b; // vendor_id : Apple
1104 d->config[0x01] = 0x10;
1105 d->config[0x02] = 0x1F; // device_id
1106 d->config[0x03] = 0x00;
1107 d->config[0x08] = 0x00; // revision
1108 d->config[0x0A] = 0x00; // class_sub = pci host
1109 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1110 d->config[0x0C] = 0x08; // cache_line_size
1111 d->config[0x0D] = 0x10; // latency_timer
1112 d->config[0x0E] = 0x00; // header_type
1113 d->config[0x34] = 0x00; // capabilities_pointer
1114
1115#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1116 /* pci-to-pci bridge */
1117 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1118 NULL, NULL);
1119 d->config[0x00] = 0x11; // vendor_id : TI
1120 d->config[0x01] = 0x10;
1121 d->config[0x02] = 0x26; // device_id
1122 d->config[0x03] = 0x00;
1123 d->config[0x08] = 0x05; // revision
1124 d->config[0x0A] = 0x04; // class_sub = pci2pci
1125 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1126 d->config[0x0C] = 0x08; // cache_line_size
1127 d->config[0x0D] = 0x20; // latency_timer
1128 d->config[0x0E] = 0x01; // header_type
1129
1130 d->config[0x18] = 0x01; // primary_bus
1131 d->config[0x19] = 0x02; // secondary_bus
1132 d->config[0x1A] = 0x02; // subordinate_bus
1133 d->config[0x1B] = 0x20; // secondary_latency_timer
1134 d->config[0x1C] = 0x11; // io_base
1135 d->config[0x1D] = 0x01; // io_limit
1136 d->config[0x20] = 0x00; // memory_base
1137 d->config[0x21] = 0x80;
1138 d->config[0x22] = 0x00; // memory_limit
1139 d->config[0x23] = 0x80;
1140 d->config[0x24] = 0x01; // prefetchable_memory_base
1141 d->config[0x25] = 0x80;
1142 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1143 d->config[0x27] = 0x7F;
1144 // d->config[0x34] = 0xdc // capabilities_pointer
1145#endif
1146#if 0 // XXX: not needed for now
1147 /* Uninorth AGP bus */
1148 s = &pci_bridge[1];
1149 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1150 pci_unin_config_write, s);
1151 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1152 pci_unin_write, s);
1153 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1154 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1155
1156 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1157 NULL, NULL);
1158 d->config[0x00] = 0x6b; // vendor_id : Apple
1159 d->config[0x01] = 0x10;
1160 d->config[0x02] = 0x20; // device_id
1161 d->config[0x03] = 0x00;
1162 d->config[0x08] = 0x00; // revision
1163 d->config[0x0A] = 0x00; // class_sub = pci host
1164 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1165 d->config[0x0C] = 0x08; // cache_line_size
1166 d->config[0x0D] = 0x10; // latency_timer
1167 d->config[0x0E] = 0x00; // header_type
1168 // d->config[0x34] = 0x80; // capabilities_pointer
1169#endif
77d4bc34 1170
f2aa58c6
FB		 1171#if 0 // XXX: not needed for now
1172 /* Uninorth internal bus */
1173 s = &pci_bridge[2];
1174 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1175 pci_unin_config_write, s);
1176 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1177 pci_unin_write, s);
1178 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1179 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1180
1181 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1182 3, 11 << 3, NULL, NULL);
1183 d->config[0x00] = 0x6b; // vendor_id : Apple
1184 d->config[0x01] = 0x10;
1185 d->config[0x02] = 0x1E; // device_id
1186 d->config[0x03] = 0x00;
1187 d->config[0x08] = 0x00; // revision
1188 d->config[0x0A] = 0x00; // class_sub = pci host
1189 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1190 d->config[0x0C] = 0x08; // cache_line_size
1191 d->config[0x0D] = 0x10; // latency_timer
1192 d->config[0x0E] = 0x00; // header_type
1193 d->config[0x34] = 0x00; // capabilities_pointer
1194#endif
1195
1196#if 0 // Grackle ?
77d4bc34
FB		 1197 /* same values as PearPC - check this */
1198 d->config[0x00] = 0x11; // vendor_id
1199 d->config[0x01] = 0x10;
1200 d->config[0x02] = 0x26; // device_id
1201 d->config[0x03] = 0x00;
1202 d->config[0x08] = 0x02; // revision
1203 d->config[0x0a] = 0x04; // class_sub = pci2pci
1204 d->config[0x0b] = 0x06; // class_base = PCI_bridge
1205 d->config[0x0e] = 0x01; // header_type
1206
1207 d->config[0x18] = 0x0; // primary_bus
1208 d->config[0x19] = 0x1; // secondary_bus
1209 d->config[0x1a] = 0x1; // subordinate_bus
1210 d->config[0x1c] = 0x10; // io_base
1211 d->config[0x1d] = 0x20; // io_limit
1212
1213 d->config[0x20] = 0x80; // memory_base
1214 d->config[0x21] = 0x80;
1215 d->config[0x22] = 0x90; // memory_limit
1216 d->config[0x23] = 0x80;
1217
1218 d->config[0x24] = 0x00; // prefetchable_memory_base
1219 d->config[0x25] = 0x84;
1220 d->config[0x26] = 0x00; // prefetchable_memory_limit
1221 d->config[0x27] = 0x85;
f2aa58c6 1222#endif
30468f78 1223 return s;
77d4bc34
FB		 1224}
1225
0ac32c83
FB		 1226/***********************************************************/
1227/* generic PCI irq support */
1228
0ac32c83 1229/* 0 <= irq_num <= 3. level must be 0 or 1 */
77d4bc34
FB		 1230void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1231{
30468f78
FB		 1232 PCIBus *bus = pci_dev->bus;
1233 bus->set_irq(pci_dev, irq_num, level);
77d4bc34 1234}
0ac32c83
FB		 1235
1236/***********************************************************/
1237/* monitor info on PCI */
1238
1239static void pci_info_device(PCIDevice *d)
1240{
1241 int i, class;
1242 PCIIORegion *r;
1243
8e3a9fd2 1244 term_printf(" Bus %2d, device %3d, function %d:\n",
30468f78 1245 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
0ac32c83 1246 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
8e3a9fd2 1247 term_printf(" ");
0ac32c83
FB		 1248 switch(class) {
1249 case 0x0101:
8e3a9fd2 1250 term_printf("IDE controller");
0ac32c83
FB		 1251 break;
1252 case 0x0200:
8e3a9fd2 1253 term_printf("Ethernet controller");
0ac32c83
FB		 1254 break;
1255 case 0x0300:
8e3a9fd2 1256 term_printf("VGA controller");
0ac32c83
FB		 1257 break;
1258 default:
8e3a9fd2 1259 term_printf("Class %04x", class);
0ac32c83
FB		 1260 break;
1261 }
8e3a9fd2 1262 term_printf(": PCI device %04x:%04x\n",
0ac32c83
FB		 1263 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1264 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1265
1266 if (d->config[PCI_INTERRUPT_PIN] != 0) {
8e3a9fd2 1267 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
0ac32c83 1268 }
8a8696a3 1269 for(i = 0;i < PCI_NUM_REGIONS; i++) {
0ac32c83
FB		 1270 r = &d->io_regions[i];
1271 if (r->size != 0) {
8e3a9fd2 1272 term_printf(" BAR%d: ", i);
0ac32c83 1273 if (r->type & PCI_ADDRESS_SPACE_IO) {
8e3a9fd2 1274 term_printf("I/O at 0x%04x [0x%04x].\n",
0ac32c83
FB		 1275 r->addr, r->addr + r->size - 1);
1276 } else {
8e3a9fd2 1277 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
0ac32c83
FB		 1278 r->addr, r->addr + r->size - 1);
1279 }
1280 }
1281 }
1282}
1283
1284void pci_info(void)
1285{
30468f78
FB		 1286 PCIBus *bus = first_bus;
1287 PCIDevice *d;
1288 int devfn;
0ac32c83 1289
30468f78
FB		 1290 if (bus) {
1291 for(devfn = 0; devfn < 256; devfn++) {
1292 d = bus->devices[devfn];
1293 if (d)
1294 pci_info_device(d);
0ac32c83
FB		 1295 }
1296 }
1297}
1298
1299/***********************************************************/
1300/* XXX: the following should be moved to the PC BIOS */
1301
30468f78 1302static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
0ac32c83
FB		 1303{
1304 return cpu_inb(cpu_single_env, addr);
1305}
1306
1307static void isa_outb(uint32_t val, uint32_t addr)
1308{
1309 cpu_outb(cpu_single_env, addr, val);
1310}
1311
30468f78 1312static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
0ac32c83
FB		 1313{
1314 return cpu_inw(cpu_single_env, addr);
1315}
1316
30468f78 1317static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
0ac32c83
FB		 1318{
1319 cpu_outw(cpu_single_env, addr, val);
1320}
1321
30468f78 1322static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
0ac32c83
FB		 1323{
1324 return cpu_inl(cpu_single_env, addr);
1325}
1326
30468f78 1327static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
0ac32c83
FB		 1328{
1329 cpu_outl(cpu_single_env, addr, val);
1330}
1331
1332static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1333{
30468f78
FB		 1334 PCIBus *s = d->bus;
1335 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1336 (d->devfn << 8) | addr;
1337 pci_data_write(s, 0, val, 4);
1338}
1339
1340static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1341{
30468f78
FB		 1342 PCIBus *s = d->bus;
1343 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1344 (d->devfn << 8) | (addr & ~3);
1345 pci_data_write(s, addr & 3, val, 2);
1346}
1347
1348static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1349{
30468f78
FB		 1350 PCIBus *s = d->bus;
1351 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1352 (d->devfn << 8) | (addr & ~3);
1353 pci_data_write(s, addr & 3, val, 1);
1354}
1355
30468f78 1356static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
0ac32c83 1357{
30468f78
FB		 1358 PCIBus *s = d->bus;
1359 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1360 (d->devfn << 8) | addr;
1361 return pci_data_read(s, 0, 4);
1362}
1363
1364static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1365{
30468f78
FB		 1366 PCIBus *s = d->bus;
1367 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1368 (d->devfn << 8) | (addr & ~3);
1369 return pci_data_read(s, addr & 3, 2);
1370}
1371
1372static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1373{
30468f78
FB		 1374 PCIBus *s = d->bus;
1375 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1376 (d->devfn << 8) | (addr & ~3);
1377 return pci_data_read(s, addr & 3, 1);
1378}
69b91039
FB		 1379
1380static uint32_t pci_bios_io_addr;
1381static uint32_t pci_bios_mem_addr;
0ac32c83
FB		 1382/* host irqs corresponding to PCI irqs A-D */
1383static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
69b91039
FB		 1384
1385static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1386{
69b91039 1387 PCIIORegion *r;
0ac32c83 1388 uint16_t cmd;
8a8696a3
FB		 1389 uint32_t ofs;
1390
1391 if ( region_num == PCI_ROM_SLOT ) {
1392 ofs = 0x30;
1393 }else{
1394 ofs = 0x10 + region_num * 4;
1395 }
69b91039 1396
8a8696a3 1397 pci_config_writel(d, ofs, addr);
69b91039
FB		 1398 r = &d->io_regions[region_num];
1399
1400 /* enable memory mappings */
0ac32c83 1401 cmd = pci_config_readw(d, PCI_COMMAND);
8a8696a3
FB		 1402 if ( region_num == PCI_ROM_SLOT )
1403 cmd |= 2;
1404 else if (r->type & PCI_ADDRESS_SPACE_IO)
0ac32c83 1405 cmd |= 1;
69b91039 1406 else
0ac32c83
FB		 1407 cmd |= 2;
1408 pci_config_writew(d, PCI_COMMAND, cmd);
69b91039
FB		 1409}
1410
69b91039
FB		 1411static void pci_bios_init_device(PCIDevice *d)
1412{
1413 int class;
1414 PCIIORegion *r;
1415 uint32_t *paddr;
63ce9e0a 1416 int i, pin, pic_irq, vendor_id, device_id;
69b91039 1417
63ce9e0a 1418 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1f62d938
FB		 1419 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1420 device_id = pci_config_readw(d, PCI_DEVICE_ID);
69b91039
FB		 1421 switch(class) {
1422 case 0x0101:
63ce9e0a
FB		 1423 if (vendor_id == 0x8086 && device_id == 0x7010) {
1424 /* PIIX3 IDE */
63ce9e0a 1425 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
7f647cf6 1426 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
d187d4b2 1427 goto default_map;
63ce9e0a
FB		 1428 } else {
1429 /* IDE: we map it as in ISA mode */
1430 pci_set_io_region_addr(d, 0, 0x1f0);
1431 pci_set_io_region_addr(d, 1, 0x3f4);
1432 pci_set_io_region_addr(d, 2, 0x170);
1433 pci_set_io_region_addr(d, 3, 0x374);
1434 }
69b91039 1435 break;
0ac32c83 1436 case 0x0300:
4c7634bc
FB		 1437 if (vendor_id != 0x1234)
1438 goto default_map;
0ac32c83
FB		 1439 /* VGA: map frame buffer to default Bochs VBE address */
1440 pci_set_io_region_addr(d, 0, 0xE0000000);
1441 break;
f2aa58c6
FB		 1442 case 0x0800:
1443 /* PIC */
1444 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1445 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1446 if (vendor_id == 0x1014) {
1447 /* IBM */
1448 if (device_id == 0x0046 || device_id == 0xFFFF) {
1449 /* MPIC & MPIC2 */
1450 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1451 }
1452 }
1453 break;
1f62d938 1454 case 0xff00:
f2aa58c6
FB		 1455 if (vendor_id == 0x0106b &&
1456 (device_id == 0x0017 || device_id == 0x0022)) {
1f62d938
FB		 1457 /* macio bridge */
1458 pci_set_io_region_addr(d, 0, 0x80800000);
1459 }
1460 break;
69b91039 1461 default:
4c7634bc 1462 default_map:
69b91039 1463 /* default memory mappings */
8a8696a3 1464 for(i = 0; i < PCI_NUM_REGIONS; i++) {
69b91039
FB		 1465 r = &d->io_regions[i];
1466 if (r->size) {
1467 if (r->type & PCI_ADDRESS_SPACE_IO)
1468 paddr = &pci_bios_io_addr;
1469 else
1470 paddr = &pci_bios_mem_addr;
1471 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1472 pci_set_io_region_addr(d, i, *paddr);
1473 *paddr += r->size;
1474 }
1475 }
1476 break;
1477 }
0ac32c83
FB		 1478
1479 /* map the interrupt */
1480 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1481 if (pin != 0) {
1482 pin = pci_slot_get_pirq(d, pin - 1);
1483 pic_irq = pci_irqs[pin];
1484 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1485 }
69b91039
FB		 1486}
1487
1488/*
1489 * This function initializes the PCI devices as a normal PCI BIOS
1490 * would do. It is provided just in case the BIOS has no support for
1491 * PCI.
1492 */
1493void pci_bios_init(void)
1494{
30468f78
FB		 1495 PCIBus *bus;
1496 PCIDevice *d;
1497 int devfn, i, irq;
0ac32c83 1498 uint8_t elcr[2];
69b91039
FB		 1499
1500 pci_bios_io_addr = 0xc000;
1501 pci_bios_mem_addr = 0xf0000000;
1502
0ac32c83
FB		 1503 /* activate IRQ mappings */
1504 elcr[0] = 0x00;
1505 elcr[1] = 0x00;
1506 for(i = 0; i < 4; i++) {
1507 irq = pci_irqs[i];
1508 /* set to trigger level */
1509 elcr[irq >> 3] |= (1 << (irq & 7));
1510 /* activate irq remapping in PIIX */
1511 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1512 }
1513 isa_outb(elcr[0], 0x4d0);
1514 isa_outb(elcr[1], 0x4d1);
1515
30468f78
FB		 1516 bus = first_bus;
1517 if (bus) {
1518 for(devfn = 0; devfn < 256; devfn++) {
1519 d = bus->devices[devfn];
1520 if (d)
1521 pci_bios_init_device(d);
77d4bc34
FB		 1522 }
1523 }
1524}
Qemu copy for testing