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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
69b91039 FB |
29 | |
30 | //#define DEBUG_PCI | |
d8d2e079 IY |
31 | #ifdef DEBUG_PCI |
32 | # define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__) | |
33 | #else | |
34 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
35 | #endif | |
69b91039 | 36 | |
30468f78 | 37 | struct PCIBus { |
02e2da45 | 38 | BusState qbus; |
30468f78 FB |
39 | int bus_num; |
40 | int devfn_min; | |
502a5395 | 41 | pci_set_irq_fn set_irq; |
d2b59317 | 42 | pci_map_irq_fn map_irq; |
30468f78 | 43 | uint32_t config_reg; /* XXX: suppress */ |
384d8876 FB |
44 | /* low level pic */ |
45 | SetIRQFunc *low_set_irq; | |
d537cf6c | 46 | qemu_irq *irq_opaque; |
30468f78 | 47 | PCIDevice *devices[256]; |
80b3ada7 PB |
48 | PCIDevice *parent_dev; |
49 | PCIBus *next; | |
d2b59317 PB |
50 | /* The bus IRQ state is the logical OR of the connected devices. |
51 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 52 | int nirq; |
10c4c98a GH |
53 | int *irq_count; |
54 | }; | |
55 | ||
56 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
57 | ||
58 | static struct BusInfo pci_bus_info = { | |
59 | .name = "PCI", | |
60 | .size = sizeof(PCIBus), | |
61 | .print_dev = pcibus_dev_print, | |
ee6847d1 GH |
62 | .props = (Property[]) { |
63 | { | |
a6307b08 GH |
64 | .name = "addr", |
65 | .info = &qdev_prop_pci_devfn, | |
ee6847d1 GH |
66 | .offset = offsetof(PCIDevice, devfn), |
67 | .defval = (uint32_t[]) { -1 }, | |
68 | }, | |
69 | {/* end of list */} | |
70 | } | |
30468f78 | 71 | }; |
69b91039 | 72 | |
1941d19c | 73 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 74 | static void pci_set_irq(void *opaque, int irq_num, int level); |
1941d19c | 75 | |
69b91039 | 76 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
77 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
78 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
30468f78 FB |
79 | static PCIBus *first_bus; |
80 | ||
52fc1d83 AZ |
81 | static void pcibus_save(QEMUFile *f, void *opaque) |
82 | { | |
83 | PCIBus *bus = (PCIBus *)opaque; | |
84 | int i; | |
85 | ||
86 | qemu_put_be32(f, bus->nirq); | |
87 | for (i = 0; i < bus->nirq; i++) | |
88 | qemu_put_be32(f, bus->irq_count[i]); | |
89 | } | |
90 | ||
91 | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) | |
92 | { | |
93 | PCIBus *bus = (PCIBus *)opaque; | |
94 | int i, nirq; | |
95 | ||
96 | if (version_id != 1) | |
97 | return -EINVAL; | |
98 | ||
99 | nirq = qemu_get_be32(f); | |
100 | if (bus->nirq != nirq) { | |
101 | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n", | |
102 | nirq, bus->nirq); | |
103 | return -EINVAL; | |
104 | } | |
105 | ||
106 | for (i = 0; i < nirq; i++) | |
107 | bus->irq_count[i] = qemu_get_be32(f); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
6eaa6847 GN |
112 | static void pci_bus_reset(void *opaque) |
113 | { | |
114 | PCIBus *bus = (PCIBus *)opaque; | |
115 | int i; | |
116 | ||
117 | for (i = 0; i < bus->nirq; i++) { | |
118 | bus->irq_count[i] = 0; | |
119 | } | |
120 | for (i = 0; i < 256; i++) { | |
121 | if (bus->devices[i]) | |
122 | memset(bus->devices[i]->irq_state, 0, | |
123 | sizeof(bus->devices[i]->irq_state)); | |
124 | } | |
125 | } | |
126 | ||
02e2da45 PB |
127 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
128 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
d537cf6c | 129 | qemu_irq *pic, int devfn_min, int nirq) |
30468f78 FB |
130 | { |
131 | PCIBus *bus; | |
52fc1d83 AZ |
132 | static int nbus = 0; |
133 | ||
10c4c98a | 134 | bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name)); |
502a5395 | 135 | bus->set_irq = set_irq; |
d2b59317 | 136 | bus->map_irq = map_irq; |
502a5395 PB |
137 | bus->irq_opaque = pic; |
138 | bus->devfn_min = devfn_min; | |
52fc1d83 | 139 | bus->nirq = nirq; |
616cbc78 | 140 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
425c608c | 141 | bus->next = first_bus; |
30468f78 | 142 | first_bus = bus; |
52fc1d83 | 143 | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
a08d4367 | 144 | qemu_register_reset(pci_bus_reset, bus); |
30468f78 FB |
145 | return bus; |
146 | } | |
69b91039 | 147 | |
72f44c8c BS |
148 | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, |
149 | pci_map_irq_fn map_irq, | |
150 | const char *name) | |
80b3ada7 PB |
151 | { |
152 | PCIBus *bus; | |
16eaedf2 | 153 | |
72f44c8c | 154 | bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name)); |
80b3ada7 PB |
155 | bus->map_irq = map_irq; |
156 | bus->parent_dev = dev; | |
157 | bus->next = dev->bus->next; | |
158 | dev->bus->next = bus; | |
159 | return bus; | |
160 | } | |
161 | ||
502a5395 PB |
162 | int pci_bus_num(PCIBus *s) |
163 | { | |
164 | return s->bus_num; | |
165 | } | |
166 | ||
1941d19c | 167 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
30ca2aab | 168 | { |
52fc1d83 AZ |
169 | int i; |
170 | ||
171 | qemu_put_be32(f, 2); /* PCI device version */ | |
30ca2aab | 172 | qemu_put_buffer(f, s->config, 256); |
52fc1d83 AZ |
173 | for (i = 0; i < 4; i++) |
174 | qemu_put_be32(f, s->irq_state[i]); | |
30ca2aab FB |
175 | } |
176 | ||
1941d19c | 177 | int pci_device_load(PCIDevice *s, QEMUFile *f) |
30ca2aab | 178 | { |
bd4b65ee | 179 | uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
1941d19c | 180 | uint32_t version_id; |
52fc1d83 AZ |
181 | int i; |
182 | ||
1941d19c | 183 | version_id = qemu_get_be32(f); |
52fc1d83 | 184 | if (version_id > 2) |
30ca2aab | 185 | return -EINVAL; |
bd4b65ee MT |
186 | qemu_get_buffer(f, config, sizeof config); |
187 | for (i = 0; i < sizeof config; ++i) | |
188 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) | |
189 | return -EINVAL; | |
190 | memcpy(s->config, config, sizeof config); | |
191 | ||
1941d19c | 192 | pci_update_mappings(s); |
52fc1d83 AZ |
193 | |
194 | if (version_id >= 2) | |
195 | for (i = 0; i < 4; i ++) | |
196 | s->irq_state[i] = qemu_get_be32(f); | |
30ca2aab FB |
197 | return 0; |
198 | } | |
199 | ||
d350d97d AL |
200 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
201 | { | |
202 | uint16_t *id; | |
203 | ||
204 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
205 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
206 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
207 | return 0; | |
208 | } | |
209 | ||
880345c4 AL |
210 | /* |
211 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
212 | */ | |
213 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
214 | { | |
215 | const char *p; | |
216 | char *e; | |
217 | unsigned long val; | |
218 | unsigned long dom = 0, bus = 0; | |
219 | unsigned slot = 0; | |
220 | ||
221 | p = addr; | |
222 | val = strtoul(p, &e, 16); | |
223 | if (e == p) | |
224 | return -1; | |
225 | if (*e == ':') { | |
226 | bus = val; | |
227 | p = e + 1; | |
228 | val = strtoul(p, &e, 16); | |
229 | if (e == p) | |
230 | return -1; | |
231 | if (*e == ':') { | |
232 | dom = bus; | |
233 | bus = val; | |
234 | p = e + 1; | |
235 | val = strtoul(p, &e, 16); | |
236 | if (e == p) | |
237 | return -1; | |
238 | } | |
239 | } | |
240 | ||
241 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
242 | return -1; | |
243 | ||
244 | slot = val; | |
245 | ||
246 | if (*e) | |
247 | return -1; | |
248 | ||
249 | /* Note: QEMU doesn't implement domains other than 0 */ | |
250 | if (dom != 0 || pci_find_bus(bus) == NULL) | |
251 | return -1; | |
252 | ||
253 | *domp = dom; | |
254 | *busp = bus; | |
255 | *slotp = slot; | |
256 | return 0; | |
257 | } | |
258 | ||
e9283f8b JK |
259 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
260 | unsigned *slotp) | |
880345c4 | 261 | { |
e9283f8b JK |
262 | /* strip legacy tag */ |
263 | if (!strncmp(addr, "pci_addr=", 9)) { | |
264 | addr += 9; | |
265 | } | |
266 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
267 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 268 | return -1; |
e9283f8b JK |
269 | } |
270 | return 0; | |
880345c4 AL |
271 | } |
272 | ||
5607c388 MA |
273 | static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
274 | { | |
275 | int dom, bus; | |
276 | unsigned slot; | |
277 | ||
278 | if (!devaddr) { | |
279 | *devfnp = -1; | |
280 | return pci_find_bus(0); | |
281 | } | |
282 | ||
283 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
284 | return NULL; | |
285 | } | |
286 | ||
287 | *devfnp = slot << 3; | |
288 | return pci_find_bus(bus); | |
289 | } | |
290 | ||
bd4b65ee MT |
291 | static void pci_init_cmask(PCIDevice *dev) |
292 | { | |
293 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
294 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
295 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
296 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
297 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
298 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
299 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
300 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
301 | } | |
302 | ||
b7ee1603 MT |
303 | static void pci_init_wmask(PCIDevice *dev) |
304 | { | |
305 | int i; | |
306 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; | |
307 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
308 | dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
309 | | PCI_COMMAND_MASTER; | |
310 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
311 | dev->wmask[i] = 0xff; | |
312 | } | |
313 | ||
69b91039 | 314 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
315 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
316 | const char *name, int devfn, | |
317 | PCIConfigReadFunc *config_read, | |
318 | PCIConfigWriteFunc *config_write) | |
69b91039 | 319 | { |
69b91039 | 320 | if (devfn < 0) { |
30468f78 FB |
321 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
322 | if (!bus->devices[devfn]) | |
69b91039 FB |
323 | goto found; |
324 | } | |
325 | return NULL; | |
326 | found: ; | |
07b7d053 MA |
327 | } else if (bus->devices[devfn]) { |
328 | return NULL; | |
69b91039 | 329 | } |
30468f78 | 330 | pci_dev->bus = bus; |
69b91039 FB |
331 | pci_dev->devfn = devfn; |
332 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d2b59317 | 333 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
d350d97d | 334 | pci_set_default_subsystem_id(pci_dev); |
bd4b65ee | 335 | pci_init_cmask(pci_dev); |
b7ee1603 | 336 | pci_init_wmask(pci_dev); |
0ac32c83 FB |
337 | |
338 | if (!config_read) | |
339 | config_read = pci_default_read_config; | |
340 | if (!config_write) | |
341 | config_write = pci_default_write_config; | |
69b91039 FB |
342 | pci_dev->config_read = config_read; |
343 | pci_dev->config_write = config_write; | |
30468f78 | 344 | bus->devices[devfn] = pci_dev; |
d537cf6c | 345 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); |
69b91039 FB |
346 | return pci_dev; |
347 | } | |
348 | ||
6b1b92d3 PB |
349 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
350 | int instance_size, int devfn, | |
351 | PCIConfigReadFunc *config_read, | |
352 | PCIConfigWriteFunc *config_write) | |
353 | { | |
354 | PCIDevice *pci_dev; | |
355 | ||
356 | pci_dev = qemu_mallocz(instance_size); | |
357 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
358 | config_read, config_write); | |
359 | return pci_dev; | |
360 | } | |
5851e08c AL |
361 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
362 | { | |
363 | return addr + pci_mem_base; | |
364 | } | |
365 | ||
366 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
367 | { | |
368 | PCIIORegion *r; | |
369 | int i; | |
370 | ||
371 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
372 | r = &pci_dev->io_regions[i]; | |
373 | if (!r->size || r->addr == -1) | |
374 | continue; | |
375 | if (r->type == PCI_ADDRESS_SPACE_IO) { | |
376 | isa_unassign_ioport(r->addr, r->size); | |
377 | } else { | |
378 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
379 | r->size, | |
380 | IO_MEM_UNASSIGNED); | |
381 | } | |
382 | } | |
383 | } | |
384 | ||
385 | int pci_unregister_device(PCIDevice *pci_dev) | |
386 | { | |
387 | int ret = 0; | |
388 | ||
389 | if (pci_dev->unregister) | |
390 | ret = pci_dev->unregister(pci_dev); | |
391 | if (ret) | |
392 | return ret; | |
393 | ||
394 | pci_unregister_io_regions(pci_dev); | |
395 | ||
396 | qemu_free_irqs(pci_dev->irq); | |
5851e08c | 397 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
02e2da45 | 398 | qdev_free(&pci_dev->qdev); |
5851e08c AL |
399 | return 0; |
400 | } | |
401 | ||
28c2c264 | 402 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
5fafdf24 | 403 | uint32_t size, int type, |
69b91039 FB |
404 | PCIMapIORegionFunc *map_func) |
405 | { | |
406 | PCIIORegion *r; | |
d7ce493a | 407 | uint32_t addr; |
b7ee1603 | 408 | uint32_t wmask; |
69b91039 | 409 | |
8a8696a3 | 410 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 411 | return; |
a4c20c6a AL |
412 | |
413 | if (size & (size-1)) { | |
414 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
415 | "type=0x%x, size=0x%x\n", type, size); | |
416 | exit(1); | |
417 | } | |
418 | ||
69b91039 FB |
419 | r = &pci_dev->io_regions[region_num]; |
420 | r->addr = -1; | |
421 | r->size = size; | |
422 | r->type = type; | |
423 | r->map_func = map_func; | |
b7ee1603 MT |
424 | |
425 | wmask = ~(size - 1); | |
d7ce493a PB |
426 | if (region_num == PCI_ROM_SLOT) { |
427 | addr = 0x30; | |
b7ee1603 MT |
428 | /* ROM enable bit is writeable */ |
429 | wmask |= 1; | |
d7ce493a PB |
430 | } else { |
431 | addr = 0x10 + region_num * 4; | |
432 | } | |
433 | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); | |
b7ee1603 | 434 | *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
bd4b65ee | 435 | *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff; |
69b91039 FB |
436 | } |
437 | ||
0ac32c83 FB |
438 | static void pci_update_mappings(PCIDevice *d) |
439 | { | |
440 | PCIIORegion *r; | |
441 | int cmd, i; | |
8a8696a3 | 442 | uint32_t last_addr, new_addr, config_ofs; |
3b46e624 | 443 | |
0ac32c83 | 444 | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
8a8696a3 | 445 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 446 | r = &d->io_regions[i]; |
8a8696a3 FB |
447 | if (i == PCI_ROM_SLOT) { |
448 | config_ofs = 0x30; | |
449 | } else { | |
450 | config_ofs = 0x10 + i * 4; | |
451 | } | |
0ac32c83 FB |
452 | if (r->size != 0) { |
453 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
454 | if (cmd & PCI_COMMAND_IO) { | |
5fafdf24 | 455 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 | 456 | config_ofs)); |
0ac32c83 FB |
457 | new_addr = new_addr & ~(r->size - 1); |
458 | last_addr = new_addr + r->size - 1; | |
459 | /* NOTE: we have only 64K ioports on PC */ | |
460 | if (last_addr <= new_addr || new_addr == 0 || | |
461 | last_addr >= 0x10000) { | |
462 | new_addr = -1; | |
463 | } | |
464 | } else { | |
465 | new_addr = -1; | |
466 | } | |
467 | } else { | |
468 | if (cmd & PCI_COMMAND_MEMORY) { | |
5fafdf24 | 469 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 FB |
470 | config_ofs)); |
471 | /* the ROM slot has a specific enable bit */ | |
472 | if (i == PCI_ROM_SLOT && !(new_addr & 1)) | |
473 | goto no_mem_map; | |
0ac32c83 FB |
474 | new_addr = new_addr & ~(r->size - 1); |
475 | last_addr = new_addr + r->size - 1; | |
476 | /* NOTE: we do not support wrapping */ | |
477 | /* XXX: as we cannot support really dynamic | |
478 | mappings, we handle specific values as invalid | |
479 | mappings. */ | |
480 | if (last_addr <= new_addr || new_addr == 0 || | |
481 | last_addr == -1) { | |
482 | new_addr = -1; | |
483 | } | |
484 | } else { | |
8a8696a3 | 485 | no_mem_map: |
0ac32c83 FB |
486 | new_addr = -1; |
487 | } | |
488 | } | |
489 | /* now do the real mapping */ | |
490 | if (new_addr != r->addr) { | |
491 | if (r->addr != -1) { | |
492 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
493 | int class; | |
494 | /* NOTE: specific hack for IDE in PC case: | |
495 | only one byte must be mapped. */ | |
496 | class = d->config[0x0a] | (d->config[0x0b] << 8); | |
497 | if (class == 0x0101 && r->size == 4) { | |
498 | isa_unassign_ioport(r->addr + 2, 1); | |
499 | } else { | |
500 | isa_unassign_ioport(r->addr, r->size); | |
501 | } | |
502 | } else { | |
502a5395 | 503 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
5fafdf24 | 504 | r->size, |
0ac32c83 | 505 | IO_MEM_UNASSIGNED); |
f65ed4c1 | 506 | qemu_unregister_coalesced_mmio(r->addr, r->size); |
0ac32c83 FB |
507 | } |
508 | } | |
509 | r->addr = new_addr; | |
510 | if (r->addr != -1) { | |
511 | r->map_func(d, i, r->addr, r->size, r->type); | |
512 | } | |
513 | } | |
514 | } | |
515 | } | |
516 | } | |
517 | ||
5fafdf24 | 518 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 519 | uint32_t address, int len) |
69b91039 | 520 | { |
0ac32c83 | 521 | uint32_t val; |
a2d4e44b | 522 | |
0ac32c83 | 523 | switch(len) { |
0ac32c83 FB |
524 | default: |
525 | case 4: | |
a2d4e44b TS |
526 | if (address <= 0xfc) { |
527 | val = le32_to_cpu(*(uint32_t *)(d->config + address)); | |
528 | break; | |
529 | } | |
530 | /* fall through */ | |
531 | case 2: | |
532 | if (address <= 0xfe) { | |
533 | val = le16_to_cpu(*(uint16_t *)(d->config + address)); | |
534 | break; | |
535 | } | |
536 | /* fall through */ | |
537 | case 1: | |
538 | val = d->config[address]; | |
0ac32c83 FB |
539 | break; |
540 | } | |
541 | return val; | |
542 | } | |
543 | ||
b7ee1603 | 544 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 545 | { |
b7ee1603 MT |
546 | uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
547 | int i; | |
0ac32c83 | 548 | |
0ac32c83 | 549 | /* not efficient, but simple */ |
b7ee1603 MT |
550 | memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
551 | for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { | |
552 | uint8_t wmask = d->wmask[addr]; | |
553 | d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); | |
0ac32c83 | 554 | } |
b7ee1603 MT |
555 | if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
556 | || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) | |
557 | & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) | |
0ac32c83 | 558 | pci_update_mappings(d); |
69b91039 FB |
559 | } |
560 | ||
502a5395 | 561 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
69b91039 | 562 | { |
30468f78 FB |
563 | PCIBus *s = opaque; |
564 | PCIDevice *pci_dev; | |
565 | int config_addr, bus_num; | |
3b46e624 | 566 | |
d8d2e079 IY |
567 | #if 0 |
568 | PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n", | |
569 | addr, val, len); | |
69b91039 | 570 | #endif |
502a5395 | 571 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
572 | while (s && s->bus_num != bus_num) |
573 | s = s->next; | |
574 | if (!s) | |
69b91039 | 575 | return; |
502a5395 | 576 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
577 | if (!pci_dev) |
578 | return; | |
502a5395 | 579 | config_addr = addr & 0xff; |
d8d2e079 IY |
580 | PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n", |
581 | pci_dev->name, config_addr, val, len); | |
0ac32c83 | 582 | pci_dev->config_write(pci_dev, config_addr, val, len); |
69b91039 FB |
583 | } |
584 | ||
502a5395 | 585 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
69b91039 | 586 | { |
30468f78 FB |
587 | PCIBus *s = opaque; |
588 | PCIDevice *pci_dev; | |
589 | int config_addr, bus_num; | |
69b91039 FB |
590 | uint32_t val; |
591 | ||
502a5395 | 592 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
593 | while (s && s->bus_num != bus_num) |
594 | s= s->next; | |
595 | if (!s) | |
69b91039 | 596 | goto fail; |
502a5395 | 597 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
598 | if (!pci_dev) { |
599 | fail: | |
63ce9e0a FB |
600 | switch(len) { |
601 | case 1: | |
602 | val = 0xff; | |
603 | break; | |
604 | case 2: | |
605 | val = 0xffff; | |
606 | break; | |
607 | default: | |
608 | case 4: | |
609 | val = 0xffffffff; | |
610 | break; | |
611 | } | |
69b91039 FB |
612 | goto the_end; |
613 | } | |
502a5395 | 614 | config_addr = addr & 0xff; |
69b91039 | 615 | val = pci_dev->config_read(pci_dev, config_addr, len); |
d8d2e079 IY |
616 | PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n", |
617 | pci_dev->name, config_addr, val, len); | |
69b91039 | 618 | the_end: |
d8d2e079 IY |
619 | #if 0 |
620 | PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n", | |
621 | addr, val, len); | |
69b91039 FB |
622 | #endif |
623 | return val; | |
624 | } | |
625 | ||
502a5395 PB |
626 | /***********************************************************/ |
627 | /* generic PCI irq support */ | |
30468f78 | 628 | |
502a5395 | 629 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 630 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 631 | { |
d537cf6c | 632 | PCIDevice *pci_dev = (PCIDevice *)opaque; |
80b3ada7 PB |
633 | PCIBus *bus; |
634 | int change; | |
3b46e624 | 635 | |
80b3ada7 PB |
636 | change = level - pci_dev->irq_state[irq_num]; |
637 | if (!change) | |
638 | return; | |
d2b59317 | 639 | |
d2b59317 | 640 | pci_dev->irq_state[irq_num] = level; |
5e966ce6 PB |
641 | for (;;) { |
642 | bus = pci_dev->bus; | |
80b3ada7 | 643 | irq_num = bus->map_irq(pci_dev, irq_num); |
5e966ce6 PB |
644 | if (bus->set_irq) |
645 | break; | |
80b3ada7 | 646 | pci_dev = bus->parent_dev; |
80b3ada7 PB |
647 | } |
648 | bus->irq_count[irq_num] += change; | |
d2b59317 | 649 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
69b91039 FB |
650 | } |
651 | ||
502a5395 PB |
652 | /***********************************************************/ |
653 | /* monitor info on PCI */ | |
0ac32c83 | 654 | |
6650ee6d PB |
655 | typedef struct { |
656 | uint16_t class; | |
657 | const char *desc; | |
658 | } pci_class_desc; | |
659 | ||
09bc878a | 660 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 661 | { |
4ca9c76f | 662 | { 0x0100, "SCSI controller"}, |
6650ee6d | 663 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
664 | { 0x0102, "Floppy controller"}, |
665 | { 0x0103, "IPI controller"}, | |
666 | { 0x0104, "RAID controller"}, | |
667 | { 0x0106, "SATA controller"}, | |
668 | { 0x0107, "SAS controller"}, | |
669 | { 0x0180, "Storage controller"}, | |
6650ee6d | 670 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
671 | { 0x0201, "Token Ring controller"}, |
672 | { 0x0202, "FDDI controller"}, | |
673 | { 0x0203, "ATM controller"}, | |
674 | { 0x0280, "Network controller"}, | |
6650ee6d | 675 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
676 | { 0x0301, "XGA controller"}, |
677 | { 0x0302, "3D controller"}, | |
678 | { 0x0380, "Display controller"}, | |
679 | { 0x0400, "Video controller"}, | |
680 | { 0x0401, "Audio controller"}, | |
681 | { 0x0402, "Phone"}, | |
682 | { 0x0480, "Multimedia controller"}, | |
683 | { 0x0500, "RAM controller"}, | |
684 | { 0x0501, "Flash controller"}, | |
685 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
686 | { 0x0600, "Host bridge"}, |
687 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
688 | { 0x0602, "EISA bridge"}, |
689 | { 0x0603, "MC bridge"}, | |
6650ee6d | 690 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
691 | { 0x0605, "PCMCIA bridge"}, |
692 | { 0x0606, "NUBUS bridge"}, | |
693 | { 0x0607, "CARDBUS bridge"}, | |
694 | { 0x0608, "RACEWAY bridge"}, | |
695 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
696 | { 0x0c03, "USB controller"}, |
697 | { 0, NULL} | |
698 | }; | |
699 | ||
502a5395 | 700 | static void pci_info_device(PCIDevice *d) |
30468f78 | 701 | { |
376253ec | 702 | Monitor *mon = cur_mon; |
502a5395 PB |
703 | int i, class; |
704 | PCIIORegion *r; | |
09bc878a | 705 | const pci_class_desc *desc; |
30468f78 | 706 | |
376253ec AL |
707 | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", |
708 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); | |
502a5395 | 709 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
376253ec | 710 | monitor_printf(mon, " "); |
6650ee6d PB |
711 | desc = pci_class_descriptions; |
712 | while (desc->desc && class != desc->class) | |
713 | desc++; | |
714 | if (desc->desc) { | |
376253ec | 715 | monitor_printf(mon, "%s", desc->desc); |
6650ee6d | 716 | } else { |
376253ec | 717 | monitor_printf(mon, "Class %04x", class); |
72cc6cfe | 718 | } |
376253ec | 719 | monitor_printf(mon, ": PCI device %04x:%04x\n", |
502a5395 PB |
720 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
721 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); | |
30468f78 | 722 | |
502a5395 | 723 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
376253ec AL |
724 | monitor_printf(mon, " IRQ %d.\n", |
725 | d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 726 | } |
80b3ada7 | 727 | if (class == 0x0604) { |
376253ec | 728 | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
80b3ada7 | 729 | } |
502a5395 PB |
730 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
731 | r = &d->io_regions[i]; | |
732 | if (r->size != 0) { | |
376253ec | 733 | monitor_printf(mon, " BAR%d: ", i); |
502a5395 | 734 | if (r->type & PCI_ADDRESS_SPACE_IO) { |
376253ec AL |
735 | monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n", |
736 | r->addr, r->addr + r->size - 1); | |
502a5395 | 737 | } else { |
376253ec AL |
738 | monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n", |
739 | r->addr, r->addr + r->size - 1); | |
502a5395 PB |
740 | } |
741 | } | |
77d4bc34 | 742 | } |
8ad12514 | 743 | monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
80b3ada7 PB |
744 | if (class == 0x0604 && d->config[0x19] != 0) { |
745 | pci_for_each_device(d->config[0x19], pci_info_device); | |
746 | } | |
384d8876 FB |
747 | } |
748 | ||
80b3ada7 | 749 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
384d8876 | 750 | { |
502a5395 | 751 | PCIBus *bus = first_bus; |
384d8876 | 752 | PCIDevice *d; |
502a5395 | 753 | int devfn; |
3b46e624 | 754 | |
80b3ada7 PB |
755 | while (bus && bus->bus_num != bus_num) |
756 | bus = bus->next; | |
502a5395 PB |
757 | if (bus) { |
758 | for(devfn = 0; devfn < 256; devfn++) { | |
759 | d = bus->devices[devfn]; | |
760 | if (d) | |
761 | fn(d); | |
762 | } | |
f2aa58c6 | 763 | } |
f2aa58c6 FB |
764 | } |
765 | ||
376253ec | 766 | void pci_info(Monitor *mon) |
f2aa58c6 | 767 | { |
80b3ada7 | 768 | pci_for_each_device(0, pci_info_device); |
77d4bc34 | 769 | } |
a41b2ff2 | 770 | |
1f5f6638 | 771 | PCIDevice *pci_create(const char *name, const char *devaddr) |
5607c388 MA |
772 | { |
773 | PCIBus *bus; | |
774 | int devfn; | |
775 | DeviceState *dev; | |
776 | ||
777 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
778 | if (!bus) { | |
779 | fprintf(stderr, "Invalid PCI device address %s for device %s\n", | |
780 | devaddr, name); | |
781 | exit(1); | |
782 | } | |
783 | ||
784 | dev = qdev_create(&bus->qbus, name); | |
a6307b08 | 785 | qdev_prop_set_uint32(dev, "addr", devfn); |
5607c388 MA |
786 | return (PCIDevice *)dev; |
787 | } | |
788 | ||
cb457d76 AL |
789 | static const char * const pci_nic_models[] = { |
790 | "ne2k_pci", | |
791 | "i82551", | |
792 | "i82557b", | |
793 | "i82559er", | |
794 | "rtl8139", | |
795 | "e1000", | |
796 | "pcnet", | |
797 | "virtio", | |
798 | NULL | |
799 | }; | |
800 | ||
9d07d757 PB |
801 | static const char * const pci_nic_names[] = { |
802 | "ne2k_pci", | |
803 | "i82551", | |
804 | "i82557b", | |
805 | "i82559er", | |
806 | "rtl8139", | |
807 | "e1000", | |
808 | "pcnet", | |
53c25cea | 809 | "virtio-net-pci", |
cb457d76 AL |
810 | NULL |
811 | }; | |
812 | ||
a41b2ff2 | 813 | /* Initialize a PCI NIC. */ |
5607c388 MA |
814 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
815 | const char *default_devaddr) | |
a41b2ff2 | 816 | { |
5607c388 MA |
817 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
818 | PCIDevice *pci_dev; | |
9d07d757 | 819 | DeviceState *dev; |
cb457d76 AL |
820 | int i; |
821 | ||
822 | qemu_check_nic_model_list(nd, pci_nic_models, default_model); | |
823 | ||
9d07d757 | 824 | for (i = 0; pci_nic_models[i]; i++) { |
72da4208 | 825 | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
5607c388 MA |
826 | pci_dev = pci_create(pci_nic_names[i], devaddr); |
827 | dev = &pci_dev->qdev; | |
eb54b6dc GH |
828 | if (nd->id) |
829 | dev->id = qemu_strdup(nd->id); | |
ee6847d1 | 830 | dev->nd = nd; |
9d07d757 PB |
831 | qdev_init(dev); |
832 | nd->private = dev; | |
5607c388 | 833 | return pci_dev; |
72da4208 | 834 | } |
9d07d757 | 835 | } |
72da4208 AL |
836 | |
837 | return NULL; | |
a41b2ff2 PB |
838 | } |
839 | ||
80b3ada7 PB |
840 | typedef struct { |
841 | PCIDevice dev; | |
842 | PCIBus *bus; | |
843 | } PCIBridge; | |
844 | ||
9596ebb7 | 845 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
846 | uint32_t address, uint32_t val, int len) |
847 | { | |
848 | PCIBridge *s = (PCIBridge *)d; | |
849 | ||
80b3ada7 | 850 | pci_default_write_config(d, address, val, len); |
b7ee1603 | 851 | s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; |
80b3ada7 PB |
852 | } |
853 | ||
3ae80618 AL |
854 | PCIBus *pci_find_bus(int bus_num) |
855 | { | |
856 | PCIBus *bus = first_bus; | |
857 | ||
858 | while (bus && bus->bus_num != bus_num) | |
859 | bus = bus->next; | |
860 | ||
861 | return bus; | |
862 | } | |
863 | ||
864 | PCIDevice *pci_find_device(int bus_num, int slot, int function) | |
865 | { | |
866 | PCIBus *bus = pci_find_bus(bus_num); | |
867 | ||
868 | if (!bus) | |
869 | return NULL; | |
870 | ||
871 | return bus->devices[PCI_DEVFN(slot, function)]; | |
872 | } | |
873 | ||
480b9f24 | 874 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
80b3ada7 PB |
875 | pci_map_irq_fn map_irq, const char *name) |
876 | { | |
877 | PCIBridge *s; | |
5fafdf24 | 878 | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), |
80b3ada7 | 879 | devfn, NULL, pci_bridge_write_config); |
480b9f24 BS |
880 | |
881 | pci_config_set_vendor_id(s->dev.config, vid); | |
882 | pci_config_set_device_id(s->dev.config, did); | |
883 | ||
80b3ada7 PB |
884 | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
885 | s->dev.config[0x05] = 0x00; | |
886 | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
887 | s->dev.config[0x07] = 0x00; // status = fast devsel | |
888 | s->dev.config[0x08] = 0x00; // revision | |
889 | s->dev.config[0x09] = 0x00; // programming i/f | |
173a543b | 890 | pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
80b3ada7 | 891 | s->dev.config[0x0D] = 0x10; // latency_timer |
6407f373 IY |
892 | s->dev.config[PCI_HEADER_TYPE] = |
893 | PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type | |
80b3ada7 PB |
894 | s->dev.config[0x1E] = 0xa0; // secondary status |
895 | ||
72f44c8c | 896 | s->bus = pci_register_secondary_bus(&s->dev, map_irq, name); |
80b3ada7 PB |
897 | return s->bus; |
898 | } | |
6b1b92d3 | 899 | |
02e2da45 | 900 | static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
901 | { |
902 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 903 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 PB |
904 | PCIBus *bus; |
905 | int devfn; | |
906 | ||
02e2da45 | 907 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 908 | devfn = pci_dev->devfn; |
16eaedf2 | 909 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
0aab0d3a | 910 | info->config_read, info->config_write); |
6b1b92d3 | 911 | assert(pci_dev); |
02e2da45 | 912 | info->init(pci_dev); |
6b1b92d3 PB |
913 | } |
914 | ||
0aab0d3a | 915 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 916 | { |
02e2da45 | 917 | info->qdev.init = pci_qdev_init; |
10c4c98a | 918 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 919 | qdev_register(&info->qdev); |
6b1b92d3 PB |
920 | } |
921 | ||
0aab0d3a GH |
922 | void pci_qdev_register_many(PCIDeviceInfo *info) |
923 | { | |
924 | while (info->qdev.name) { | |
925 | pci_qdev_register(info); | |
926 | info++; | |
927 | } | |
928 | } | |
929 | ||
6b1b92d3 PB |
930 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
931 | { | |
932 | DeviceState *dev; | |
933 | ||
02e2da45 | 934 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 935 | qdev_prop_set_uint32(dev, "addr", devfn); |
6b1b92d3 PB |
936 | qdev_init(dev); |
937 | ||
938 | return (PCIDevice *)dev; | |
939 | } | |
6f4cbd39 MT |
940 | |
941 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
942 | { | |
943 | int offset = PCI_CONFIG_HEADER_SIZE; | |
944 | int i; | |
945 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
946 | if (pdev->used[i]) | |
947 | offset = i + 1; | |
948 | else if (i - offset + 1 == size) | |
949 | return offset; | |
950 | return 0; | |
951 | } | |
952 | ||
953 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
954 | uint8_t *prev_p) | |
955 | { | |
956 | uint8_t next, prev; | |
957 | ||
958 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
959 | return 0; | |
960 | ||
961 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
962 | prev = next + PCI_CAP_LIST_NEXT) | |
963 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
964 | break; | |
965 | ||
966 | if (prev_p) | |
967 | *prev_p = prev; | |
968 | return next; | |
969 | } | |
970 | ||
971 | /* Reserve space and add capability to the linked list in pci config space */ | |
972 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
973 | { | |
974 | uint8_t offset = pci_find_space(pdev, size); | |
975 | uint8_t *config = pdev->config + offset; | |
976 | if (!offset) | |
977 | return -ENOSPC; | |
978 | config[PCI_CAP_LIST_ID] = cap_id; | |
979 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
980 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
981 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
982 | memset(pdev->used + offset, 0xFF, size); | |
983 | /* Make capability read-only by default */ | |
984 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
985 | /* Check capability by default */ |
986 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
987 | return offset; |
988 | } | |
989 | ||
990 | /* Unlink capability from the pci config space. */ | |
991 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
992 | { | |
993 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
994 | if (!offset) | |
995 | return; | |
996 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
997 | /* Make capability writeable again */ | |
998 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
999 | /* Clear cmask as device-specific registers can't be checked */ |
1000 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1001 | memset(pdev->used + offset, 0, size); |
1002 | ||
1003 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1004 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1005 | } | |
1006 | ||
1007 | /* Reserve space for capability at a known offset (to call after load). */ | |
1008 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1009 | { | |
1010 | memset(pdev->used + offset, 0xff, size); | |
1011 | } | |
1012 | ||
1013 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1014 | { | |
1015 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1016 | } | |
10c4c98a GH |
1017 | |
1018 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1019 | { | |
1020 | PCIDevice *d = (PCIDevice *)dev; | |
1021 | const pci_class_desc *desc; | |
1022 | char ctxt[64]; | |
1023 | PCIIORegion *r; | |
1024 | int i, class; | |
1025 | ||
1026 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); | |
1027 | desc = pci_class_descriptions; | |
1028 | while (desc->desc && class != desc->class) | |
1029 | desc++; | |
1030 | if (desc->desc) { | |
1031 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1032 | } else { | |
1033 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1034 | } | |
1035 | ||
1036 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1037 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1038 | indent, "", ctxt, | |
1039 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7, | |
1040 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), | |
1041 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))), | |
1042 | le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))), | |
1043 | le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID)))); | |
1044 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1045 | r = &d->io_regions[i]; | |
1046 | if (!r->size) | |
1047 | continue; | |
1048 | monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", | |
1049 | i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem", | |
1050 | r->addr, r->addr + r->size - 1); | |
1051 | } | |
1052 | } |