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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
72bb3c75 | 29 | #include "loader.h" |
69b91039 FB |
30 | |
31 | //#define DEBUG_PCI | |
d8d2e079 | 32 | #ifdef DEBUG_PCI |
2e49d64a | 33 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
34 | #else |
35 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
36 | #endif | |
69b91039 | 37 | |
30468f78 | 38 | struct PCIBus { |
02e2da45 | 39 | BusState qbus; |
30468f78 | 40 | int devfn_min; |
502a5395 | 41 | pci_set_irq_fn set_irq; |
d2b59317 | 42 | pci_map_irq_fn map_irq; |
ee995ffb | 43 | pci_hotplug_fn hotplug; |
30468f78 | 44 | uint32_t config_reg; /* XXX: suppress */ |
5d4e84c8 | 45 | void *irq_opaque; |
30468f78 | 46 | PCIDevice *devices[256]; |
80b3ada7 | 47 | PCIDevice *parent_dev; |
e822a52a IY |
48 | |
49 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
50 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
51 | ||
d2b59317 PB |
52 | /* The bus IRQ state is the logical OR of the connected devices. |
53 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 54 | int nirq; |
10c4c98a GH |
55 | int *irq_count; |
56 | }; | |
57 | ||
58 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
59 | ||
60 | static struct BusInfo pci_bus_info = { | |
61 | .name = "PCI", | |
62 | .size = sizeof(PCIBus), | |
63 | .print_dev = pcibus_dev_print, | |
ee6847d1 | 64 | .props = (Property[]) { |
54586bd1 | 65 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
898829d5 | 66 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), |
027866ce | 67 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
54586bd1 | 68 | DEFINE_PROP_END_OF_LIST() |
ee6847d1 | 69 | } |
30468f78 | 70 | }; |
69b91039 | 71 | |
1941d19c | 72 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 73 | static void pci_set_irq(void *opaque, int irq_num, int level); |
898829d5 | 74 | static int pci_add_option_rom(PCIDevice *pdev); |
1941d19c | 75 | |
c227f099 | 76 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
77 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
78 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
79 | |
80 | struct PCIHostBus { | |
81 | int domain; | |
82 | struct PCIBus *bus; | |
83 | QLIST_ENTRY(PCIHostBus) next; | |
84 | }; | |
85 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 86 | |
2d1e9f96 JQ |
87 | static const VMStateDescription vmstate_pcibus = { |
88 | .name = "PCIBUS", | |
89 | .version_id = 1, | |
90 | .minimum_version_id = 1, | |
91 | .minimum_version_id_old = 1, | |
92 | .fields = (VMStateField []) { | |
93 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 94 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 95 | VMSTATE_END_OF_LIST() |
52fc1d83 | 96 | } |
2d1e9f96 | 97 | }; |
52fc1d83 | 98 | |
b3b11697 | 99 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 100 | { |
b3b11697 IY |
101 | uint8_t type; |
102 | ||
103 | if (reg != PCI_ROM_SLOT) | |
104 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
105 | ||
106 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
107 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
108 | } |
109 | ||
eea4acfa MT |
110 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
111 | { | |
112 | return (d->irq_state >> irq_num) & 0x1; | |
113 | } | |
114 | ||
115 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
116 | { | |
117 | d->irq_state &= ~(0x1 << irq_num); | |
118 | d->irq_state |= level << irq_num; | |
119 | } | |
120 | ||
121 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
122 | { | |
123 | PCIBus *bus; | |
124 | for (;;) { | |
125 | bus = pci_dev->bus; | |
126 | irq_num = bus->map_irq(pci_dev, irq_num); | |
127 | if (bus->set_irq) | |
128 | break; | |
129 | pci_dev = bus->parent_dev; | |
130 | } | |
131 | bus->irq_count[irq_num] += change; | |
132 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
133 | } | |
134 | ||
67a2698d MT |
135 | /* Update interrupt status bit in config space on interrupt |
136 | * state change. */ | |
137 | static void pci_update_irq_status(PCIDevice *dev) | |
138 | { | |
139 | if (dev->irq_state) { | |
140 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
141 | } else { | |
142 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
143 | } | |
144 | } | |
145 | ||
5330de09 MT |
146 | static void pci_device_reset(PCIDevice *dev) |
147 | { | |
c0b1905b MT |
148 | int r; |
149 | ||
eea4acfa | 150 | dev->irq_state = 0; |
67a2698d | 151 | pci_update_irq_status(dev); |
c0b1905b MT |
152 | dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
153 | PCI_COMMAND_MASTER); | |
154 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; | |
155 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
156 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
157 | if (!dev->io_regions[r].size) { | |
158 | continue; | |
159 | } | |
b3b11697 | 160 | pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
c0b1905b MT |
161 | } |
162 | pci_update_mappings(dev); | |
5330de09 MT |
163 | } |
164 | ||
6eaa6847 GN |
165 | static void pci_bus_reset(void *opaque) |
166 | { | |
a60380a5 | 167 | PCIBus *bus = opaque; |
6eaa6847 GN |
168 | int i; |
169 | ||
170 | for (i = 0; i < bus->nirq; i++) { | |
171 | bus->irq_count[i] = 0; | |
172 | } | |
5330de09 MT |
173 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
174 | if (bus->devices[i]) { | |
175 | pci_device_reset(bus->devices[i]); | |
176 | } | |
6eaa6847 GN |
177 | } |
178 | } | |
179 | ||
e822a52a IY |
180 | static void pci_host_bus_register(int domain, PCIBus *bus) |
181 | { | |
182 | struct PCIHostBus *host; | |
183 | host = qemu_mallocz(sizeof(*host)); | |
184 | host->domain = domain; | |
185 | host->bus = bus; | |
186 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
187 | } | |
188 | ||
c469e1dd | 189 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
190 | { |
191 | struct PCIHostBus *host; | |
192 | ||
193 | QLIST_FOREACH(host, &host_buses, next) { | |
194 | if (host->domain == domain) { | |
195 | return host->bus; | |
196 | } | |
197 | } | |
198 | ||
199 | return NULL; | |
200 | } | |
201 | ||
21eea4b3 GH |
202 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
203 | const char *name, int devfn_min) | |
30468f78 | 204 | { |
21eea4b3 | 205 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
502a5395 | 206 | bus->devfn_min = devfn_min; |
e822a52a IY |
207 | |
208 | /* host bridge */ | |
209 | QLIST_INIT(&bus->child); | |
210 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
211 | ||
5084bca1 | 212 | vmstate_register(-1, &vmstate_pcibus, bus); |
a08d4367 | 213 | qemu_register_reset(pci_bus_reset, bus); |
21eea4b3 GH |
214 | } |
215 | ||
216 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) | |
217 | { | |
218 | PCIBus *bus; | |
219 | ||
220 | bus = qemu_mallocz(sizeof(*bus)); | |
221 | bus->qbus.qdev_allocated = 1; | |
222 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
223 | return bus; | |
224 | } | |
225 | ||
226 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
227 | void *irq_opaque, int nirq) | |
228 | { | |
229 | bus->set_irq = set_irq; | |
230 | bus->map_irq = map_irq; | |
231 | bus->irq_opaque = irq_opaque; | |
232 | bus->nirq = nirq; | |
233 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
234 | } | |
235 | ||
ee995ffb GH |
236 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug) |
237 | { | |
238 | bus->qbus.allow_hotplug = 1; | |
239 | bus->hotplug = hotplug; | |
240 | } | |
241 | ||
21eea4b3 GH |
242 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
243 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
244 | void *irq_opaque, int devfn_min, int nirq) | |
245 | { | |
246 | PCIBus *bus; | |
247 | ||
248 | bus = pci_bus_new(parent, name, devfn_min); | |
249 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
250 | return bus; |
251 | } | |
69b91039 | 252 | |
e822a52a IY |
253 | static void pci_register_secondary_bus(PCIBus *parent, |
254 | PCIBus *bus, | |
03587182 GH |
255 | PCIDevice *dev, |
256 | pci_map_irq_fn map_irq, | |
257 | const char *name) | |
80b3ada7 | 258 | { |
03587182 | 259 | qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
80b3ada7 PB |
260 | bus->map_irq = map_irq; |
261 | bus->parent_dev = dev; | |
e822a52a IY |
262 | |
263 | QLIST_INIT(&bus->child); | |
264 | QLIST_INSERT_HEAD(&parent->child, bus, sibling); | |
265 | } | |
266 | ||
267 | static void pci_unregister_secondary_bus(PCIBus *bus) | |
268 | { | |
269 | assert(QLIST_EMPTY(&bus->child)); | |
270 | QLIST_REMOVE(bus, sibling); | |
80b3ada7 PB |
271 | } |
272 | ||
502a5395 PB |
273 | int pci_bus_num(PCIBus *s) |
274 | { | |
e94ff650 IY |
275 | if (!s->parent_dev) |
276 | return 0; /* pci host bridge */ | |
277 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
278 | } |
279 | ||
73534f2f | 280 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 281 | { |
73534f2f | 282 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 283 | uint8_t *config; |
52fc1d83 AZ |
284 | int i; |
285 | ||
a9f49946 IY |
286 | assert(size == pci_config_size(s)); |
287 | config = qemu_malloc(size); | |
288 | ||
289 | qemu_get_buffer(f, config, size); | |
290 | for (i = 0; i < size; ++i) { | |
291 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) { | |
292 | qemu_free(config); | |
bd4b65ee | 293 | return -EINVAL; |
a9f49946 IY |
294 | } |
295 | } | |
296 | memcpy(s->config, config, size); | |
bd4b65ee | 297 | |
1941d19c | 298 | pci_update_mappings(s); |
52fc1d83 | 299 | |
a9f49946 | 300 | qemu_free(config); |
30ca2aab FB |
301 | return 0; |
302 | } | |
303 | ||
73534f2f | 304 | /* just put buffer */ |
84e2e3eb | 305 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 306 | { |
dbe73d7f | 307 | const uint8_t **v = pv; |
a9f49946 | 308 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 309 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
310 | } |
311 | ||
312 | static VMStateInfo vmstate_info_pci_config = { | |
313 | .name = "pci config", | |
314 | .get = get_pci_config_device, | |
315 | .put = put_pci_config_device, | |
316 | }; | |
317 | ||
eea4acfa MT |
318 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
319 | { | |
320 | PCIDevice *s = container_of(pv, PCIDevice, config); | |
321 | uint32_t irq_state[PCI_NUM_PINS]; | |
322 | int i; | |
323 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
324 | irq_state[i] = qemu_get_be32(f); | |
325 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
326 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
327 | irq_state[i]); | |
328 | return -EINVAL; | |
329 | } | |
330 | } | |
331 | ||
332 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
333 | pci_set_irq_state(s, i, irq_state[i]); | |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
340 | { | |
341 | int i; | |
342 | PCIDevice *s = container_of(pv, PCIDevice, config); | |
343 | ||
344 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
345 | qemu_put_be32(f, pci_irq_state(s, i)); | |
346 | } | |
347 | } | |
348 | ||
349 | static VMStateInfo vmstate_info_pci_irq_state = { | |
350 | .name = "pci irq state", | |
351 | .get = get_pci_irq_state, | |
352 | .put = put_pci_irq_state, | |
353 | }; | |
354 | ||
73534f2f JQ |
355 | const VMStateDescription vmstate_pci_device = { |
356 | .name = "PCIDevice", | |
357 | .version_id = 2, | |
358 | .minimum_version_id = 1, | |
359 | .minimum_version_id_old = 1, | |
360 | .fields = (VMStateField []) { | |
361 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
362 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
363 | vmstate_info_pci_config, | |
364 | PCI_CONFIG_SPACE_SIZE), | |
eea4acfa MT |
365 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
366 | vmstate_info_pci_irq_state, | |
367 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
368 | VMSTATE_END_OF_LIST() |
369 | } | |
370 | }; | |
371 | ||
372 | const VMStateDescription vmstate_pcie_device = { | |
373 | .name = "PCIDevice", | |
374 | .version_id = 2, | |
375 | .minimum_version_id = 1, | |
376 | .minimum_version_id_old = 1, | |
377 | .fields = (VMStateField []) { | |
378 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
379 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
380 | vmstate_info_pci_config, | |
381 | PCIE_CONFIG_SPACE_SIZE), | |
eea4acfa MT |
382 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
383 | vmstate_info_pci_irq_state, | |
384 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
385 | VMSTATE_END_OF_LIST() |
386 | } | |
387 | }; | |
388 | ||
a9f49946 IY |
389 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
390 | { | |
391 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
392 | } | |
393 | ||
73534f2f JQ |
394 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
395 | { | |
67a2698d MT |
396 | /* Clear interrupt status bit: it is implicit |
397 | * in irq_state which we are saving. | |
398 | * This makes us compatible with old devices | |
399 | * which never set or clear this bit. */ | |
400 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 401 | vmstate_save_state(f, pci_get_vmstate(s), s); |
67a2698d MT |
402 | /* Restore the interrupt status bit. */ |
403 | pci_update_irq_status(s); | |
73534f2f JQ |
404 | } |
405 | ||
406 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
407 | { | |
67a2698d MT |
408 | int ret; |
409 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
410 | /* Restore the interrupt status bit. */ | |
411 | pci_update_irq_status(s); | |
412 | return ret; | |
73534f2f JQ |
413 | } |
414 | ||
d350d97d AL |
415 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
416 | { | |
417 | uint16_t *id; | |
418 | ||
419 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
420 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
421 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
422 | return 0; | |
423 | } | |
424 | ||
880345c4 AL |
425 | /* |
426 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
427 | */ | |
428 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
429 | { | |
430 | const char *p; | |
431 | char *e; | |
432 | unsigned long val; | |
433 | unsigned long dom = 0, bus = 0; | |
434 | unsigned slot = 0; | |
435 | ||
436 | p = addr; | |
437 | val = strtoul(p, &e, 16); | |
438 | if (e == p) | |
439 | return -1; | |
440 | if (*e == ':') { | |
441 | bus = val; | |
442 | p = e + 1; | |
443 | val = strtoul(p, &e, 16); | |
444 | if (e == p) | |
445 | return -1; | |
446 | if (*e == ':') { | |
447 | dom = bus; | |
448 | bus = val; | |
449 | p = e + 1; | |
450 | val = strtoul(p, &e, 16); | |
451 | if (e == p) | |
452 | return -1; | |
453 | } | |
454 | } | |
455 | ||
456 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
457 | return -1; | |
458 | ||
459 | slot = val; | |
460 | ||
461 | if (*e) | |
462 | return -1; | |
463 | ||
464 | /* Note: QEMU doesn't implement domains other than 0 */ | |
c469e1dd | 465 | if (!pci_find_bus(pci_find_root_bus(dom), bus)) |
880345c4 AL |
466 | return -1; |
467 | ||
468 | *domp = dom; | |
469 | *busp = bus; | |
470 | *slotp = slot; | |
471 | return 0; | |
472 | } | |
473 | ||
e9283f8b JK |
474 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
475 | unsigned *slotp) | |
880345c4 | 476 | { |
e9283f8b JK |
477 | /* strip legacy tag */ |
478 | if (!strncmp(addr, "pci_addr=", 9)) { | |
479 | addr += 9; | |
480 | } | |
481 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
482 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 483 | return -1; |
e9283f8b JK |
484 | } |
485 | return 0; | |
880345c4 AL |
486 | } |
487 | ||
49bd1458 | 488 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
489 | { |
490 | int dom, bus; | |
491 | unsigned slot; | |
492 | ||
493 | if (!devaddr) { | |
494 | *devfnp = -1; | |
c469e1dd | 495 | return pci_find_bus(pci_find_root_bus(0), 0); |
5607c388 MA |
496 | } |
497 | ||
498 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
499 | return NULL; | |
500 | } | |
501 | ||
502 | *devfnp = slot << 3; | |
c469e1dd | 503 | return pci_find_bus(pci_find_root_bus(0), bus); |
5607c388 MA |
504 | } |
505 | ||
bd4b65ee MT |
506 | static void pci_init_cmask(PCIDevice *dev) |
507 | { | |
508 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
509 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
510 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
511 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
512 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
513 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
514 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
515 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
516 | } | |
517 | ||
b7ee1603 MT |
518 | static void pci_init_wmask(PCIDevice *dev) |
519 | { | |
a9f49946 IY |
520 | int config_size = pci_config_size(dev); |
521 | ||
b7ee1603 MT |
522 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
523 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 524 | pci_set_word(dev->wmask + PCI_COMMAND, |
686a3c3d | 525 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
3e21ffc9 IY |
526 | |
527 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
528 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
529 | } |
530 | ||
fb231628 IY |
531 | static void pci_init_wmask_bridge(PCIDevice *d) |
532 | { | |
533 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
534 | PCI_SEC_LETENCY_TIMER */ | |
535 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
536 | ||
537 | /* base and limit */ | |
538 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
539 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
540 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
541 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
542 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
543 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
544 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
545 | PCI_PREF_RANGE_MASK & 0xffff); | |
546 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
547 | PCI_PREF_RANGE_MASK & 0xffff); | |
548 | ||
549 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
550 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
551 | ||
552 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); | |
553 | } | |
554 | ||
a9f49946 IY |
555 | static void pci_config_alloc(PCIDevice *pci_dev) |
556 | { | |
557 | int config_size = pci_config_size(pci_dev); | |
558 | ||
559 | pci_dev->config = qemu_mallocz(config_size); | |
560 | pci_dev->cmask = qemu_mallocz(config_size); | |
561 | pci_dev->wmask = qemu_mallocz(config_size); | |
562 | pci_dev->used = qemu_mallocz(config_size); | |
563 | } | |
564 | ||
565 | static void pci_config_free(PCIDevice *pci_dev) | |
566 | { | |
567 | qemu_free(pci_dev->config); | |
568 | qemu_free(pci_dev->cmask); | |
569 | qemu_free(pci_dev->wmask); | |
570 | qemu_free(pci_dev->used); | |
571 | } | |
572 | ||
69b91039 | 573 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
574 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
575 | const char *name, int devfn, | |
576 | PCIConfigReadFunc *config_read, | |
fb231628 IY |
577 | PCIConfigWriteFunc *config_write, |
578 | uint8_t header_type) | |
69b91039 | 579 | { |
69b91039 | 580 | if (devfn < 0) { |
b47b0706 IY |
581 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
582 | devfn += 8) { | |
30468f78 | 583 | if (!bus->devices[devfn]) |
69b91039 FB |
584 | goto found; |
585 | } | |
ea2138cf GH |
586 | qemu_error("PCI: no devfn available for %s, all in use\n", name); |
587 | return NULL; | |
69b91039 | 588 | found: ; |
07b7d053 | 589 | } else if (bus->devices[devfn]) { |
ea2138cf | 590 | qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn, |
c364c974 | 591 | name, bus->devices[devfn]->name); |
ea2138cf | 592 | return NULL; |
69b91039 | 593 | } |
30468f78 | 594 | pci_dev->bus = bus; |
69b91039 FB |
595 | pci_dev->devfn = devfn; |
596 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
eea4acfa | 597 | pci_dev->irq_state = 0; |
a9f49946 | 598 | pci_config_alloc(pci_dev); |
fb231628 IY |
599 | |
600 | header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
601 | if (header_type == PCI_HEADER_TYPE_NORMAL) { | |
602 | pci_set_default_subsystem_id(pci_dev); | |
603 | } | |
bd4b65ee | 604 | pci_init_cmask(pci_dev); |
b7ee1603 | 605 | pci_init_wmask(pci_dev); |
fb231628 IY |
606 | if (header_type == PCI_HEADER_TYPE_BRIDGE) { |
607 | pci_init_wmask_bridge(pci_dev); | |
608 | } | |
0ac32c83 FB |
609 | |
610 | if (!config_read) | |
611 | config_read = pci_default_read_config; | |
612 | if (!config_write) | |
613 | config_write = pci_default_write_config; | |
69b91039 FB |
614 | pci_dev->config_read = config_read; |
615 | pci_dev->config_write = config_write; | |
30468f78 | 616 | bus->devices[devfn] = pci_dev; |
e369cad7 | 617 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 618 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
619 | return pci_dev; |
620 | } | |
621 | ||
6b1b92d3 PB |
622 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
623 | int instance_size, int devfn, | |
624 | PCIConfigReadFunc *config_read, | |
625 | PCIConfigWriteFunc *config_write) | |
626 | { | |
627 | PCIDevice *pci_dev; | |
628 | ||
629 | pci_dev = qemu_mallocz(instance_size); | |
630 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
fb231628 IY |
631 | config_read, config_write, |
632 | PCI_HEADER_TYPE_NORMAL); | |
ea2138cf GH |
633 | if (pci_dev == NULL) { |
634 | hw_error("PCI: can't register device\n"); | |
635 | } | |
6b1b92d3 PB |
636 | return pci_dev; |
637 | } | |
c227f099 | 638 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
5851e08c AL |
639 | { |
640 | return addr + pci_mem_base; | |
641 | } | |
642 | ||
643 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
644 | { | |
645 | PCIIORegion *r; | |
646 | int i; | |
647 | ||
648 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
649 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 650 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 651 | continue; |
0392a017 | 652 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
a0c7a97e | 653 | isa_unassign_ioport(r->addr, r->filtered_size); |
5851e08c AL |
654 | } else { |
655 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
a0c7a97e | 656 | r->filtered_size, |
5851e08c AL |
657 | IO_MEM_UNASSIGNED); |
658 | } | |
659 | } | |
660 | } | |
661 | ||
a36a344d | 662 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 663 | { |
a36a344d | 664 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 665 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
666 | int ret = 0; |
667 | ||
e3936fa5 GH |
668 | if (info->exit) |
669 | ret = info->exit(pci_dev); | |
5851e08c AL |
670 | if (ret) |
671 | return ret; | |
672 | ||
673 | pci_unregister_io_regions(pci_dev); | |
674 | ||
675 | qemu_free_irqs(pci_dev->irq); | |
5851e08c | 676 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
a9f49946 | 677 | pci_config_free(pci_dev); |
5851e08c AL |
678 | return 0; |
679 | } | |
680 | ||
28c2c264 | 681 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 682 | pcibus_t size, int type, |
69b91039 FB |
683 | PCIMapIORegionFunc *map_func) |
684 | { | |
685 | PCIIORegion *r; | |
d7ce493a | 686 | uint32_t addr; |
6e355d90 | 687 | pcibus_t wmask; |
69b91039 | 688 | |
8a8696a3 | 689 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 690 | return; |
a4c20c6a AL |
691 | |
692 | if (size & (size-1)) { | |
693 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 694 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
695 | exit(1); |
696 | } | |
697 | ||
69b91039 | 698 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 699 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 | 700 | r->size = size; |
a0c7a97e | 701 | r->filtered_size = size; |
69b91039 FB |
702 | r->type = type; |
703 | r->map_func = map_func; | |
b7ee1603 MT |
704 | |
705 | wmask = ~(size - 1); | |
b3b11697 | 706 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 707 | if (region_num == PCI_ROM_SLOT) { |
b7ee1603 | 708 | /* ROM enable bit is writeable */ |
5330de09 | 709 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 710 | } |
b0ff8eb2 | 711 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
712 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
713 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
714 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
715 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
716 | } else { | |
717 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
718 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
719 | } | |
69b91039 FB |
720 | } |
721 | ||
a0c7a97e IY |
722 | static uint32_t pci_config_get_io_base(PCIDevice *d, |
723 | uint32_t base, uint32_t base_upper16) | |
724 | { | |
725 | uint32_t val; | |
726 | ||
727 | val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; | |
728 | if (d->config[base] & PCI_IO_RANGE_TYPE_32) { | |
10c9c329 | 729 | val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; |
a0c7a97e IY |
730 | } |
731 | return val; | |
732 | } | |
733 | ||
d46636b8 | 734 | static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base) |
a0c7a97e | 735 | { |
d46636b8 | 736 | return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) |
a0c7a97e IY |
737 | << 16; |
738 | } | |
739 | ||
d46636b8 | 740 | static pcibus_t pci_config_get_pref_base(PCIDevice *d, |
a0c7a97e IY |
741 | uint32_t base, uint32_t upper) |
742 | { | |
d46636b8 IY |
743 | pcibus_t tmp; |
744 | pcibus_t val; | |
745 | ||
746 | tmp = (pcibus_t)pci_get_word(d->config + base); | |
747 | val = (tmp & PCI_PREF_RANGE_MASK) << 16; | |
748 | if (tmp & PCI_PREF_RANGE_TYPE_64) { | |
749 | val |= (pcibus_t)pci_get_long(d->config + upper) << 32; | |
750 | } | |
a0c7a97e IY |
751 | return val; |
752 | } | |
753 | ||
754 | static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type) | |
755 | { | |
756 | pcibus_t base; | |
757 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
758 | base = pci_config_get_io_base(bridge, | |
759 | PCI_IO_BASE, PCI_IO_BASE_UPPER16); | |
760 | } else { | |
761 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
762 | base = pci_config_get_pref_base( | |
763 | bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); | |
764 | } else { | |
765 | base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); | |
766 | } | |
767 | } | |
768 | ||
769 | return base; | |
770 | } | |
771 | ||
772 | static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type) | |
773 | { | |
774 | pcibus_t limit; | |
775 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
776 | limit = pci_config_get_io_base(bridge, | |
777 | PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); | |
778 | limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ | |
779 | } else { | |
780 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
781 | limit = pci_config_get_pref_base( | |
782 | bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); | |
783 | } else { | |
784 | limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); | |
785 | } | |
786 | limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ | |
787 | } | |
788 | return limit; | |
789 | } | |
790 | ||
791 | static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, | |
792 | uint8_t type) | |
793 | { | |
794 | pcibus_t base = *addr; | |
795 | pcibus_t limit = *addr + *size - 1; | |
796 | PCIDevice *br; | |
797 | ||
798 | for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { | |
799 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
800 | ||
801 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
802 | if (!(cmd & PCI_COMMAND_IO)) { | |
803 | goto no_map; | |
804 | } | |
805 | } else { | |
806 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
807 | goto no_map; | |
808 | } | |
809 | } | |
810 | ||
811 | base = MAX(base, pci_bridge_get_base(br, type)); | |
812 | limit = MIN(limit, pci_bridge_get_limit(br, type)); | |
813 | } | |
814 | ||
815 | if (base > limit) { | |
88a95564 | 816 | goto no_map; |
a0c7a97e | 817 | } |
88a95564 MT |
818 | *addr = base; |
819 | *size = limit - base + 1; | |
820 | return; | |
821 | no_map: | |
822 | *addr = PCI_BAR_UNMAPPED; | |
823 | *size = 0; | |
a0c7a97e IY |
824 | } |
825 | ||
876a350d MT |
826 | static pcibus_t pci_bar_address(PCIDevice *d, |
827 | int reg, uint8_t type, pcibus_t size) | |
828 | { | |
829 | pcibus_t new_addr, last_addr; | |
830 | int bar = pci_bar(d, reg); | |
831 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
832 | ||
833 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
834 | if (!(cmd & PCI_COMMAND_IO)) { | |
835 | return PCI_BAR_UNMAPPED; | |
836 | } | |
837 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
838 | last_addr = new_addr + size - 1; | |
839 | /* NOTE: we have only 64K ioports on PC */ | |
840 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
841 | return PCI_BAR_UNMAPPED; | |
842 | } | |
843 | return new_addr; | |
844 | } | |
845 | ||
846 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
847 | return PCI_BAR_UNMAPPED; | |
848 | } | |
849 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
850 | new_addr = pci_get_quad(d->config + bar); | |
851 | } else { | |
852 | new_addr = pci_get_long(d->config + bar); | |
853 | } | |
854 | /* the ROM slot has a specific enable bit */ | |
855 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
856 | return PCI_BAR_UNMAPPED; | |
857 | } | |
858 | new_addr &= ~(size - 1); | |
859 | last_addr = new_addr + size - 1; | |
860 | /* NOTE: we do not support wrapping */ | |
861 | /* XXX: as we cannot support really dynamic | |
862 | mappings, we handle specific values as invalid | |
863 | mappings. */ | |
864 | if (last_addr <= new_addr || new_addr == 0 || | |
865 | last_addr == PCI_BAR_UNMAPPED) { | |
866 | return PCI_BAR_UNMAPPED; | |
867 | } | |
868 | ||
869 | /* Now pcibus_t is 64bit. | |
870 | * Check if 32 bit BAR wraps around explicitly. | |
871 | * Without this, PC ide doesn't work well. | |
872 | * TODO: remove this work around. | |
873 | */ | |
874 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
875 | return PCI_BAR_UNMAPPED; | |
876 | } | |
877 | ||
878 | /* | |
879 | * OS is allowed to set BAR beyond its addressable | |
880 | * bits. For example, 32 bit OS can set 64bit bar | |
881 | * to >4G. Check it. TODO: we might need to support | |
882 | * it in the future for e.g. PAE. | |
883 | */ | |
884 | if (last_addr >= TARGET_PHYS_ADDR_MAX) { | |
885 | return PCI_BAR_UNMAPPED; | |
886 | } | |
887 | ||
888 | return new_addr; | |
889 | } | |
890 | ||
0ac32c83 FB |
891 | static void pci_update_mappings(PCIDevice *d) |
892 | { | |
893 | PCIIORegion *r; | |
876a350d MT |
894 | int i; |
895 | pcibus_t new_addr, filtered_size; | |
3b46e624 | 896 | |
8a8696a3 | 897 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 898 | r = &d->io_regions[i]; |
a9688570 IY |
899 | |
900 | /* this region isn't registered */ | |
ec503442 | 901 | if (!r->size) |
a9688570 IY |
902 | continue; |
903 | ||
876a350d | 904 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 | 905 | |
a0c7a97e IY |
906 | /* bridge filtering */ |
907 | filtered_size = r->size; | |
908 | if (new_addr != PCI_BAR_UNMAPPED) { | |
909 | pci_bridge_filter(d, &new_addr, &filtered_size, r->type); | |
910 | } | |
911 | ||
a9688570 | 912 | /* This bar isn't changed */ |
a0c7a97e | 913 | if (new_addr == r->addr && filtered_size == r->filtered_size) |
a9688570 IY |
914 | continue; |
915 | ||
916 | /* now do the real mapping */ | |
917 | if (r->addr != PCI_BAR_UNMAPPED) { | |
918 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
919 | int class; | |
920 | /* NOTE: specific hack for IDE in PC case: | |
921 | only one byte must be mapped. */ | |
922 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
923 | if (class == 0x0101 && r->size == 4) { | |
924 | isa_unassign_ioport(r->addr + 2, 1); | |
925 | } else { | |
a0c7a97e | 926 | isa_unassign_ioport(r->addr, r->filtered_size); |
0ac32c83 | 927 | } |
a9688570 IY |
928 | } else { |
929 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
a0c7a97e | 930 | r->filtered_size, |
a9688570 | 931 | IO_MEM_UNASSIGNED); |
a0c7a97e | 932 | qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
0ac32c83 FB |
933 | } |
934 | } | |
a9688570 | 935 | r->addr = new_addr; |
a0c7a97e | 936 | r->filtered_size = filtered_size; |
a9688570 | 937 | if (r->addr != PCI_BAR_UNMAPPED) { |
a0c7a97e IY |
938 | /* |
939 | * TODO: currently almost all the map funcions assumes | |
940 | * filtered_size == size and addr & ~(size - 1) == addr. | |
941 | * However with bridge filtering, they aren't always true. | |
942 | * Teach them such cases, such that filtered_size < size and | |
943 | * addr & (size - 1) != 0. | |
944 | */ | |
945 | r->map_func(d, i, r->addr, r->filtered_size, r->type); | |
a9688570 | 946 | } |
0ac32c83 FB |
947 | } |
948 | } | |
949 | ||
5fafdf24 | 950 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 951 | uint32_t address, int len) |
69b91039 | 952 | { |
5029fe12 IY |
953 | uint32_t val = 0; |
954 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 955 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
956 | memcpy(&val, d->config + address, len); |
957 | return le32_to_cpu(val); | |
0ac32c83 FB |
958 | } |
959 | ||
b7ee1603 | 960 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 961 | { |
686a3c3d | 962 | int i; |
a9f49946 | 963 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 964 | |
91011d4f SW |
965 | for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
966 | uint8_t wmask = d->wmask[addr + i]; | |
967 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); | |
0ac32c83 | 968 | } |
260c0cd3 | 969 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
970 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
971 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 972 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 973 | pci_update_mappings(d); |
69b91039 FB |
974 | } |
975 | ||
502a5395 PB |
976 | /***********************************************************/ |
977 | /* generic PCI irq support */ | |
30468f78 | 978 | |
502a5395 | 979 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 980 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 981 | { |
a60380a5 | 982 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 983 | int change; |
3b46e624 | 984 | |
eea4acfa | 985 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
986 | if (!change) |
987 | return; | |
d2b59317 | 988 | |
eea4acfa | 989 | pci_set_irq_state(pci_dev, irq_num, level); |
67a2698d | 990 | pci_update_irq_status(pci_dev); |
eea4acfa | 991 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
992 | } |
993 | ||
502a5395 PB |
994 | /***********************************************************/ |
995 | /* monitor info on PCI */ | |
0ac32c83 | 996 | |
6650ee6d PB |
997 | typedef struct { |
998 | uint16_t class; | |
999 | const char *desc; | |
1000 | } pci_class_desc; | |
1001 | ||
09bc878a | 1002 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1003 | { |
4ca9c76f | 1004 | { 0x0100, "SCSI controller"}, |
6650ee6d | 1005 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
1006 | { 0x0102, "Floppy controller"}, |
1007 | { 0x0103, "IPI controller"}, | |
1008 | { 0x0104, "RAID controller"}, | |
1009 | { 0x0106, "SATA controller"}, | |
1010 | { 0x0107, "SAS controller"}, | |
1011 | { 0x0180, "Storage controller"}, | |
6650ee6d | 1012 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
1013 | { 0x0201, "Token Ring controller"}, |
1014 | { 0x0202, "FDDI controller"}, | |
1015 | { 0x0203, "ATM controller"}, | |
1016 | { 0x0280, "Network controller"}, | |
6650ee6d | 1017 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
1018 | { 0x0301, "XGA controller"}, |
1019 | { 0x0302, "3D controller"}, | |
1020 | { 0x0380, "Display controller"}, | |
1021 | { 0x0400, "Video controller"}, | |
1022 | { 0x0401, "Audio controller"}, | |
1023 | { 0x0402, "Phone"}, | |
1024 | { 0x0480, "Multimedia controller"}, | |
1025 | { 0x0500, "RAM controller"}, | |
1026 | { 0x0501, "Flash controller"}, | |
1027 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
1028 | { 0x0600, "Host bridge"}, |
1029 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
1030 | { 0x0602, "EISA bridge"}, |
1031 | { 0x0603, "MC bridge"}, | |
6650ee6d | 1032 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
1033 | { 0x0605, "PCMCIA bridge"}, |
1034 | { 0x0606, "NUBUS bridge"}, | |
1035 | { 0x0607, "CARDBUS bridge"}, | |
1036 | { 0x0608, "RACEWAY bridge"}, | |
1037 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
1038 | { 0x0c03, "USB controller"}, |
1039 | { 0, NULL} | |
1040 | }; | |
1041 | ||
e822a52a | 1042 | static void pci_info_device(PCIBus *bus, PCIDevice *d) |
30468f78 | 1043 | { |
376253ec | 1044 | Monitor *mon = cur_mon; |
502a5395 PB |
1045 | int i, class; |
1046 | PCIIORegion *r; | |
09bc878a | 1047 | const pci_class_desc *desc; |
30468f78 | 1048 | |
376253ec | 1049 | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", |
e94ff650 IY |
1050 | pci_bus_num(d->bus), |
1051 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); | |
b0ff8eb2 | 1052 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
376253ec | 1053 | monitor_printf(mon, " "); |
6650ee6d PB |
1054 | desc = pci_class_descriptions; |
1055 | while (desc->desc && class != desc->class) | |
1056 | desc++; | |
1057 | if (desc->desc) { | |
376253ec | 1058 | monitor_printf(mon, "%s", desc->desc); |
6650ee6d | 1059 | } else { |
376253ec | 1060 | monitor_printf(mon, "Class %04x", class); |
72cc6cfe | 1061 | } |
376253ec | 1062 | monitor_printf(mon, ": PCI device %04x:%04x\n", |
b0ff8eb2 IY |
1063 | pci_get_word(d->config + PCI_VENDOR_ID), |
1064 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
30468f78 | 1065 | |
502a5395 | 1066 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
376253ec AL |
1067 | monitor_printf(mon, " IRQ %d.\n", |
1068 | d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 1069 | } |
80b3ada7 | 1070 | if (class == 0x0604) { |
b4dccd8d IY |
1071 | uint64_t base; |
1072 | uint64_t limit; | |
1073 | ||
376253ec | 1074 | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
b4dccd8d IY |
1075 | monitor_printf(mon, " secondary bus %d.\n", |
1076 | d->config[PCI_SECONDARY_BUS]); | |
1077 | monitor_printf(mon, " subordinate bus %d.\n", | |
1078 | d->config[PCI_SUBORDINATE_BUS]); | |
1079 | ||
1080 | base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO); | |
1081 | limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO); | |
1082 | monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", | |
1083 | base, limit); | |
1084 | ||
1085 | base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
f88d7509 | 1086 | limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY); |
b4dccd8d IY |
1087 | monitor_printf(mon, |
1088 | " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", | |
1089 | base, limit); | |
1090 | ||
1091 | base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1092 | PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1093 | limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1094 | PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1095 | monitor_printf(mon, " prefetchable memory range " | |
1096 | "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit); | |
80b3ada7 | 1097 | } |
502a5395 PB |
1098 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1099 | r = &d->io_regions[i]; | |
1100 | if (r->size != 0) { | |
376253ec | 1101 | monitor_printf(mon, " BAR%d: ", i); |
0392a017 | 1102 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
89e8b13c IY |
1103 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS |
1104 | " [0x%04"FMT_PCIBUS"].\n", | |
376253ec | 1105 | r->addr, r->addr + r->size - 1); |
502a5395 | 1106 | } else { |
14421258 IY |
1107 | const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ? |
1108 | "64 bit" : "32 bit"; | |
1109 | const char *prefetch = | |
1110 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ? | |
1111 | " prefetchable" : ""; | |
1112 | ||
1113 | monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 1114 | " [0x%08"FMT_PCIBUS"].\n", |
14421258 | 1115 | type, prefetch, |
376253ec | 1116 | r->addr, r->addr + r->size - 1); |
502a5395 PB |
1117 | } |
1118 | } | |
77d4bc34 | 1119 | } |
8ad12514 | 1120 | monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
80b3ada7 | 1121 | if (class == 0x0604 && d->config[0x19] != 0) { |
e822a52a | 1122 | pci_for_each_device(bus, d->config[0x19], pci_info_device); |
80b3ada7 | 1123 | } |
384d8876 FB |
1124 | } |
1125 | ||
1074df4f IY |
1126 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1127 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
384d8876 | 1128 | { |
384d8876 | 1129 | PCIDevice *d; |
502a5395 | 1130 | int devfn; |
3b46e624 | 1131 | |
b47b0706 | 1132 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1074df4f IY |
1133 | d = bus->devices[devfn]; |
1134 | if (d) | |
1135 | fn(bus, d); | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
1140 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
1141 | { | |
e822a52a | 1142 | bus = pci_find_bus(bus, bus_num); |
1074df4f | 1143 | |
502a5395 | 1144 | if (bus) { |
1074df4f | 1145 | pci_for_each_device_under_bus(bus, fn); |
f2aa58c6 | 1146 | } |
f2aa58c6 FB |
1147 | } |
1148 | ||
376253ec | 1149 | void pci_info(Monitor *mon) |
f2aa58c6 | 1150 | { |
e822a52a IY |
1151 | struct PCIHostBus *host; |
1152 | QLIST_FOREACH(host, &host_buses, next) { | |
1153 | pci_for_each_device(host->bus, 0, pci_info_device); | |
1154 | } | |
77d4bc34 | 1155 | } |
a41b2ff2 | 1156 | |
cb457d76 AL |
1157 | static const char * const pci_nic_models[] = { |
1158 | "ne2k_pci", | |
1159 | "i82551", | |
1160 | "i82557b", | |
1161 | "i82559er", | |
1162 | "rtl8139", | |
1163 | "e1000", | |
1164 | "pcnet", | |
1165 | "virtio", | |
1166 | NULL | |
1167 | }; | |
1168 | ||
9d07d757 PB |
1169 | static const char * const pci_nic_names[] = { |
1170 | "ne2k_pci", | |
1171 | "i82551", | |
1172 | "i82557b", | |
1173 | "i82559er", | |
1174 | "rtl8139", | |
1175 | "e1000", | |
1176 | "pcnet", | |
53c25cea | 1177 | "virtio-net-pci", |
cb457d76 AL |
1178 | NULL |
1179 | }; | |
1180 | ||
a41b2ff2 | 1181 | /* Initialize a PCI NIC. */ |
33e66b86 | 1182 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1183 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1184 | const char *default_devaddr) | |
a41b2ff2 | 1185 | { |
5607c388 | 1186 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1187 | PCIBus *bus; |
1188 | int devfn; | |
5607c388 | 1189 | PCIDevice *pci_dev; |
9d07d757 | 1190 | DeviceState *dev; |
cb457d76 AL |
1191 | int i; |
1192 | ||
07caea31 MA |
1193 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1194 | if (i < 0) | |
1195 | return NULL; | |
1196 | ||
1197 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1198 | if (!bus) { | |
1199 | qemu_error("Invalid PCI device address %s for device %s\n", | |
1200 | devaddr, pci_nic_names[i]); | |
1201 | return NULL; | |
1202 | } | |
1203 | ||
499cf102 | 1204 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1205 | dev = &pci_dev->qdev; |
dea7b3b9 MM |
1206 | if (nd->name) |
1207 | dev->id = qemu_strdup(nd->name); | |
1cc33683 | 1208 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1209 | if (qdev_init(dev) < 0) |
1210 | return NULL; | |
9ee05825 | 1211 | return pci_dev; |
a41b2ff2 PB |
1212 | } |
1213 | ||
07caea31 MA |
1214 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1215 | const char *default_devaddr) | |
1216 | { | |
1217 | PCIDevice *res; | |
1218 | ||
1219 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1220 | exit(0); | |
1221 | ||
1222 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1223 | if (!res) | |
1224 | exit(1); | |
1225 | return res; | |
1226 | } | |
1227 | ||
80b3ada7 PB |
1228 | typedef struct { |
1229 | PCIDevice dev; | |
03587182 GH |
1230 | PCIBus bus; |
1231 | uint32_t vid; | |
1232 | uint32_t did; | |
80b3ada7 PB |
1233 | } PCIBridge; |
1234 | ||
a0c7a97e IY |
1235 | |
1236 | static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) | |
1237 | { | |
1238 | pci_update_mappings(d); | |
1239 | } | |
1240 | ||
1241 | static void pci_bridge_update_mappings(PCIBus *b) | |
1242 | { | |
1243 | PCIBus *child; | |
1244 | ||
1245 | pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); | |
1246 | ||
1247 | QLIST_FOREACH(child, &b->child, sibling) { | |
1248 | pci_bridge_update_mappings(child); | |
1249 | } | |
1250 | } | |
1251 | ||
9596ebb7 | 1252 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
1253 | uint32_t address, uint32_t val, int len) |
1254 | { | |
80b3ada7 | 1255 | pci_default_write_config(d, address, val, len); |
a0c7a97e IY |
1256 | |
1257 | if (/* io base/limit */ | |
1258 | ranges_overlap(address, len, PCI_IO_BASE, 2) || | |
1259 | ||
1260 | /* memory base/limit, prefetchable base/limit and | |
1261 | io base/limit upper 16 */ | |
1262 | ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { | |
1263 | pci_bridge_update_mappings(d->bus); | |
1264 | } | |
80b3ada7 PB |
1265 | } |
1266 | ||
e822a52a | 1267 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 1268 | { |
e822a52a | 1269 | PCIBus *sec; |
3ae80618 | 1270 | |
e822a52a IY |
1271 | if (!bus) |
1272 | return NULL; | |
3ae80618 | 1273 | |
e822a52a IY |
1274 | if (pci_bus_num(bus) == bus_num) { |
1275 | return bus; | |
1276 | } | |
1277 | ||
1278 | /* try child bus */ | |
1279 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
070297d2 IY |
1280 | |
1281 | if (!bus->parent_dev /* pci host bridge */ | |
1282 | || (pci_bus_num(sec) <= bus_num && | |
1283 | bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { | |
e822a52a IY |
1284 | return pci_find_bus(sec, bus_num); |
1285 | } | |
1286 | } | |
1287 | ||
1288 | return NULL; | |
3ae80618 AL |
1289 | } |
1290 | ||
e822a52a | 1291 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
3ae80618 | 1292 | { |
e822a52a | 1293 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
1294 | |
1295 | if (!bus) | |
1296 | return NULL; | |
1297 | ||
1298 | return bus->devices[PCI_DEVFN(slot, function)]; | |
1299 | } | |
1300 | ||
03587182 | 1301 | static int pci_bridge_initfn(PCIDevice *dev) |
80b3ada7 | 1302 | { |
03587182 | 1303 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
480b9f24 | 1304 | |
03587182 GH |
1305 | pci_config_set_vendor_id(s->dev.config, s->vid); |
1306 | pci_config_set_device_id(s->dev.config, s->did); | |
480b9f24 | 1307 | |
74c01823 IY |
1308 | pci_set_word(dev->config + PCI_STATUS, |
1309 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
1310 | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); | |
d6318738 | 1311 | dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; |
74c01823 IY |
1312 | pci_set_word(dev->config + PCI_SEC_STATUS, |
1313 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
03587182 GH |
1314 | return 0; |
1315 | } | |
80b3ada7 | 1316 | |
e822a52a IY |
1317 | static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1318 | { | |
1319 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); | |
1320 | PCIBus *bus = &s->bus; | |
1321 | pci_unregister_secondary_bus(bus); | |
1322 | return 0; | |
1323 | } | |
1324 | ||
03587182 GH |
1325 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
1326 | pci_map_irq_fn map_irq, const char *name) | |
1327 | { | |
1328 | PCIDevice *dev; | |
1329 | PCIBridge *s; | |
1330 | ||
499cf102 | 1331 | dev = pci_create(bus, devfn, "pci-bridge"); |
03587182 GH |
1332 | qdev_prop_set_uint32(&dev->qdev, "vendorid", vid); |
1333 | qdev_prop_set_uint32(&dev->qdev, "deviceid", did); | |
e23a1b33 | 1334 | qdev_init_nofail(&dev->qdev); |
03587182 GH |
1335 | |
1336 | s = DO_UPCAST(PCIBridge, dev, dev); | |
e822a52a | 1337 | pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
03587182 | 1338 | return &s->bus; |
80b3ada7 | 1339 | } |
6b1b92d3 | 1340 | |
d6318738 MT |
1341 | PCIDevice *pci_bridge_get_device(PCIBus *bus) |
1342 | { | |
1343 | return bus->parent_dev; | |
1344 | } | |
1345 | ||
81a322d4 | 1346 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1347 | { |
1348 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1349 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1350 | PCIBus *bus; |
ee995ffb | 1351 | int devfn, rc; |
6b1b92d3 | 1352 | |
a9f49946 IY |
1353 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1354 | if (info->is_express) { | |
1355 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1356 | } | |
1357 | ||
02e2da45 | 1358 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 1359 | devfn = pci_dev->devfn; |
16eaedf2 | 1360 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
fb231628 IY |
1361 | info->config_read, info->config_write, |
1362 | info->header_type); | |
ea2138cf GH |
1363 | if (pci_dev == NULL) |
1364 | return -1; | |
ee995ffb GH |
1365 | rc = info->init(pci_dev); |
1366 | if (rc != 0) | |
1367 | return rc; | |
898829d5 GH |
1368 | |
1369 | /* rom loading */ | |
1370 | if (pci_dev->romfile == NULL && info->romfile != NULL) | |
1371 | pci_dev->romfile = qemu_strdup(info->romfile); | |
1372 | pci_add_option_rom(pci_dev); | |
1373 | ||
ee995ffb GH |
1374 | if (qdev->hotplugged) |
1375 | bus->hotplug(pci_dev, 1); | |
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | static int pci_unplug_device(DeviceState *qdev) | |
1380 | { | |
1381 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
1382 | ||
1383 | dev->bus->hotplug(dev, 0); | |
1384 | return 0; | |
6b1b92d3 PB |
1385 | } |
1386 | ||
0aab0d3a | 1387 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1388 | { |
02e2da45 | 1389 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1390 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1391 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1392 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1393 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1394 | } |
1395 | ||
0aab0d3a GH |
1396 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1397 | { | |
1398 | while (info->qdev.name) { | |
1399 | pci_qdev_register(info); | |
1400 | info++; | |
1401 | } | |
1402 | } | |
1403 | ||
499cf102 | 1404 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
6b1b92d3 PB |
1405 | { |
1406 | DeviceState *dev; | |
1407 | ||
02e2da45 | 1408 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1409 | qdev_prop_set_uint32(dev, "addr", devfn); |
71077c1c GH |
1410 | return DO_UPCAST(PCIDevice, qdev, dev); |
1411 | } | |
6b1b92d3 | 1412 | |
71077c1c GH |
1413 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1414 | { | |
499cf102 | 1415 | PCIDevice *dev = pci_create(bus, devfn, name); |
e23a1b33 | 1416 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1417 | return dev; |
6b1b92d3 | 1418 | } |
6f4cbd39 MT |
1419 | |
1420 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
1421 | { | |
a9f49946 | 1422 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1423 | int offset = PCI_CONFIG_HEADER_SIZE; |
1424 | int i; | |
a9f49946 | 1425 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1426 | if (pdev->used[i]) |
1427 | offset = i + 1; | |
1428 | else if (i - offset + 1 == size) | |
1429 | return offset; | |
1430 | return 0; | |
1431 | } | |
1432 | ||
1433 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1434 | uint8_t *prev_p) | |
1435 | { | |
1436 | uint8_t next, prev; | |
1437 | ||
1438 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1439 | return 0; | |
1440 | ||
1441 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1442 | prev = next + PCI_CAP_LIST_NEXT) | |
1443 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1444 | break; | |
1445 | ||
1446 | if (prev_p) | |
1447 | *prev_p = prev; | |
1448 | return next; | |
1449 | } | |
1450 | ||
72bb3c75 AL |
1451 | static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1452 | { | |
1453 | cpu_register_physical_memory(addr, size, pdev->rom_offset); | |
1454 | } | |
1455 | ||
1456 | /* Add an option rom for the device */ | |
898829d5 | 1457 | static int pci_add_option_rom(PCIDevice *pdev) |
72bb3c75 AL |
1458 | { |
1459 | int size; | |
1460 | char *path; | |
1461 | void *ptr; | |
1462 | ||
898829d5 GH |
1463 | if (!pdev->romfile) |
1464 | return 0; | |
1465 | if (strlen(pdev->romfile) == 0) | |
1466 | return 0; | |
1467 | ||
027866ce GH |
1468 | if (!pdev->rom_bar) { |
1469 | /* | |
1470 | * Load rom via fw_cfg instead of creating a rom bar, | |
1471 | * for 0.11 compatibility. | |
1472 | */ | |
1473 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1474 | if (class == 0x0300) { | |
1475 | rom_add_vga(pdev->romfile); | |
1476 | } else { | |
1477 | rom_add_option(pdev->romfile); | |
1478 | } | |
1479 | return 0; | |
1480 | } | |
1481 | ||
898829d5 | 1482 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
72bb3c75 | 1483 | if (path == NULL) { |
898829d5 | 1484 | path = qemu_strdup(pdev->romfile); |
72bb3c75 AL |
1485 | } |
1486 | ||
1487 | size = get_image_size(path); | |
898829d5 GH |
1488 | if (size < 0) { |
1489 | qemu_error("%s: failed to find romfile \"%s\"\n", __FUNCTION__, | |
1490 | pdev->romfile); | |
1491 | return -1; | |
1492 | } | |
72bb3c75 AL |
1493 | if (size & (size - 1)) { |
1494 | size = 1 << qemu_fls(size); | |
1495 | } | |
1496 | ||
1497 | pdev->rom_offset = qemu_ram_alloc(size); | |
1498 | ||
1499 | ptr = qemu_get_ram_ptr(pdev->rom_offset); | |
1500 | load_image(path, ptr); | |
1501 | qemu_free(path); | |
1502 | ||
1503 | pci_register_bar(pdev, PCI_ROM_SLOT, size, | |
1504 | 0, pci_map_option_rom); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
6f4cbd39 MT |
1509 | /* Reserve space and add capability to the linked list in pci config space */ |
1510 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1511 | { | |
1512 | uint8_t offset = pci_find_space(pdev, size); | |
1513 | uint8_t *config = pdev->config + offset; | |
1514 | if (!offset) | |
1515 | return -ENOSPC; | |
1516 | config[PCI_CAP_LIST_ID] = cap_id; | |
1517 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1518 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1519 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1520 | memset(pdev->used + offset, 0xFF, size); | |
1521 | /* Make capability read-only by default */ | |
1522 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1523 | /* Check capability by default */ |
1524 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1525 | return offset; |
1526 | } | |
1527 | ||
1528 | /* Unlink capability from the pci config space. */ | |
1529 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1530 | { | |
1531 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1532 | if (!offset) | |
1533 | return; | |
1534 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
1535 | /* Make capability writeable again */ | |
1536 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
1537 | /* Clear cmask as device-specific registers can't be checked */ |
1538 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1539 | memset(pdev->used + offset, 0, size); |
1540 | ||
1541 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1542 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1543 | } | |
1544 | ||
1545 | /* Reserve space for capability at a known offset (to call after load). */ | |
1546 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1547 | { | |
1548 | memset(pdev->used + offset, 0xff, size); | |
1549 | } | |
1550 | ||
1551 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1552 | { | |
1553 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1554 | } | |
10c4c98a GH |
1555 | |
1556 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1557 | { | |
1558 | PCIDevice *d = (PCIDevice *)dev; | |
1559 | const pci_class_desc *desc; | |
1560 | char ctxt[64]; | |
1561 | PCIIORegion *r; | |
1562 | int i, class; | |
1563 | ||
b0ff8eb2 | 1564 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1565 | desc = pci_class_descriptions; |
1566 | while (desc->desc && class != desc->class) | |
1567 | desc++; | |
1568 | if (desc->desc) { | |
1569 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1570 | } else { | |
1571 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1572 | } | |
1573 | ||
1574 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1575 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1576 | indent, "", ctxt, | |
e822a52a IY |
1577 | d->config[PCI_SECONDARY_BUS], |
1578 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), | |
b0ff8eb2 IY |
1579 | pci_get_word(d->config + PCI_VENDOR_ID), |
1580 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1581 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1582 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1583 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1584 | r = &d->io_regions[i]; | |
1585 | if (!r->size) | |
1586 | continue; | |
89e8b13c IY |
1587 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1588 | " [0x%"FMT_PCIBUS"]\n", | |
1589 | indent, "", | |
0392a017 | 1590 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1591 | r->addr, r->addr + r->size - 1); |
1592 | } | |
1593 | } | |
03587182 GH |
1594 | |
1595 | static PCIDeviceInfo bridge_info = { | |
1596 | .qdev.name = "pci-bridge", | |
1597 | .qdev.size = sizeof(PCIBridge), | |
1598 | .init = pci_bridge_initfn, | |
e822a52a | 1599 | .exit = pci_bridge_exitfn, |
03587182 GH |
1600 | .config_write = pci_bridge_write_config, |
1601 | .qdev.props = (Property[]) { | |
1602 | DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), | |
1603 | DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), | |
1604 | DEFINE_PROP_END_OF_LIST(), | |
1605 | } | |
1606 | }; | |
1607 | ||
1608 | static void pci_register_devices(void) | |
1609 | { | |
1610 | pci_qdev_register(&bridge_info); | |
1611 | } | |
1612 | ||
1613 | device_init(pci_register_devices) |