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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "console.h" | |
27 | #include "net.h" | |
fbe78f4f | 28 | #include "virtio-net.h" |
880345c4 | 29 | #include "sysemu.h" |
69b91039 FB |
30 | |
31 | //#define DEBUG_PCI | |
32 | ||
30468f78 FB |
33 | struct PCIBus { |
34 | int bus_num; | |
35 | int devfn_min; | |
502a5395 | 36 | pci_set_irq_fn set_irq; |
d2b59317 | 37 | pci_map_irq_fn map_irq; |
30468f78 | 38 | uint32_t config_reg; /* XXX: suppress */ |
384d8876 FB |
39 | /* low level pic */ |
40 | SetIRQFunc *low_set_irq; | |
d537cf6c | 41 | qemu_irq *irq_opaque; |
30468f78 | 42 | PCIDevice *devices[256]; |
80b3ada7 PB |
43 | PCIDevice *parent_dev; |
44 | PCIBus *next; | |
d2b59317 PB |
45 | /* The bus IRQ state is the logical OR of the connected devices. |
46 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 47 | int nirq; |
80b3ada7 | 48 | int irq_count[]; |
30468f78 | 49 | }; |
69b91039 | 50 | |
1941d19c | 51 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 52 | static void pci_set_irq(void *opaque, int irq_num, int level); |
1941d19c | 53 | |
69b91039 | 54 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
55 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
56 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
0ac32c83 | 57 | static int pci_irq_index; |
30468f78 FB |
58 | static PCIBus *first_bus; |
59 | ||
52fc1d83 AZ |
60 | static void pcibus_save(QEMUFile *f, void *opaque) |
61 | { | |
62 | PCIBus *bus = (PCIBus *)opaque; | |
63 | int i; | |
64 | ||
65 | qemu_put_be32(f, bus->nirq); | |
66 | for (i = 0; i < bus->nirq; i++) | |
67 | qemu_put_be32(f, bus->irq_count[i]); | |
68 | } | |
69 | ||
70 | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) | |
71 | { | |
72 | PCIBus *bus = (PCIBus *)opaque; | |
73 | int i, nirq; | |
74 | ||
75 | if (version_id != 1) | |
76 | return -EINVAL; | |
77 | ||
78 | nirq = qemu_get_be32(f); | |
79 | if (bus->nirq != nirq) { | |
80 | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n", | |
81 | nirq, bus->nirq); | |
82 | return -EINVAL; | |
83 | } | |
84 | ||
85 | for (i = 0; i < nirq; i++) | |
86 | bus->irq_count[i] = qemu_get_be32(f); | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
d2b59317 | 91 | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
d537cf6c | 92 | qemu_irq *pic, int devfn_min, int nirq) |
30468f78 FB |
93 | { |
94 | PCIBus *bus; | |
52fc1d83 AZ |
95 | static int nbus = 0; |
96 | ||
80b3ada7 | 97 | bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
502a5395 | 98 | bus->set_irq = set_irq; |
d2b59317 | 99 | bus->map_irq = map_irq; |
502a5395 PB |
100 | bus->irq_opaque = pic; |
101 | bus->devfn_min = devfn_min; | |
52fc1d83 | 102 | bus->nirq = nirq; |
30468f78 | 103 | first_bus = bus; |
52fc1d83 | 104 | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
30468f78 FB |
105 | return bus; |
106 | } | |
69b91039 | 107 | |
9596ebb7 | 108 | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq) |
80b3ada7 PB |
109 | { |
110 | PCIBus *bus; | |
111 | bus = qemu_mallocz(sizeof(PCIBus)); | |
112 | bus->map_irq = map_irq; | |
113 | bus->parent_dev = dev; | |
114 | bus->next = dev->bus->next; | |
115 | dev->bus->next = bus; | |
116 | return bus; | |
117 | } | |
118 | ||
502a5395 PB |
119 | int pci_bus_num(PCIBus *s) |
120 | { | |
121 | return s->bus_num; | |
122 | } | |
123 | ||
1941d19c | 124 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
30ca2aab | 125 | { |
52fc1d83 AZ |
126 | int i; |
127 | ||
128 | qemu_put_be32(f, 2); /* PCI device version */ | |
30ca2aab | 129 | qemu_put_buffer(f, s->config, 256); |
52fc1d83 AZ |
130 | for (i = 0; i < 4; i++) |
131 | qemu_put_be32(f, s->irq_state[i]); | |
30ca2aab FB |
132 | } |
133 | ||
1941d19c | 134 | int pci_device_load(PCIDevice *s, QEMUFile *f) |
30ca2aab | 135 | { |
1941d19c | 136 | uint32_t version_id; |
52fc1d83 AZ |
137 | int i; |
138 | ||
1941d19c | 139 | version_id = qemu_get_be32(f); |
52fc1d83 | 140 | if (version_id > 2) |
30ca2aab | 141 | return -EINVAL; |
30ca2aab | 142 | qemu_get_buffer(f, s->config, 256); |
1941d19c | 143 | pci_update_mappings(s); |
52fc1d83 AZ |
144 | |
145 | if (version_id >= 2) | |
146 | for (i = 0; i < 4; i ++) | |
147 | s->irq_state[i] = qemu_get_be32(f); | |
148 | ||
30ca2aab FB |
149 | return 0; |
150 | } | |
151 | ||
d350d97d AL |
152 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
153 | { | |
154 | uint16_t *id; | |
155 | ||
156 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
157 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
158 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
159 | return 0; | |
160 | } | |
161 | ||
880345c4 AL |
162 | /* |
163 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
164 | */ | |
165 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
166 | { | |
167 | const char *p; | |
168 | char *e; | |
169 | unsigned long val; | |
170 | unsigned long dom = 0, bus = 0; | |
171 | unsigned slot = 0; | |
172 | ||
173 | p = addr; | |
174 | val = strtoul(p, &e, 16); | |
175 | if (e == p) | |
176 | return -1; | |
177 | if (*e == ':') { | |
178 | bus = val; | |
179 | p = e + 1; | |
180 | val = strtoul(p, &e, 16); | |
181 | if (e == p) | |
182 | return -1; | |
183 | if (*e == ':') { | |
184 | dom = bus; | |
185 | bus = val; | |
186 | p = e + 1; | |
187 | val = strtoul(p, &e, 16); | |
188 | if (e == p) | |
189 | return -1; | |
190 | } | |
191 | } | |
192 | ||
193 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
194 | return -1; | |
195 | ||
196 | slot = val; | |
197 | ||
198 | if (*e) | |
199 | return -1; | |
200 | ||
201 | /* Note: QEMU doesn't implement domains other than 0 */ | |
202 | if (dom != 0 || pci_find_bus(bus) == NULL) | |
203 | return -1; | |
204 | ||
205 | *domp = dom; | |
206 | *busp = bus; | |
207 | *slotp = slot; | |
208 | return 0; | |
209 | } | |
210 | ||
211 | int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
212 | { | |
213 | char devaddr[32]; | |
214 | ||
215 | if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) | |
216 | return -1; | |
217 | ||
218 | return pci_parse_devaddr(devaddr, domp, busp, slotp); | |
219 | } | |
220 | ||
221 | int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
222 | { | |
223 | char devaddr[32]; | |
224 | ||
225 | if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) | |
226 | return -1; | |
227 | ||
228 | if (!strcmp(devaddr, "auto")) { | |
229 | *domp = *busp = 0; | |
230 | *slotp = -1; | |
231 | /* want to support dom/bus auto-assign at some point */ | |
232 | return 0; | |
233 | } | |
234 | ||
235 | return pci_parse_devaddr(devaddr, domp, busp, slotp); | |
236 | } | |
237 | ||
69b91039 | 238 | /* -1 for devfn means auto assign */ |
5fafdf24 | 239 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
30468f78 | 240 | int instance_size, int devfn, |
5fafdf24 | 241 | PCIConfigReadFunc *config_read, |
69b91039 FB |
242 | PCIConfigWriteFunc *config_write) |
243 | { | |
30468f78 | 244 | PCIDevice *pci_dev; |
69b91039 | 245 | |
0ac32c83 FB |
246 | if (pci_irq_index >= PCI_DEVICES_MAX) |
247 | return NULL; | |
3b46e624 | 248 | |
69b91039 | 249 | if (devfn < 0) { |
30468f78 FB |
250 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
251 | if (!bus->devices[devfn]) | |
69b91039 FB |
252 | goto found; |
253 | } | |
254 | return NULL; | |
255 | found: ; | |
256 | } | |
257 | pci_dev = qemu_mallocz(instance_size); | |
30468f78 | 258 | pci_dev->bus = bus; |
69b91039 FB |
259 | pci_dev->devfn = devfn; |
260 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d2b59317 | 261 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
d350d97d | 262 | pci_set_default_subsystem_id(pci_dev); |
0ac32c83 FB |
263 | |
264 | if (!config_read) | |
265 | config_read = pci_default_read_config; | |
266 | if (!config_write) | |
267 | config_write = pci_default_write_config; | |
69b91039 FB |
268 | pci_dev->config_read = config_read; |
269 | pci_dev->config_write = config_write; | |
0ac32c83 | 270 | pci_dev->irq_index = pci_irq_index++; |
30468f78 | 271 | bus->devices[devfn] = pci_dev; |
d537cf6c | 272 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); |
69b91039 FB |
273 | return pci_dev; |
274 | } | |
275 | ||
5851e08c AL |
276 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
277 | { | |
278 | return addr + pci_mem_base; | |
279 | } | |
280 | ||
281 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
282 | { | |
283 | PCIIORegion *r; | |
284 | int i; | |
285 | ||
286 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
287 | r = &pci_dev->io_regions[i]; | |
288 | if (!r->size || r->addr == -1) | |
289 | continue; | |
290 | if (r->type == PCI_ADDRESS_SPACE_IO) { | |
291 | isa_unassign_ioport(r->addr, r->size); | |
292 | } else { | |
293 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
294 | r->size, | |
295 | IO_MEM_UNASSIGNED); | |
296 | } | |
297 | } | |
298 | } | |
299 | ||
300 | int pci_unregister_device(PCIDevice *pci_dev) | |
301 | { | |
302 | int ret = 0; | |
303 | ||
304 | if (pci_dev->unregister) | |
305 | ret = pci_dev->unregister(pci_dev); | |
306 | if (ret) | |
307 | return ret; | |
308 | ||
309 | pci_unregister_io_regions(pci_dev); | |
310 | ||
311 | qemu_free_irqs(pci_dev->irq); | |
312 | pci_irq_index--; | |
313 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
314 | qemu_free(pci_dev); | |
315 | return 0; | |
316 | } | |
317 | ||
5fafdf24 TS |
318 | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
319 | uint32_t size, int type, | |
69b91039 FB |
320 | PCIMapIORegionFunc *map_func) |
321 | { | |
322 | PCIIORegion *r; | |
d7ce493a | 323 | uint32_t addr; |
69b91039 | 324 | |
8a8696a3 | 325 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 326 | return; |
a4c20c6a AL |
327 | |
328 | if (size & (size-1)) { | |
329 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
330 | "type=0x%x, size=0x%x\n", type, size); | |
331 | exit(1); | |
332 | } | |
333 | ||
69b91039 FB |
334 | r = &pci_dev->io_regions[region_num]; |
335 | r->addr = -1; | |
336 | r->size = size; | |
337 | r->type = type; | |
338 | r->map_func = map_func; | |
d7ce493a PB |
339 | if (region_num == PCI_ROM_SLOT) { |
340 | addr = 0x30; | |
341 | } else { | |
342 | addr = 0x10 + region_num * 4; | |
343 | } | |
344 | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); | |
69b91039 FB |
345 | } |
346 | ||
0ac32c83 FB |
347 | static void pci_update_mappings(PCIDevice *d) |
348 | { | |
349 | PCIIORegion *r; | |
350 | int cmd, i; | |
8a8696a3 | 351 | uint32_t last_addr, new_addr, config_ofs; |
3b46e624 | 352 | |
0ac32c83 | 353 | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
8a8696a3 | 354 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 355 | r = &d->io_regions[i]; |
8a8696a3 FB |
356 | if (i == PCI_ROM_SLOT) { |
357 | config_ofs = 0x30; | |
358 | } else { | |
359 | config_ofs = 0x10 + i * 4; | |
360 | } | |
0ac32c83 FB |
361 | if (r->size != 0) { |
362 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
363 | if (cmd & PCI_COMMAND_IO) { | |
5fafdf24 | 364 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 | 365 | config_ofs)); |
0ac32c83 FB |
366 | new_addr = new_addr & ~(r->size - 1); |
367 | last_addr = new_addr + r->size - 1; | |
368 | /* NOTE: we have only 64K ioports on PC */ | |
369 | if (last_addr <= new_addr || new_addr == 0 || | |
370 | last_addr >= 0x10000) { | |
371 | new_addr = -1; | |
372 | } | |
373 | } else { | |
374 | new_addr = -1; | |
375 | } | |
376 | } else { | |
377 | if (cmd & PCI_COMMAND_MEMORY) { | |
5fafdf24 | 378 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 FB |
379 | config_ofs)); |
380 | /* the ROM slot has a specific enable bit */ | |
381 | if (i == PCI_ROM_SLOT && !(new_addr & 1)) | |
382 | goto no_mem_map; | |
0ac32c83 FB |
383 | new_addr = new_addr & ~(r->size - 1); |
384 | last_addr = new_addr + r->size - 1; | |
385 | /* NOTE: we do not support wrapping */ | |
386 | /* XXX: as we cannot support really dynamic | |
387 | mappings, we handle specific values as invalid | |
388 | mappings. */ | |
389 | if (last_addr <= new_addr || new_addr == 0 || | |
390 | last_addr == -1) { | |
391 | new_addr = -1; | |
392 | } | |
393 | } else { | |
8a8696a3 | 394 | no_mem_map: |
0ac32c83 FB |
395 | new_addr = -1; |
396 | } | |
397 | } | |
398 | /* now do the real mapping */ | |
399 | if (new_addr != r->addr) { | |
400 | if (r->addr != -1) { | |
401 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
402 | int class; | |
403 | /* NOTE: specific hack for IDE in PC case: | |
404 | only one byte must be mapped. */ | |
405 | class = d->config[0x0a] | (d->config[0x0b] << 8); | |
406 | if (class == 0x0101 && r->size == 4) { | |
407 | isa_unassign_ioport(r->addr + 2, 1); | |
408 | } else { | |
409 | isa_unassign_ioport(r->addr, r->size); | |
410 | } | |
411 | } else { | |
502a5395 | 412 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
5fafdf24 | 413 | r->size, |
0ac32c83 | 414 | IO_MEM_UNASSIGNED); |
f65ed4c1 | 415 | qemu_unregister_coalesced_mmio(r->addr, r->size); |
0ac32c83 FB |
416 | } |
417 | } | |
418 | r->addr = new_addr; | |
419 | if (r->addr != -1) { | |
420 | r->map_func(d, i, r->addr, r->size, r->type); | |
421 | } | |
422 | } | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
5fafdf24 | 427 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 428 | uint32_t address, int len) |
69b91039 | 429 | { |
0ac32c83 | 430 | uint32_t val; |
a2d4e44b | 431 | |
0ac32c83 | 432 | switch(len) { |
0ac32c83 FB |
433 | default: |
434 | case 4: | |
a2d4e44b TS |
435 | if (address <= 0xfc) { |
436 | val = le32_to_cpu(*(uint32_t *)(d->config + address)); | |
437 | break; | |
438 | } | |
439 | /* fall through */ | |
440 | case 2: | |
441 | if (address <= 0xfe) { | |
442 | val = le16_to_cpu(*(uint16_t *)(d->config + address)); | |
443 | break; | |
444 | } | |
445 | /* fall through */ | |
446 | case 1: | |
447 | val = d->config[address]; | |
0ac32c83 FB |
448 | break; |
449 | } | |
450 | return val; | |
451 | } | |
452 | ||
5fafdf24 | 453 | void pci_default_write_config(PCIDevice *d, |
0ac32c83 FB |
454 | uint32_t address, uint32_t val, int len) |
455 | { | |
456 | int can_write, i; | |
7bf5be70 | 457 | uint32_t end, addr; |
0ac32c83 | 458 | |
5fafdf24 | 459 | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
8a8696a3 | 460 | (address >= 0x30 && address < 0x34))) { |
0ac32c83 FB |
461 | PCIIORegion *r; |
462 | int reg; | |
463 | ||
8a8696a3 FB |
464 | if ( address >= 0x30 ) { |
465 | reg = PCI_ROM_SLOT; | |
466 | }else{ | |
467 | reg = (address - 0x10) >> 2; | |
468 | } | |
0ac32c83 FB |
469 | r = &d->io_regions[reg]; |
470 | if (r->size == 0) | |
471 | goto default_config; | |
472 | /* compute the stored value */ | |
8a8696a3 FB |
473 | if (reg == PCI_ROM_SLOT) { |
474 | /* keep ROM enable bit */ | |
475 | val &= (~(r->size - 1)) | 1; | |
476 | } else { | |
477 | val &= ~(r->size - 1); | |
478 | val |= r->type; | |
479 | } | |
480 | *(uint32_t *)(d->config + address) = cpu_to_le32(val); | |
0ac32c83 | 481 | pci_update_mappings(d); |
69b91039 | 482 | return; |
0ac32c83 FB |
483 | } |
484 | default_config: | |
485 | /* not efficient, but simple */ | |
7bf5be70 | 486 | addr = address; |
0ac32c83 FB |
487 | for(i = 0; i < len; i++) { |
488 | /* default read/write accesses */ | |
1f62d938 | 489 | switch(d->config[0x0e]) { |
0ac32c83 | 490 | case 0x00: |
1f62d938 FB |
491 | case 0x80: |
492 | switch(addr) { | |
493 | case 0x00: | |
494 | case 0x01: | |
495 | case 0x02: | |
496 | case 0x03: | |
497 | case 0x08: | |
498 | case 0x09: | |
499 | case 0x0a: | |
500 | case 0x0b: | |
501 | case 0x0e: | |
502 | case 0x10 ... 0x27: /* base */ | |
8098ed41 | 503 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
1f62d938 FB |
504 | case 0x30 ... 0x33: /* rom */ |
505 | case 0x3d: | |
506 | can_write = 0; | |
507 | break; | |
508 | default: | |
509 | can_write = 1; | |
510 | break; | |
511 | } | |
0ac32c83 FB |
512 | break; |
513 | default: | |
1f62d938 FB |
514 | case 0x01: |
515 | switch(addr) { | |
516 | case 0x00: | |
517 | case 0x01: | |
518 | case 0x02: | |
519 | case 0x03: | |
520 | case 0x08: | |
521 | case 0x09: | |
522 | case 0x0a: | |
523 | case 0x0b: | |
524 | case 0x0e: | |
8098ed41 | 525 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
1f62d938 FB |
526 | case 0x38 ... 0x3b: /* rom */ |
527 | case 0x3d: | |
528 | can_write = 0; | |
529 | break; | |
530 | default: | |
531 | can_write = 1; | |
532 | break; | |
533 | } | |
0ac32c83 FB |
534 | break; |
535 | } | |
536 | if (can_write) { | |
8098ed41 AJ |
537 | /* Mask out writes to reserved bits in registers */ |
538 | switch (addr) { | |
475dc65f AJ |
539 | case 0x05: |
540 | val &= ~PCI_COMMAND_RESERVED_MASK_HI; | |
541 | break; | |
8098ed41 AJ |
542 | case 0x06: |
543 | val &= ~PCI_STATUS_RESERVED_MASK_LO; | |
544 | break; | |
545 | case 0x07: | |
546 | val &= ~PCI_STATUS_RESERVED_MASK_HI; | |
547 | break; | |
548 | } | |
7bf5be70 | 549 | d->config[addr] = val; |
0ac32c83 | 550 | } |
a2d4e44b TS |
551 | if (++addr > 0xff) |
552 | break; | |
0ac32c83 FB |
553 | val >>= 8; |
554 | } | |
555 | ||
556 | end = address + len; | |
557 | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { | |
558 | /* if the command register is modified, we must modify the mappings */ | |
559 | pci_update_mappings(d); | |
69b91039 FB |
560 | } |
561 | } | |
562 | ||
502a5395 | 563 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
69b91039 | 564 | { |
30468f78 FB |
565 | PCIBus *s = opaque; |
566 | PCIDevice *pci_dev; | |
567 | int config_addr, bus_num; | |
3b46e624 | 568 | |
69b91039 FB |
569 | #if defined(DEBUG_PCI) && 0 |
570 | printf("pci_data_write: addr=%08x val=%08x len=%d\n", | |
502a5395 | 571 | addr, val, len); |
69b91039 | 572 | #endif |
502a5395 | 573 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
574 | while (s && s->bus_num != bus_num) |
575 | s = s->next; | |
576 | if (!s) | |
69b91039 | 577 | return; |
502a5395 | 578 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
579 | if (!pci_dev) |
580 | return; | |
502a5395 | 581 | config_addr = addr & 0xff; |
69b91039 FB |
582 | #if defined(DEBUG_PCI) |
583 | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n", | |
584 | pci_dev->name, config_addr, val, len); | |
585 | #endif | |
0ac32c83 | 586 | pci_dev->config_write(pci_dev, config_addr, val, len); |
69b91039 FB |
587 | } |
588 | ||
502a5395 | 589 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
69b91039 | 590 | { |
30468f78 FB |
591 | PCIBus *s = opaque; |
592 | PCIDevice *pci_dev; | |
593 | int config_addr, bus_num; | |
69b91039 FB |
594 | uint32_t val; |
595 | ||
502a5395 | 596 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
597 | while (s && s->bus_num != bus_num) |
598 | s= s->next; | |
599 | if (!s) | |
69b91039 | 600 | goto fail; |
502a5395 | 601 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
602 | if (!pci_dev) { |
603 | fail: | |
63ce9e0a FB |
604 | switch(len) { |
605 | case 1: | |
606 | val = 0xff; | |
607 | break; | |
608 | case 2: | |
609 | val = 0xffff; | |
610 | break; | |
611 | default: | |
612 | case 4: | |
613 | val = 0xffffffff; | |
614 | break; | |
615 | } | |
69b91039 FB |
616 | goto the_end; |
617 | } | |
502a5395 | 618 | config_addr = addr & 0xff; |
69b91039 FB |
619 | val = pci_dev->config_read(pci_dev, config_addr, len); |
620 | #if defined(DEBUG_PCI) | |
621 | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n", | |
622 | pci_dev->name, config_addr, val, len); | |
623 | #endif | |
624 | the_end: | |
625 | #if defined(DEBUG_PCI) && 0 | |
626 | printf("pci_data_read: addr=%08x val=%08x len=%d\n", | |
502a5395 | 627 | addr, val, len); |
69b91039 FB |
628 | #endif |
629 | return val; | |
630 | } | |
631 | ||
502a5395 PB |
632 | /***********************************************************/ |
633 | /* generic PCI irq support */ | |
30468f78 | 634 | |
502a5395 | 635 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 636 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 637 | { |
d537cf6c | 638 | PCIDevice *pci_dev = (PCIDevice *)opaque; |
80b3ada7 PB |
639 | PCIBus *bus; |
640 | int change; | |
3b46e624 | 641 | |
80b3ada7 PB |
642 | change = level - pci_dev->irq_state[irq_num]; |
643 | if (!change) | |
644 | return; | |
d2b59317 | 645 | |
d2b59317 | 646 | pci_dev->irq_state[irq_num] = level; |
5e966ce6 PB |
647 | for (;;) { |
648 | bus = pci_dev->bus; | |
80b3ada7 | 649 | irq_num = bus->map_irq(pci_dev, irq_num); |
5e966ce6 PB |
650 | if (bus->set_irq) |
651 | break; | |
80b3ada7 | 652 | pci_dev = bus->parent_dev; |
80b3ada7 PB |
653 | } |
654 | bus->irq_count[irq_num] += change; | |
d2b59317 | 655 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
69b91039 FB |
656 | } |
657 | ||
502a5395 PB |
658 | /***********************************************************/ |
659 | /* monitor info on PCI */ | |
0ac32c83 | 660 | |
6650ee6d PB |
661 | typedef struct { |
662 | uint16_t class; | |
663 | const char *desc; | |
664 | } pci_class_desc; | |
665 | ||
09bc878a | 666 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 667 | { |
4ca9c76f | 668 | { 0x0100, "SCSI controller"}, |
6650ee6d | 669 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
670 | { 0x0102, "Floppy controller"}, |
671 | { 0x0103, "IPI controller"}, | |
672 | { 0x0104, "RAID controller"}, | |
673 | { 0x0106, "SATA controller"}, | |
674 | { 0x0107, "SAS controller"}, | |
675 | { 0x0180, "Storage controller"}, | |
6650ee6d | 676 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
677 | { 0x0201, "Token Ring controller"}, |
678 | { 0x0202, "FDDI controller"}, | |
679 | { 0x0203, "ATM controller"}, | |
680 | { 0x0280, "Network controller"}, | |
6650ee6d | 681 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
682 | { 0x0301, "XGA controller"}, |
683 | { 0x0302, "3D controller"}, | |
684 | { 0x0380, "Display controller"}, | |
685 | { 0x0400, "Video controller"}, | |
686 | { 0x0401, "Audio controller"}, | |
687 | { 0x0402, "Phone"}, | |
688 | { 0x0480, "Multimedia controller"}, | |
689 | { 0x0500, "RAM controller"}, | |
690 | { 0x0501, "Flash controller"}, | |
691 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
692 | { 0x0600, "Host bridge"}, |
693 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
694 | { 0x0602, "EISA bridge"}, |
695 | { 0x0603, "MC bridge"}, | |
6650ee6d | 696 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
697 | { 0x0605, "PCMCIA bridge"}, |
698 | { 0x0606, "NUBUS bridge"}, | |
699 | { 0x0607, "CARDBUS bridge"}, | |
700 | { 0x0608, "RACEWAY bridge"}, | |
701 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
702 | { 0x0c03, "USB controller"}, |
703 | { 0, NULL} | |
704 | }; | |
705 | ||
502a5395 | 706 | static void pci_info_device(PCIDevice *d) |
30468f78 | 707 | { |
502a5395 PB |
708 | int i, class; |
709 | PCIIORegion *r; | |
09bc878a | 710 | const pci_class_desc *desc; |
30468f78 | 711 | |
502a5395 PB |
712 | term_printf(" Bus %2d, device %3d, function %d:\n", |
713 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); | |
714 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); | |
715 | term_printf(" "); | |
6650ee6d PB |
716 | desc = pci_class_descriptions; |
717 | while (desc->desc && class != desc->class) | |
718 | desc++; | |
719 | if (desc->desc) { | |
720 | term_printf("%s", desc->desc); | |
721 | } else { | |
502a5395 | 722 | term_printf("Class %04x", class); |
72cc6cfe | 723 | } |
502a5395 PB |
724 | term_printf(": PCI device %04x:%04x\n", |
725 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), | |
726 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); | |
30468f78 | 727 | |
502a5395 PB |
728 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
729 | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 730 | } |
80b3ada7 PB |
731 | if (class == 0x0604) { |
732 | term_printf(" BUS %d.\n", d->config[0x19]); | |
733 | } | |
502a5395 PB |
734 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
735 | r = &d->io_regions[i]; | |
736 | if (r->size != 0) { | |
737 | term_printf(" BAR%d: ", i); | |
738 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
5fafdf24 | 739 | term_printf("I/O at 0x%04x [0x%04x].\n", |
502a5395 PB |
740 | r->addr, r->addr + r->size - 1); |
741 | } else { | |
5fafdf24 | 742 | term_printf("32 bit memory at 0x%08x [0x%08x].\n", |
502a5395 PB |
743 | r->addr, r->addr + r->size - 1); |
744 | } | |
745 | } | |
77d4bc34 | 746 | } |
80b3ada7 PB |
747 | if (class == 0x0604 && d->config[0x19] != 0) { |
748 | pci_for_each_device(d->config[0x19], pci_info_device); | |
749 | } | |
384d8876 FB |
750 | } |
751 | ||
80b3ada7 | 752 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
384d8876 | 753 | { |
502a5395 | 754 | PCIBus *bus = first_bus; |
384d8876 | 755 | PCIDevice *d; |
502a5395 | 756 | int devfn; |
3b46e624 | 757 | |
80b3ada7 PB |
758 | while (bus && bus->bus_num != bus_num) |
759 | bus = bus->next; | |
502a5395 PB |
760 | if (bus) { |
761 | for(devfn = 0; devfn < 256; devfn++) { | |
762 | d = bus->devices[devfn]; | |
763 | if (d) | |
764 | fn(d); | |
765 | } | |
f2aa58c6 | 766 | } |
f2aa58c6 FB |
767 | } |
768 | ||
502a5395 | 769 | void pci_info(void) |
f2aa58c6 | 770 | { |
80b3ada7 | 771 | pci_for_each_device(0, pci_info_device); |
77d4bc34 | 772 | } |
a41b2ff2 | 773 | |
cb457d76 AL |
774 | static const char * const pci_nic_models[] = { |
775 | "ne2k_pci", | |
776 | "i82551", | |
777 | "i82557b", | |
778 | "i82559er", | |
779 | "rtl8139", | |
780 | "e1000", | |
781 | "pcnet", | |
782 | "virtio", | |
783 | NULL | |
784 | }; | |
785 | ||
72da4208 | 786 | typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int); |
cb457d76 AL |
787 | |
788 | static PCINICInitFn pci_nic_init_fns[] = { | |
789 | pci_ne2000_init, | |
790 | pci_i82551_init, | |
791 | pci_i82557b_init, | |
792 | pci_i82559er_init, | |
793 | pci_rtl8139_init, | |
794 | pci_e1000_init, | |
795 | pci_pcnet_init, | |
796 | virtio_net_init, | |
797 | NULL | |
798 | }; | |
799 | ||
a41b2ff2 | 800 | /* Initialize a PCI NIC. */ |
72da4208 | 801 | PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, |
cb457d76 | 802 | const char *default_model) |
a41b2ff2 | 803 | { |
72da4208 | 804 | PCIDevice *pci_dev; |
cb457d76 AL |
805 | int i; |
806 | ||
807 | qemu_check_nic_model_list(nd, pci_nic_models, default_model); | |
808 | ||
809 | for (i = 0; pci_nic_models[i]; i++) | |
72da4208 AL |
810 | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
811 | pci_dev = pci_nic_init_fns[i](bus, nd, devfn); | |
812 | if (pci_dev) | |
813 | nd->private = pci_dev; | |
814 | return pci_dev; | |
815 | } | |
816 | ||
817 | return NULL; | |
a41b2ff2 PB |
818 | } |
819 | ||
80b3ada7 PB |
820 | typedef struct { |
821 | PCIDevice dev; | |
822 | PCIBus *bus; | |
823 | } PCIBridge; | |
824 | ||
9596ebb7 | 825 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
826 | uint32_t address, uint32_t val, int len) |
827 | { | |
828 | PCIBridge *s = (PCIBridge *)d; | |
829 | ||
830 | if (address == 0x19 || (address == 0x18 && len > 1)) { | |
831 | if (address == 0x19) | |
832 | s->bus->bus_num = val & 0xff; | |
833 | else | |
834 | s->bus->bus_num = (val >> 8) & 0xff; | |
835 | #if defined(DEBUG_PCI) | |
836 | printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num); | |
837 | #endif | |
838 | } | |
839 | pci_default_write_config(d, address, val, len); | |
840 | } | |
841 | ||
3ae80618 AL |
842 | PCIBus *pci_find_bus(int bus_num) |
843 | { | |
844 | PCIBus *bus = first_bus; | |
845 | ||
846 | while (bus && bus->bus_num != bus_num) | |
847 | bus = bus->next; | |
848 | ||
849 | return bus; | |
850 | } | |
851 | ||
852 | PCIDevice *pci_find_device(int bus_num, int slot, int function) | |
853 | { | |
854 | PCIBus *bus = pci_find_bus(bus_num); | |
855 | ||
856 | if (!bus) | |
857 | return NULL; | |
858 | ||
859 | return bus->devices[PCI_DEVFN(slot, function)]; | |
860 | } | |
861 | ||
480b9f24 | 862 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
80b3ada7 PB |
863 | pci_map_irq_fn map_irq, const char *name) |
864 | { | |
865 | PCIBridge *s; | |
5fafdf24 | 866 | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), |
80b3ada7 | 867 | devfn, NULL, pci_bridge_write_config); |
480b9f24 BS |
868 | |
869 | pci_config_set_vendor_id(s->dev.config, vid); | |
870 | pci_config_set_device_id(s->dev.config, did); | |
871 | ||
80b3ada7 PB |
872 | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
873 | s->dev.config[0x05] = 0x00; | |
874 | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
875 | s->dev.config[0x07] = 0x00; // status = fast devsel | |
876 | s->dev.config[0x08] = 0x00; // revision | |
877 | s->dev.config[0x09] = 0x00; // programming i/f | |
173a543b | 878 | pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
80b3ada7 PB |
879 | s->dev.config[0x0D] = 0x10; // latency_timer |
880 | s->dev.config[0x0E] = 0x81; // header_type | |
881 | s->dev.config[0x1E] = 0xa0; // secondary status | |
882 | ||
883 | s->bus = pci_register_secondary_bus(&s->dev, map_irq); | |
884 | return s->bus; | |
885 | } |