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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
783753fd | 26 | #include "pci_bridge.h" |
cfb0a50a | 27 | #include "pci_internals.h" |
376253ec | 28 | #include "monitor.h" |
87ecb68b | 29 | #include "net.h" |
880345c4 | 30 | #include "sysemu.h" |
c2039bd0 | 31 | #include "loader.h" |
163c8a59 | 32 | #include "qemu-objects.h" |
bf1b0071 | 33 | #include "range.h" |
69b91039 FB |
34 | |
35 | //#define DEBUG_PCI | |
d8d2e079 | 36 | #ifdef DEBUG_PCI |
2e49d64a | 37 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
38 | #else |
39 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
40 | #endif | |
69b91039 | 41 | |
10c4c98a | 42 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 43 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 44 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
9bb33586 | 45 | static int pcibus_reset(BusState *qbus); |
10c4c98a | 46 | |
cfb0a50a | 47 | struct BusInfo pci_bus_info = { |
10c4c98a GH |
48 | .name = "PCI", |
49 | .size = sizeof(PCIBus), | |
50 | .print_dev = pcibus_dev_print, | |
4f43c1ff | 51 | .get_dev_path = pcibus_get_dev_path, |
5e0259e7 | 52 | .get_fw_dev_path = pcibus_get_fw_dev_path, |
9bb33586 | 53 | .reset = pcibus_reset, |
ee6847d1 | 54 | .props = (Property[]) { |
54586bd1 | 55 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
8c52c8f3 | 56 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), |
88169ddf | 57 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
49823868 IY |
58 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, |
59 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
b1aeb926 IY |
60 | DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, |
61 | QEMU_PCI_CAP_SERR_BITNR, true), | |
54586bd1 | 62 | DEFINE_PROP_END_OF_LIST() |
ee6847d1 | 63 | } |
30468f78 | 64 | }; |
69b91039 | 65 | |
1941d19c | 66 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 67 | static void pci_set_irq(void *opaque, int irq_num, int level); |
ab85ceb1 | 68 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
230741dc | 69 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 70 | |
d350d97d AL |
71 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
72 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
73 | |
74 | struct PCIHostBus { | |
75 | int domain; | |
76 | struct PCIBus *bus; | |
77 | QLIST_ENTRY(PCIHostBus) next; | |
78 | }; | |
79 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 80 | |
2d1e9f96 JQ |
81 | static const VMStateDescription vmstate_pcibus = { |
82 | .name = "PCIBUS", | |
83 | .version_id = 1, | |
84 | .minimum_version_id = 1, | |
85 | .minimum_version_id_old = 1, | |
86 | .fields = (VMStateField []) { | |
87 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 88 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 89 | VMSTATE_END_OF_LIST() |
52fc1d83 | 90 | } |
2d1e9f96 | 91 | }; |
52fc1d83 | 92 | |
b3b11697 | 93 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 94 | { |
b3b11697 IY |
95 | uint8_t type; |
96 | ||
97 | if (reg != PCI_ROM_SLOT) | |
98 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
99 | ||
100 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
101 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
102 | } |
103 | ||
d036bb21 MT |
104 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
105 | { | |
106 | return (d->irq_state >> irq_num) & 0x1; | |
107 | } | |
108 | ||
109 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
110 | { | |
111 | d->irq_state &= ~(0x1 << irq_num); | |
112 | d->irq_state |= level << irq_num; | |
113 | } | |
114 | ||
115 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
116 | { | |
117 | PCIBus *bus; | |
118 | for (;;) { | |
119 | bus = pci_dev->bus; | |
120 | irq_num = bus->map_irq(pci_dev, irq_num); | |
121 | if (bus->set_irq) | |
122 | break; | |
123 | pci_dev = bus->parent_dev; | |
124 | } | |
125 | bus->irq_count[irq_num] += change; | |
126 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
127 | } | |
128 | ||
9ddf8437 IY |
129 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
130 | { | |
131 | assert(irq_num >= 0); | |
132 | assert(irq_num < bus->nirq); | |
133 | return !!bus->irq_count[irq_num]; | |
134 | } | |
135 | ||
f9bf77dd MT |
136 | /* Update interrupt status bit in config space on interrupt |
137 | * state change. */ | |
138 | static void pci_update_irq_status(PCIDevice *dev) | |
139 | { | |
140 | if (dev->irq_state) { | |
141 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
142 | } else { | |
143 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
144 | } | |
145 | } | |
146 | ||
4c92325b IY |
147 | void pci_device_deassert_intx(PCIDevice *dev) |
148 | { | |
149 | int i; | |
150 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
151 | qemu_set_irq(dev->irq[i], 0); | |
152 | } | |
153 | } | |
154 | ||
0ead87c8 IY |
155 | /* |
156 | * This function is called on #RST and FLR. | |
157 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
158 | */ | |
159 | void pci_device_reset(PCIDevice *dev) | |
5330de09 | 160 | { |
c0b1905b | 161 | int r; |
9bb33586 IY |
162 | /* TODO: call the below unconditionally once all pci devices |
163 | * are qdevified */ | |
164 | if (dev->qdev.info) { | |
165 | qdev_reset_all(&dev->qdev); | |
166 | } | |
c0b1905b | 167 | |
d036bb21 | 168 | dev->irq_state = 0; |
f9bf77dd | 169 | pci_update_irq_status(dev); |
4c92325b | 170 | pci_device_deassert_intx(dev); |
ebabb67a | 171 | /* Clear all writable bits */ |
99443c21 | 172 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
173 | pci_get_word(dev->wmask + PCI_COMMAND) | |
174 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
175 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
176 | pci_get_word(dev->wmask + PCI_STATUS) | | |
177 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
c0b1905b MT |
178 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
179 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
180 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
181 | PCIIORegion *region = &dev->io_regions[r]; |
182 | if (!region->size) { | |
c0b1905b MT |
183 | continue; |
184 | } | |
71ebd6dc IY |
185 | |
186 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
187 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
188 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
189 | } else { | |
190 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
191 | } | |
c0b1905b MT |
192 | } |
193 | pci_update_mappings(dev); | |
5330de09 MT |
194 | } |
195 | ||
9bb33586 IY |
196 | /* |
197 | * Trigger pci bus reset under a given bus. | |
198 | * To be called on RST# assert. | |
199 | */ | |
200 | void pci_bus_reset(PCIBus *bus) | |
6eaa6847 | 201 | { |
6eaa6847 GN |
202 | int i; |
203 | ||
204 | for (i = 0; i < bus->nirq; i++) { | |
205 | bus->irq_count[i] = 0; | |
206 | } | |
5330de09 MT |
207 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
208 | if (bus->devices[i]) { | |
209 | pci_device_reset(bus->devices[i]); | |
210 | } | |
6eaa6847 GN |
211 | } |
212 | } | |
213 | ||
9bb33586 IY |
214 | static int pcibus_reset(BusState *qbus) |
215 | { | |
216 | pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); | |
217 | ||
218 | /* topology traverse is done by pci_bus_reset(). | |
219 | Tell qbus/qdev walker not to traverse the tree */ | |
220 | return 1; | |
221 | } | |
222 | ||
e822a52a IY |
223 | static void pci_host_bus_register(int domain, PCIBus *bus) |
224 | { | |
225 | struct PCIHostBus *host; | |
226 | host = qemu_mallocz(sizeof(*host)); | |
227 | host->domain = domain; | |
228 | host->bus = bus; | |
229 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
230 | } | |
231 | ||
c469e1dd | 232 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
233 | { |
234 | struct PCIHostBus *host; | |
235 | ||
236 | QLIST_FOREACH(host, &host_buses, next) { | |
237 | if (host->domain == domain) { | |
238 | return host->bus; | |
239 | } | |
240 | } | |
241 | ||
242 | return NULL; | |
243 | } | |
244 | ||
e075e788 IY |
245 | int pci_find_domain(const PCIBus *bus) |
246 | { | |
247 | PCIDevice *d; | |
248 | struct PCIHostBus *host; | |
249 | ||
250 | /* obtain root bus */ | |
251 | while ((d = bus->parent_dev) != NULL) { | |
252 | bus = d->bus; | |
253 | } | |
254 | ||
255 | QLIST_FOREACH(host, &host_buses, next) { | |
256 | if (host->bus == bus) { | |
257 | return host->domain; | |
258 | } | |
259 | } | |
260 | ||
261 | abort(); /* should not be reached */ | |
262 | return -1; | |
263 | } | |
264 | ||
21eea4b3 | 265 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
6f3279b5 | 266 | const char *name, uint8_t devfn_min) |
30468f78 | 267 | { |
21eea4b3 | 268 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
6fa84913 | 269 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 270 | bus->devfn_min = devfn_min; |
e822a52a IY |
271 | |
272 | /* host bridge */ | |
273 | QLIST_INIT(&bus->child); | |
274 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
275 | ||
0be71e32 | 276 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
21eea4b3 GH |
277 | } |
278 | ||
6f3279b5 | 279 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min) |
21eea4b3 GH |
280 | { |
281 | PCIBus *bus; | |
282 | ||
283 | bus = qemu_mallocz(sizeof(*bus)); | |
284 | bus->qbus.qdev_allocated = 1; | |
285 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
286 | return bus; | |
287 | } | |
288 | ||
289 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
290 | void *irq_opaque, int nirq) | |
291 | { | |
292 | bus->set_irq = set_irq; | |
293 | bus->map_irq = map_irq; | |
294 | bus->irq_opaque = irq_opaque; | |
295 | bus->nirq = nirq; | |
296 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
297 | } | |
298 | ||
87c30546 | 299 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
300 | { |
301 | bus->qbus.allow_hotplug = 1; | |
302 | bus->hotplug = hotplug; | |
87c30546 | 303 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
304 | } |
305 | ||
2e01c8cf BS |
306 | void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base) |
307 | { | |
308 | bus->mem_base = base; | |
309 | } | |
310 | ||
21eea4b3 GH |
311 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
312 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
6f3279b5 | 313 | void *irq_opaque, uint8_t devfn_min, int nirq) |
21eea4b3 GH |
314 | { |
315 | PCIBus *bus; | |
316 | ||
317 | bus = pci_bus_new(parent, name, devfn_min); | |
318 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
319 | return bus; |
320 | } | |
69b91039 | 321 | |
502a5395 PB |
322 | int pci_bus_num(PCIBus *s) |
323 | { | |
e94ff650 IY |
324 | if (!s->parent_dev) |
325 | return 0; /* pci host bridge */ | |
326 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
327 | } |
328 | ||
73534f2f | 329 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 330 | { |
73534f2f | 331 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 332 | uint8_t *config; |
52fc1d83 AZ |
333 | int i; |
334 | ||
a9f49946 IY |
335 | assert(size == pci_config_size(s)); |
336 | config = qemu_malloc(size); | |
337 | ||
338 | qemu_get_buffer(f, config, size); | |
339 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
340 | if ((config[i] ^ s->config[i]) & |
341 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
a9f49946 | 342 | qemu_free(config); |
bd4b65ee | 343 | return -EINVAL; |
a9f49946 IY |
344 | } |
345 | } | |
346 | memcpy(s->config, config, size); | |
bd4b65ee | 347 | |
1941d19c | 348 | pci_update_mappings(s); |
52fc1d83 | 349 | |
a9f49946 | 350 | qemu_free(config); |
30ca2aab FB |
351 | return 0; |
352 | } | |
353 | ||
73534f2f | 354 | /* just put buffer */ |
84e2e3eb | 355 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 356 | { |
dbe73d7f | 357 | const uint8_t **v = pv; |
a9f49946 | 358 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 359 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
360 | } |
361 | ||
362 | static VMStateInfo vmstate_info_pci_config = { | |
363 | .name = "pci config", | |
364 | .get = get_pci_config_device, | |
365 | .put = put_pci_config_device, | |
366 | }; | |
367 | ||
d036bb21 MT |
368 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
369 | { | |
c3f8f611 | 370 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
371 | uint32_t irq_state[PCI_NUM_PINS]; |
372 | int i; | |
373 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
374 | irq_state[i] = qemu_get_be32(f); | |
375 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
376 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
377 | irq_state[i]); | |
378 | return -EINVAL; | |
379 | } | |
380 | } | |
381 | ||
382 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
383 | pci_set_irq_state(s, i, irq_state[i]); | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
390 | { | |
391 | int i; | |
c3f8f611 | 392 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
393 | |
394 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
395 | qemu_put_be32(f, pci_irq_state(s, i)); | |
396 | } | |
397 | } | |
398 | ||
399 | static VMStateInfo vmstate_info_pci_irq_state = { | |
400 | .name = "pci irq state", | |
401 | .get = get_pci_irq_state, | |
402 | .put = put_pci_irq_state, | |
403 | }; | |
404 | ||
73534f2f JQ |
405 | const VMStateDescription vmstate_pci_device = { |
406 | .name = "PCIDevice", | |
407 | .version_id = 2, | |
408 | .minimum_version_id = 1, | |
409 | .minimum_version_id_old = 1, | |
410 | .fields = (VMStateField []) { | |
411 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
412 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
413 | vmstate_info_pci_config, | |
414 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
415 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
416 | vmstate_info_pci_irq_state, | |
417 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
418 | VMSTATE_END_OF_LIST() |
419 | } | |
420 | }; | |
421 | ||
422 | const VMStateDescription vmstate_pcie_device = { | |
423 | .name = "PCIDevice", | |
424 | .version_id = 2, | |
425 | .minimum_version_id = 1, | |
426 | .minimum_version_id_old = 1, | |
427 | .fields = (VMStateField []) { | |
428 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
429 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
430 | vmstate_info_pci_config, | |
431 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
432 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
433 | vmstate_info_pci_irq_state, | |
434 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
435 | VMSTATE_END_OF_LIST() |
436 | } | |
437 | }; | |
438 | ||
a9f49946 IY |
439 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
440 | { | |
441 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
442 | } | |
443 | ||
73534f2f JQ |
444 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
445 | { | |
f9bf77dd MT |
446 | /* Clear interrupt status bit: it is implicit |
447 | * in irq_state which we are saving. | |
448 | * This makes us compatible with old devices | |
449 | * which never set or clear this bit. */ | |
450 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 451 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
452 | /* Restore the interrupt status bit. */ |
453 | pci_update_irq_status(s); | |
73534f2f JQ |
454 | } |
455 | ||
456 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
457 | { | |
f9bf77dd MT |
458 | int ret; |
459 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
460 | /* Restore the interrupt status bit. */ | |
461 | pci_update_irq_status(s); | |
462 | return ret; | |
73534f2f JQ |
463 | } |
464 | ||
5e434f4e | 465 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 466 | { |
5e434f4e IY |
467 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
468 | pci_default_sub_vendor_id); | |
469 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
470 | pci_default_sub_device_id); | |
d350d97d AL |
471 | } |
472 | ||
880345c4 | 473 | /* |
43c945f1 IY |
474 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
475 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 476 | */ |
43c945f1 IY |
477 | int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
478 | unsigned int *slotp, unsigned int *funcp) | |
880345c4 AL |
479 | { |
480 | const char *p; | |
481 | char *e; | |
482 | unsigned long val; | |
483 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
484 | unsigned int slot = 0; |
485 | unsigned int func = 0; | |
880345c4 AL |
486 | |
487 | p = addr; | |
488 | val = strtoul(p, &e, 16); | |
489 | if (e == p) | |
490 | return -1; | |
491 | if (*e == ':') { | |
492 | bus = val; | |
493 | p = e + 1; | |
494 | val = strtoul(p, &e, 16); | |
495 | if (e == p) | |
496 | return -1; | |
497 | if (*e == ':') { | |
498 | dom = bus; | |
499 | bus = val; | |
500 | p = e + 1; | |
501 | val = strtoul(p, &e, 16); | |
502 | if (e == p) | |
503 | return -1; | |
504 | } | |
505 | } | |
506 | ||
880345c4 AL |
507 | slot = val; |
508 | ||
43c945f1 IY |
509 | if (funcp != NULL) { |
510 | if (*e != '.') | |
511 | return -1; | |
512 | ||
513 | p = e + 1; | |
514 | val = strtoul(p, &e, 16); | |
515 | if (e == p) | |
516 | return -1; | |
517 | ||
518 | func = val; | |
519 | } | |
520 | ||
521 | /* if funcp == NULL func is 0 */ | |
522 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
523 | return -1; | |
524 | ||
880345c4 AL |
525 | if (*e) |
526 | return -1; | |
527 | ||
528 | /* Note: QEMU doesn't implement domains other than 0 */ | |
c469e1dd | 529 | if (!pci_find_bus(pci_find_root_bus(dom), bus)) |
880345c4 AL |
530 | return -1; |
531 | ||
532 | *domp = dom; | |
533 | *busp = bus; | |
534 | *slotp = slot; | |
43c945f1 IY |
535 | if (funcp != NULL) |
536 | *funcp = func; | |
880345c4 AL |
537 | return 0; |
538 | } | |
539 | ||
e9283f8b JK |
540 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
541 | unsigned *slotp) | |
880345c4 | 542 | { |
e9283f8b JK |
543 | /* strip legacy tag */ |
544 | if (!strncmp(addr, "pci_addr=", 9)) { | |
545 | addr += 9; | |
546 | } | |
43c945f1 | 547 | if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { |
e9283f8b | 548 | monitor_printf(mon, "Invalid pci address\n"); |
880345c4 | 549 | return -1; |
e9283f8b JK |
550 | } |
551 | return 0; | |
880345c4 AL |
552 | } |
553 | ||
49bd1458 | 554 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
555 | { |
556 | int dom, bus; | |
557 | unsigned slot; | |
558 | ||
559 | if (!devaddr) { | |
560 | *devfnp = -1; | |
c469e1dd | 561 | return pci_find_bus(pci_find_root_bus(0), 0); |
5607c388 MA |
562 | } |
563 | ||
43c945f1 | 564 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
565 | return NULL; |
566 | } | |
567 | ||
6ff534b6 | 568 | *devfnp = PCI_DEVFN(slot, 0); |
e075e788 | 569 | return pci_find_bus(pci_find_root_bus(dom), bus); |
5607c388 MA |
570 | } |
571 | ||
bd4b65ee MT |
572 | static void pci_init_cmask(PCIDevice *dev) |
573 | { | |
574 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
575 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
576 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
577 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
578 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
579 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
580 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
581 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
582 | } | |
583 | ||
b7ee1603 MT |
584 | static void pci_init_wmask(PCIDevice *dev) |
585 | { | |
a9f49946 IY |
586 | int config_size = pci_config_size(dev); |
587 | ||
b7ee1603 MT |
588 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
589 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 590 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
591 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
592 | PCI_COMMAND_INTX_DISABLE); | |
b1aeb926 IY |
593 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
594 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); | |
595 | } | |
3e21ffc9 IY |
596 | |
597 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
598 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
599 | } |
600 | ||
89d437df IY |
601 | static void pci_init_w1cmask(PCIDevice *dev) |
602 | { | |
603 | /* | |
f6bdfcc9 | 604 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
605 | * long as their value is hardwired to 0. |
606 | */ | |
607 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
608 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
609 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
610 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
611 | } | |
612 | ||
fb231628 IY |
613 | static void pci_init_wmask_bridge(PCIDevice *d) |
614 | { | |
615 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
616 | PCI_SEC_LETENCY_TIMER */ | |
617 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
618 | ||
619 | /* base and limit */ | |
620 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
621 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
622 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
623 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
624 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
625 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
626 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
627 | PCI_PREF_RANGE_MASK & 0xffff); | |
628 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
629 | PCI_PREF_RANGE_MASK & 0xffff); | |
630 | ||
631 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
632 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
633 | ||
f6bdfcc9 MT |
634 | /* TODO: add this define to pci_regs.h in linux and then in qemu. */ |
635 | #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ | |
636 | #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ | |
637 | #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ | |
638 | #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ | |
639 | #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ | |
640 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, | |
641 | PCI_BRIDGE_CTL_PARITY | | |
642 | PCI_BRIDGE_CTL_SERR | | |
643 | PCI_BRIDGE_CTL_ISA | | |
644 | PCI_BRIDGE_CTL_VGA | | |
645 | PCI_BRIDGE_CTL_VGA_16BIT | | |
646 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
647 | PCI_BRIDGE_CTL_BUS_RESET | | |
648 | PCI_BRIDGE_CTL_FAST_BACK | | |
649 | PCI_BRIDGE_CTL_DISCARD | | |
650 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
651 | PCI_BRIDGE_CTL_DISCARD_SERR); |
652 | /* Below does not do anything as we never set this bit, put here for | |
653 | * completeness. */ | |
654 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
655 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
fb231628 IY |
656 | } |
657 | ||
6eab3de1 IY |
658 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
659 | { | |
660 | uint8_t slot = PCI_SLOT(dev->devfn); | |
661 | uint8_t func; | |
662 | ||
663 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
664 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
665 | } | |
666 | ||
667 | /* | |
b0cd712c | 668 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
669 | * - all functions must set the bit to 1. |
670 | * Example: Intel X53 | |
671 | * - function 0 must set the bit, but the rest function (> 0) | |
672 | * is allowed to leave the bit to 0. | |
673 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
674 | * | |
675 | * So OS (at least Linux) checks the bit of only function 0, | |
676 | * and doesn't see the bit of function > 0. | |
677 | * | |
678 | * The below check allows both interpretation. | |
679 | */ | |
680 | if (PCI_FUNC(dev->devfn)) { | |
681 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
682 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
683 | /* function 0 should set multifunction bit */ | |
684 | error_report("PCI: single function device can't be populated " | |
685 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
686 | return -1; | |
687 | } | |
688 | return 0; | |
689 | } | |
690 | ||
691 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
692 | return 0; | |
693 | } | |
694 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
695 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
696 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
697 | error_report("PCI: %x.0 indicates single function, " | |
698 | "but %x.%x is already populated.", | |
699 | slot, slot, func); | |
700 | return -1; | |
701 | } | |
702 | } | |
703 | return 0; | |
704 | } | |
705 | ||
a9f49946 IY |
706 | static void pci_config_alloc(PCIDevice *pci_dev) |
707 | { | |
708 | int config_size = pci_config_size(pci_dev); | |
709 | ||
710 | pci_dev->config = qemu_mallocz(config_size); | |
711 | pci_dev->cmask = qemu_mallocz(config_size); | |
712 | pci_dev->wmask = qemu_mallocz(config_size); | |
92ba5f51 | 713 | pci_dev->w1cmask = qemu_mallocz(config_size); |
a9f49946 IY |
714 | pci_dev->used = qemu_mallocz(config_size); |
715 | } | |
716 | ||
717 | static void pci_config_free(PCIDevice *pci_dev) | |
718 | { | |
719 | qemu_free(pci_dev->config); | |
720 | qemu_free(pci_dev->cmask); | |
721 | qemu_free(pci_dev->wmask); | |
92ba5f51 | 722 | qemu_free(pci_dev->w1cmask); |
a9f49946 IY |
723 | qemu_free(pci_dev->used); |
724 | } | |
725 | ||
69b91039 | 726 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
727 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
728 | const char *name, int devfn, | |
113f89df | 729 | const PCIDeviceInfo *info) |
69b91039 | 730 | { |
113f89df IY |
731 | PCIConfigReadFunc *config_read = info->config_read; |
732 | PCIConfigWriteFunc *config_write = info->config_write; | |
733 | ||
69b91039 | 734 | if (devfn < 0) { |
b47b0706 | 735 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 736 | devfn += PCI_FUNC_MAX) { |
30468f78 | 737 | if (!bus->devices[devfn]) |
69b91039 FB |
738 | goto found; |
739 | } | |
3709c1b7 | 740 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 741 | return NULL; |
69b91039 | 742 | found: ; |
07b7d053 | 743 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
744 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
745 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 746 | return NULL; |
69b91039 | 747 | } |
30468f78 | 748 | pci_dev->bus = bus; |
69b91039 FB |
749 | pci_dev->devfn = devfn; |
750 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 751 | pci_dev->irq_state = 0; |
a9f49946 | 752 | pci_config_alloc(pci_dev); |
fb231628 | 753 | |
113f89df IY |
754 | pci_config_set_vendor_id(pci_dev->config, info->vendor_id); |
755 | pci_config_set_device_id(pci_dev->config, info->device_id); | |
756 | pci_config_set_revision(pci_dev->config, info->revision); | |
757 | pci_config_set_class(pci_dev->config, info->class_id); | |
758 | ||
759 | if (!info->is_bridge) { | |
760 | if (info->subsystem_vendor_id || info->subsystem_id) { | |
761 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, | |
762 | info->subsystem_vendor_id); | |
763 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
764 | info->subsystem_id); | |
765 | } else { | |
766 | pci_set_default_subsystem_id(pci_dev); | |
767 | } | |
768 | } else { | |
769 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
770 | assert(!info->subsystem_vendor_id); | |
771 | assert(!info->subsystem_id); | |
fb231628 | 772 | } |
bd4b65ee | 773 | pci_init_cmask(pci_dev); |
b7ee1603 | 774 | pci_init_wmask(pci_dev); |
89d437df | 775 | pci_init_w1cmask(pci_dev); |
113f89df | 776 | if (info->is_bridge) { |
fb231628 IY |
777 | pci_init_wmask_bridge(pci_dev); |
778 | } | |
6eab3de1 IY |
779 | if (pci_init_multifunction(bus, pci_dev)) { |
780 | pci_config_free(pci_dev); | |
781 | return NULL; | |
782 | } | |
0ac32c83 FB |
783 | |
784 | if (!config_read) | |
785 | config_read = pci_default_read_config; | |
786 | if (!config_write) | |
787 | config_write = pci_default_write_config; | |
69b91039 FB |
788 | pci_dev->config_read = config_read; |
789 | pci_dev->config_write = config_write; | |
30468f78 | 790 | bus->devices[devfn] = pci_dev; |
e369cad7 | 791 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 792 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
793 | return pci_dev; |
794 | } | |
795 | ||
925fe64a AW |
796 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
797 | { | |
798 | qemu_free_irqs(pci_dev->irq); | |
799 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
800 | pci_config_free(pci_dev); | |
801 | } | |
802 | ||
113f89df | 803 | /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */ |
6b1b92d3 PB |
804 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
805 | int instance_size, int devfn, | |
806 | PCIConfigReadFunc *config_read, | |
807 | PCIConfigWriteFunc *config_write) | |
808 | { | |
809 | PCIDevice *pci_dev; | |
113f89df IY |
810 | PCIDeviceInfo info = { |
811 | .config_read = config_read, | |
812 | .config_write = config_write, | |
813 | }; | |
6b1b92d3 PB |
814 | |
815 | pci_dev = qemu_mallocz(instance_size); | |
113f89df | 816 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info); |
09e3acc6 GH |
817 | if (pci_dev == NULL) { |
818 | hw_error("PCI: can't register device\n"); | |
819 | } | |
6b1b92d3 PB |
820 | return pci_dev; |
821 | } | |
2e01c8cf BS |
822 | |
823 | static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus, | |
824 | target_phys_addr_t addr) | |
5851e08c | 825 | { |
2e01c8cf | 826 | return addr + bus->mem_base; |
5851e08c AL |
827 | } |
828 | ||
829 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
830 | { | |
831 | PCIIORegion *r; | |
832 | int i; | |
833 | ||
834 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
835 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 836 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 837 | continue; |
0392a017 | 838 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
a0c7a97e | 839 | isa_unassign_ioport(r->addr, r->filtered_size); |
5851e08c | 840 | } else { |
2e01c8cf BS |
841 | cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, |
842 | r->addr), | |
843 | r->filtered_size, | |
844 | IO_MEM_UNASSIGNED); | |
5851e08c AL |
845 | } |
846 | } | |
847 | } | |
848 | ||
a36a344d | 849 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 850 | { |
a36a344d | 851 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 852 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
853 | int ret = 0; |
854 | ||
e3936fa5 GH |
855 | if (info->exit) |
856 | ret = info->exit(pci_dev); | |
5851e08c AL |
857 | if (ret) |
858 | return ret; | |
859 | ||
860 | pci_unregister_io_regions(pci_dev); | |
230741dc | 861 | pci_del_option_rom(pci_dev); |
be7052c2 | 862 | qemu_free(pci_dev->romfile); |
925fe64a | 863 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
864 | return 0; |
865 | } | |
866 | ||
28c2c264 | 867 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
0bb750ef | 868 | pcibus_t size, uint8_t type, |
69b91039 FB |
869 | PCIMapIORegionFunc *map_func) |
870 | { | |
871 | PCIIORegion *r; | |
d7ce493a | 872 | uint32_t addr; |
5a9ff381 | 873 | uint64_t wmask; |
a4c20c6a | 874 | |
2bbb9c2f IY |
875 | assert(region_num >= 0); |
876 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
877 | if (size & (size-1)) { |
878 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 879 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
880 | exit(1); |
881 | } | |
882 | ||
69b91039 | 883 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 884 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 | 885 | r->size = size; |
a0c7a97e | 886 | r->filtered_size = size; |
69b91039 FB |
887 | r->type = type; |
888 | r->map_func = map_func; | |
17cbcb0b | 889 | r->ram_addr = IO_MEM_UNASSIGNED; |
b7ee1603 MT |
890 | |
891 | wmask = ~(size - 1); | |
b3b11697 | 892 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 893 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 894 | /* ROM enable bit is writable */ |
5330de09 | 895 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 896 | } |
b0ff8eb2 | 897 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
898 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
899 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
900 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
901 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
902 | } else { | |
903 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
904 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
905 | } | |
69b91039 FB |
906 | } |
907 | ||
17cbcb0b AK |
908 | static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num, |
909 | pcibus_t addr, pcibus_t size, int type) | |
910 | { | |
911 | cpu_register_physical_memory(addr, size, | |
912 | pci_dev->io_regions[region_num].ram_addr); | |
913 | } | |
914 | ||
915 | void pci_register_bar_simple(PCIDevice *pci_dev, int region_num, | |
916 | pcibus_t size, uint8_t attr, ram_addr_t ram_addr) | |
917 | { | |
918 | pci_register_bar(pci_dev, region_num, size, | |
919 | PCI_BASE_ADDRESS_SPACE_MEMORY | attr, | |
920 | pci_simple_bar_mapfunc); | |
921 | pci_dev->io_regions[region_num].ram_addr = ram_addr; | |
922 | } | |
923 | ||
a0c7a97e IY |
924 | static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, |
925 | uint8_t type) | |
926 | { | |
927 | pcibus_t base = *addr; | |
928 | pcibus_t limit = *addr + *size - 1; | |
929 | PCIDevice *br; | |
930 | ||
931 | for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { | |
932 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
933 | ||
934 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
935 | if (!(cmd & PCI_COMMAND_IO)) { | |
936 | goto no_map; | |
937 | } | |
938 | } else { | |
939 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
940 | goto no_map; | |
941 | } | |
942 | } | |
943 | ||
944 | base = MAX(base, pci_bridge_get_base(br, type)); | |
945 | limit = MIN(limit, pci_bridge_get_limit(br, type)); | |
946 | } | |
947 | ||
948 | if (base > limit) { | |
88a95564 | 949 | goto no_map; |
a0c7a97e | 950 | } |
88a95564 MT |
951 | *addr = base; |
952 | *size = limit - base + 1; | |
953 | return; | |
954 | no_map: | |
955 | *addr = PCI_BAR_UNMAPPED; | |
956 | *size = 0; | |
a0c7a97e IY |
957 | } |
958 | ||
876a350d MT |
959 | static pcibus_t pci_bar_address(PCIDevice *d, |
960 | int reg, uint8_t type, pcibus_t size) | |
961 | { | |
962 | pcibus_t new_addr, last_addr; | |
963 | int bar = pci_bar(d, reg); | |
964 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
965 | ||
966 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
967 | if (!(cmd & PCI_COMMAND_IO)) { | |
968 | return PCI_BAR_UNMAPPED; | |
969 | } | |
970 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
971 | last_addr = new_addr + size - 1; | |
972 | /* NOTE: we have only 64K ioports on PC */ | |
973 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
974 | return PCI_BAR_UNMAPPED; | |
975 | } | |
976 | return new_addr; | |
977 | } | |
978 | ||
979 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
980 | return PCI_BAR_UNMAPPED; | |
981 | } | |
982 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
983 | new_addr = pci_get_quad(d->config + bar); | |
984 | } else { | |
985 | new_addr = pci_get_long(d->config + bar); | |
986 | } | |
987 | /* the ROM slot has a specific enable bit */ | |
988 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
989 | return PCI_BAR_UNMAPPED; | |
990 | } | |
991 | new_addr &= ~(size - 1); | |
992 | last_addr = new_addr + size - 1; | |
993 | /* NOTE: we do not support wrapping */ | |
994 | /* XXX: as we cannot support really dynamic | |
995 | mappings, we handle specific values as invalid | |
996 | mappings. */ | |
997 | if (last_addr <= new_addr || new_addr == 0 || | |
998 | last_addr == PCI_BAR_UNMAPPED) { | |
999 | return PCI_BAR_UNMAPPED; | |
1000 | } | |
1001 | ||
1002 | /* Now pcibus_t is 64bit. | |
1003 | * Check if 32 bit BAR wraps around explicitly. | |
1004 | * Without this, PC ide doesn't work well. | |
1005 | * TODO: remove this work around. | |
1006 | */ | |
1007 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
1008 | return PCI_BAR_UNMAPPED; | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * OS is allowed to set BAR beyond its addressable | |
1013 | * bits. For example, 32 bit OS can set 64bit bar | |
1014 | * to >4G. Check it. TODO: we might need to support | |
1015 | * it in the future for e.g. PAE. | |
1016 | */ | |
1017 | if (last_addr >= TARGET_PHYS_ADDR_MAX) { | |
1018 | return PCI_BAR_UNMAPPED; | |
1019 | } | |
1020 | ||
1021 | return new_addr; | |
1022 | } | |
1023 | ||
0ac32c83 FB |
1024 | static void pci_update_mappings(PCIDevice *d) |
1025 | { | |
1026 | PCIIORegion *r; | |
876a350d | 1027 | int i; |
c71b5b4a | 1028 | pcibus_t new_addr, filtered_size; |
3b46e624 | 1029 | |
8a8696a3 | 1030 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1031 | r = &d->io_regions[i]; |
a9688570 IY |
1032 | |
1033 | /* this region isn't registered */ | |
ec503442 | 1034 | if (!r->size) |
a9688570 IY |
1035 | continue; |
1036 | ||
876a350d | 1037 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 | 1038 | |
a0c7a97e IY |
1039 | /* bridge filtering */ |
1040 | filtered_size = r->size; | |
1041 | if (new_addr != PCI_BAR_UNMAPPED) { | |
1042 | pci_bridge_filter(d, &new_addr, &filtered_size, r->type); | |
1043 | } | |
1044 | ||
a9688570 | 1045 | /* This bar isn't changed */ |
a0c7a97e | 1046 | if (new_addr == r->addr && filtered_size == r->filtered_size) |
a9688570 IY |
1047 | continue; |
1048 | ||
1049 | /* now do the real mapping */ | |
1050 | if (r->addr != PCI_BAR_UNMAPPED) { | |
1051 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1052 | int class; | |
1053 | /* NOTE: specific hack for IDE in PC case: | |
1054 | only one byte must be mapped. */ | |
1055 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
1056 | if (class == 0x0101 && r->size == 4) { | |
1057 | isa_unassign_ioport(r->addr + 2, 1); | |
1058 | } else { | |
a0c7a97e | 1059 | isa_unassign_ioport(r->addr, r->filtered_size); |
0ac32c83 | 1060 | } |
a9688570 | 1061 | } else { |
c71b5b4a | 1062 | cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), |
a0c7a97e | 1063 | r->filtered_size, |
a9688570 | 1064 | IO_MEM_UNASSIGNED); |
a0c7a97e | 1065 | qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
0ac32c83 FB |
1066 | } |
1067 | } | |
a9688570 | 1068 | r->addr = new_addr; |
a0c7a97e | 1069 | r->filtered_size = filtered_size; |
a9688570 | 1070 | if (r->addr != PCI_BAR_UNMAPPED) { |
a0c7a97e IY |
1071 | /* |
1072 | * TODO: currently almost all the map funcions assumes | |
1073 | * filtered_size == size and addr & ~(size - 1) == addr. | |
1074 | * However with bridge filtering, they aren't always true. | |
1075 | * Teach them such cases, such that filtered_size < size and | |
1076 | * addr & (size - 1) != 0. | |
1077 | */ | |
cf616802 BS |
1078 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1079 | r->map_func(d, i, r->addr, r->filtered_size, r->type); | |
1080 | } else { | |
1081 | r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr), | |
1082 | r->filtered_size, r->type); | |
1083 | } | |
a9688570 | 1084 | } |
0ac32c83 FB |
1085 | } |
1086 | } | |
1087 | ||
a7b15a5c MT |
1088 | static inline int pci_irq_disabled(PCIDevice *d) |
1089 | { | |
1090 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1091 | } | |
1092 | ||
1093 | /* Called after interrupt disabled field update in config space, | |
1094 | * assert/deassert interrupts if necessary. | |
1095 | * Gets original interrupt disable bit value (before update). */ | |
1096 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1097 | { | |
1098 | int i, disabled = pci_irq_disabled(d); | |
1099 | if (disabled == was_irq_disabled) | |
1100 | return; | |
1101 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1102 | int state = pci_irq_state(d, i); | |
1103 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1104 | } | |
1105 | } | |
1106 | ||
5fafdf24 | 1107 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1108 | uint32_t address, int len) |
69b91039 | 1109 | { |
5029fe12 IY |
1110 | uint32_t val = 0; |
1111 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 1112 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
1113 | memcpy(&val, d->config + address, len); |
1114 | return le32_to_cpu(val); | |
0ac32c83 FB |
1115 | } |
1116 | ||
b7ee1603 | 1117 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 1118 | { |
a7b15a5c | 1119 | int i, was_irq_disabled = pci_irq_disabled(d); |
a9f49946 | 1120 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 1121 | |
91011d4f SW |
1122 | for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
1123 | uint8_t wmask = d->wmask[addr + i]; | |
92ba5f51 IY |
1124 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1125 | assert(!(wmask & w1cmask)); | |
91011d4f | 1126 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1127 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1128 | } |
260c0cd3 | 1129 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1130 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1131 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1132 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1133 | pci_update_mappings(d); |
a7b15a5c MT |
1134 | |
1135 | if (range_covers_byte(addr, l, PCI_COMMAND)) | |
1136 | pci_update_irq_disabled(d, was_irq_disabled); | |
69b91039 FB |
1137 | } |
1138 | ||
502a5395 PB |
1139 | /***********************************************************/ |
1140 | /* generic PCI irq support */ | |
30468f78 | 1141 | |
502a5395 | 1142 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1143 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1144 | { |
a60380a5 | 1145 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1146 | int change; |
3b46e624 | 1147 | |
d036bb21 | 1148 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1149 | if (!change) |
1150 | return; | |
d2b59317 | 1151 | |
d036bb21 | 1152 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1153 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1154 | if (pci_irq_disabled(pci_dev)) |
1155 | return; | |
d036bb21 | 1156 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1157 | } |
1158 | ||
502a5395 PB |
1159 | /***********************************************************/ |
1160 | /* monitor info on PCI */ | |
0ac32c83 | 1161 | |
6650ee6d PB |
1162 | typedef struct { |
1163 | uint16_t class; | |
1164 | const char *desc; | |
5e0259e7 GN |
1165 | const char *fw_name; |
1166 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1167 | } pci_class_desc; |
1168 | ||
09bc878a | 1169 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1170 | { |
5e0259e7 GN |
1171 | { 0x0001, "VGA controller", "display"}, |
1172 | { 0x0100, "SCSI controller", "scsi"}, | |
1173 | { 0x0101, "IDE controller", "ide"}, | |
1174 | { 0x0102, "Floppy controller", "fdc"}, | |
1175 | { 0x0103, "IPI controller", "ipi"}, | |
1176 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1177 | { 0x0106, "SATA controller"}, |
1178 | { 0x0107, "SAS controller"}, | |
1179 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1180 | { 0x0200, "Ethernet controller", "ethernet"}, |
1181 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1182 | { 0x0202, "FDDI controller", "fddi"}, | |
1183 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1184 | { 0x0280, "Network controller"}, |
5e0259e7 | 1185 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1186 | { 0x0301, "XGA controller"}, |
1187 | { 0x0302, "3D controller"}, | |
1188 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1189 | { 0x0400, "Video controller", "video"}, |
1190 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1191 | { 0x0402, "Phone"}, |
602ef4d9 | 1192 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1193 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1194 | { 0x0500, "RAM controller", "memory"}, |
1195 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1196 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1197 | { 0x0600, "Host bridge", "host"}, |
1198 | { 0x0601, "ISA bridge", "isa"}, | |
1199 | { 0x0602, "EISA bridge", "eisa"}, | |
1200 | { 0x0603, "MC bridge", "mca"}, | |
1201 | { 0x0604, "PCI bridge", "pci"}, | |
1202 | { 0x0605, "PCMCIA bridge", "pcmcia"}, | |
1203 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1204 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1205 | { 0x0608, "RACEWAY bridge"}, |
1206 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1207 | { 0x0700, "Serial port", "serial"}, |
1208 | { 0x0701, "Parallel port", "parallel"}, | |
1209 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1210 | { 0x0801, "DMA controller", "dma-controller"}, | |
1211 | { 0x0802, "Timer", "timer"}, | |
1212 | { 0x0803, "RTC", "rtc"}, | |
1213 | { 0x0900, "Keyboard", "keyboard"}, | |
1214 | { 0x0901, "Pen", "pen"}, | |
1215 | { 0x0902, "Mouse", "mouse"}, | |
1216 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1217 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
1218 | { 0x0c00, "Fireware contorller", "fireware"}, | |
1219 | { 0x0c01, "Access bus controller", "access-bus"}, | |
1220 | { 0x0c02, "SSA controller", "ssa"}, | |
1221 | { 0x0c03, "USB controller", "usb"}, | |
1222 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
6650ee6d PB |
1223 | { 0, NULL} |
1224 | }; | |
1225 | ||
163c8a59 LC |
1226 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1227 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
30468f78 | 1228 | { |
163c8a59 LC |
1229 | PCIDevice *d; |
1230 | int devfn; | |
30468f78 | 1231 | |
163c8a59 LC |
1232 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1233 | d = bus->devices[devfn]; | |
1234 | if (d) { | |
1235 | fn(bus, d); | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
1241 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
1242 | { | |
1243 | bus = pci_find_bus(bus, bus_num); | |
1244 | ||
1245 | if (bus) { | |
1246 | pci_for_each_device_under_bus(bus, fn); | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | static void pci_device_print(Monitor *mon, QDict *device) | |
1251 | { | |
1252 | QDict *qdict; | |
1253 | QListEntry *entry; | |
1254 | uint64_t addr, size; | |
1255 | ||
1256 | monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus")); | |
1257 | monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n", | |
1258 | qdict_get_int(device, "slot"), | |
1259 | qdict_get_int(device, "function")); | |
376253ec | 1260 | monitor_printf(mon, " "); |
163c8a59 LC |
1261 | |
1262 | qdict = qdict_get_qdict(device, "class_info"); | |
1263 | if (qdict_haskey(qdict, "desc")) { | |
1264 | monitor_printf(mon, "%s", qdict_get_str(qdict, "desc")); | |
6650ee6d | 1265 | } else { |
163c8a59 | 1266 | monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class")); |
72cc6cfe | 1267 | } |
30468f78 | 1268 | |
163c8a59 LC |
1269 | qdict = qdict_get_qdict(device, "id"); |
1270 | monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", | |
1271 | qdict_get_int(qdict, "device"), | |
1272 | qdict_get_int(qdict, "vendor")); | |
1273 | ||
1274 | if (qdict_haskey(device, "irq")) { | |
1275 | monitor_printf(mon, " IRQ %" PRId64 ".\n", | |
1276 | qdict_get_int(device, "irq")); | |
30468f78 | 1277 | } |
b4dccd8d | 1278 | |
163c8a59 LC |
1279 | if (qdict_haskey(device, "pci_bridge")) { |
1280 | QDict *info; | |
1281 | ||
1282 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1283 | ||
1284 | info = qdict_get_qdict(qdict, "bus"); | |
1285 | monitor_printf(mon, " BUS %" PRId64 ".\n", | |
1286 | qdict_get_int(info, "number")); | |
1287 | monitor_printf(mon, " secondary bus %" PRId64 ".\n", | |
1288 | qdict_get_int(info, "secondary")); | |
1289 | monitor_printf(mon, " subordinate bus %" PRId64 ".\n", | |
1290 | qdict_get_int(info, "subordinate")); | |
b4dccd8d | 1291 | |
163c8a59 | 1292 | info = qdict_get_qdict(qdict, "io_range"); |
b4dccd8d | 1293 | monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
163c8a59 LC |
1294 | qdict_get_int(info, "base"), |
1295 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1296 | |
163c8a59 | 1297 | info = qdict_get_qdict(qdict, "memory_range"); |
b4dccd8d IY |
1298 | monitor_printf(mon, |
1299 | " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", | |
163c8a59 LC |
1300 | qdict_get_int(info, "base"), |
1301 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1302 | |
163c8a59 | 1303 | info = qdict_get_qdict(qdict, "prefetchable_range"); |
b4dccd8d | 1304 | monitor_printf(mon, " prefetchable memory range " |
163c8a59 LC |
1305 | "[0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1306 | qdict_get_int(info, "base"), | |
1307 | qdict_get_int(info, "limit")); | |
80b3ada7 | 1308 | } |
14421258 | 1309 | |
163c8a59 LC |
1310 | QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) { |
1311 | qdict = qobject_to_qdict(qlist_entry_obj(entry)); | |
1312 | monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar")); | |
1313 | ||
1314 | addr = qdict_get_int(qdict, "address"); | |
1315 | size = qdict_get_int(qdict, "size"); | |
1316 | ||
1317 | if (!strcmp(qdict_get_str(qdict, "type"), "io")) { | |
1318 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS | |
1319 | " [0x%04"FMT_PCIBUS"].\n", | |
1320 | addr, addr + size - 1); | |
1321 | } else { | |
1322 | monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 1323 | " [0x%08"FMT_PCIBUS"].\n", |
163c8a59 LC |
1324 | qdict_get_bool(qdict, "mem_type_64") ? 64 : 32, |
1325 | qdict_get_bool(qdict, "prefetch") ? | |
1326 | " prefetchable" : "", addr, addr + size - 1); | |
502a5395 | 1327 | } |
77d4bc34 | 1328 | } |
163c8a59 LC |
1329 | |
1330 | monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id")); | |
1331 | ||
d5e4acf7 LC |
1332 | if (qdict_haskey(device, "pci_bridge")) { |
1333 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1334 | if (qdict_haskey(qdict, "devices")) { | |
1335 | QListEntry *dev; | |
1336 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1337 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1338 | } | |
1339 | } | |
1340 | } | |
163c8a59 LC |
1341 | } |
1342 | ||
1343 | void do_pci_info_print(Monitor *mon, const QObject *data) | |
1344 | { | |
1345 | QListEntry *bus, *dev; | |
1346 | ||
1347 | QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) { | |
1348 | QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus)); | |
1349 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1350 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1351 | } | |
80b3ada7 | 1352 | } |
384d8876 FB |
1353 | } |
1354 | ||
163c8a59 LC |
1355 | static QObject *pci_get_dev_class(const PCIDevice *dev) |
1356 | { | |
1357 | int class; | |
1358 | const pci_class_desc *desc; | |
1359 | ||
1360 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1361 | desc = pci_class_descriptions; | |
1362 | while (desc->desc && class != desc->class) | |
1363 | desc++; | |
1364 | ||
1365 | if (desc->desc) { | |
1366 | return qobject_from_jsonf("{ 'desc': %s, 'class': %d }", | |
1367 | desc->desc, class); | |
1368 | } else { | |
1369 | return qobject_from_jsonf("{ 'class': %d }", class); | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | static QObject *pci_get_dev_id(const PCIDevice *dev) | |
1374 | { | |
1375 | return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }", | |
1376 | pci_get_word(dev->config + PCI_VENDOR_ID), | |
1377 | pci_get_word(dev->config + PCI_DEVICE_ID)); | |
1378 | } | |
1379 | ||
1380 | static QObject *pci_get_regions_list(const PCIDevice *dev) | |
1381 | { | |
1382 | int i; | |
1383 | QList *regions_list; | |
1384 | ||
1385 | regions_list = qlist_new(); | |
1386 | ||
1387 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1388 | QObject *obj; | |
1389 | const PCIIORegion *r = &dev->io_regions[i]; | |
1390 | ||
1391 | if (!r->size) { | |
1392 | continue; | |
1393 | } | |
1394 | ||
1395 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1396 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', " | |
1397 | "'address': %" PRId64 ", " | |
1398 | "'size': %" PRId64 " }", | |
1399 | i, r->addr, r->size); | |
1400 | } else { | |
1401 | int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
1402 | ||
1403 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', " | |
1404 | "'mem_type_64': %i, 'prefetch': %i, " | |
1405 | "'address': %" PRId64 ", " | |
1406 | "'size': %" PRId64 " }", | |
1407 | i, mem_type_64, | |
1408 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH, | |
1409 | r->addr, r->size); | |
1410 | } | |
1411 | ||
1412 | qlist_append_obj(regions_list, obj); | |
1413 | } | |
1414 | ||
1415 | return QOBJECT(regions_list); | |
1416 | } | |
1417 | ||
d5e4acf7 LC |
1418 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num); |
1419 | ||
1420 | static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num) | |
163c8a59 | 1421 | { |
b5937f29 | 1422 | uint8_t type; |
163c8a59 LC |
1423 | QObject *obj; |
1424 | ||
1425 | obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p," | |
1426 | " 'qdev_id': %s }", | |
1427 | bus_num, | |
1428 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
1429 | pci_get_dev_class(dev), pci_get_dev_id(dev), | |
1430 | pci_get_regions_list(dev), | |
1431 | dev->qdev.id ? dev->qdev.id : ""); | |
1432 | ||
1433 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
1434 | QDict *qdict = qobject_to_qdict(obj); | |
1435 | qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE])); | |
1436 | } | |
1437 | ||
b5937f29 IY |
1438 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1439 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
163c8a59 LC |
1440 | QDict *qdict; |
1441 | QObject *pci_bridge; | |
1442 | ||
1443 | pci_bridge = qobject_from_jsonf("{ 'bus': " | |
1444 | "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, " | |
1445 | "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1446 | "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1447 | "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }", | |
c021f8e6 | 1448 | dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS], |
163c8a59 LC |
1449 | dev->config[PCI_SUBORDINATE_BUS], |
1450 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1451 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1452 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1453 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1454 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1455 | PCI_BASE_ADDRESS_MEM_PREFETCH), | |
1456 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1457 | PCI_BASE_ADDRESS_MEM_PREFETCH)); | |
1458 | ||
c021f8e6 BS |
1459 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1460 | PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); | |
d5e4acf7 | 1461 | |
c021f8e6 BS |
1462 | if (child_bus) { |
1463 | qdict = qobject_to_qdict(pci_bridge); | |
1464 | qdict_put_obj(qdict, "devices", | |
1465 | pci_get_devices_list(child_bus, | |
1466 | dev->config[PCI_SECONDARY_BUS])); | |
1467 | } | |
1468 | } | |
163c8a59 LC |
1469 | qdict = qobject_to_qdict(obj); |
1470 | qdict_put_obj(qdict, "pci_bridge", pci_bridge); | |
1471 | } | |
1472 | ||
1473 | return obj; | |
1474 | } | |
1475 | ||
1476 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num) | |
384d8876 | 1477 | { |
502a5395 | 1478 | int devfn; |
163c8a59 LC |
1479 | PCIDevice *dev; |
1480 | QList *dev_list; | |
3b46e624 | 1481 | |
163c8a59 LC |
1482 | dev_list = qlist_new(); |
1483 | ||
1484 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1485 | dev = bus->devices[devfn]; | |
1486 | if (dev) { | |
d5e4acf7 | 1487 | qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num)); |
163c8a59 | 1488 | } |
1074df4f | 1489 | } |
163c8a59 LC |
1490 | |
1491 | return QOBJECT(dev_list); | |
1074df4f IY |
1492 | } |
1493 | ||
163c8a59 | 1494 | static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num) |
1074df4f | 1495 | { |
e822a52a | 1496 | bus = pci_find_bus(bus, bus_num); |
502a5395 | 1497 | if (bus) { |
163c8a59 LC |
1498 | return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }", |
1499 | bus_num, pci_get_devices_list(bus, bus_num)); | |
f2aa58c6 | 1500 | } |
163c8a59 LC |
1501 | |
1502 | return NULL; | |
f2aa58c6 FB |
1503 | } |
1504 | ||
163c8a59 | 1505 | void do_pci_info(Monitor *mon, QObject **ret_data) |
f2aa58c6 | 1506 | { |
163c8a59 | 1507 | QList *bus_list; |
e822a52a | 1508 | struct PCIHostBus *host; |
163c8a59 LC |
1509 | |
1510 | bus_list = qlist_new(); | |
1511 | ||
e822a52a | 1512 | QLIST_FOREACH(host, &host_buses, next) { |
163c8a59 LC |
1513 | QObject *obj = pci_get_bus_dict(host->bus, 0); |
1514 | if (obj) { | |
1515 | qlist_append_obj(bus_list, obj); | |
1516 | } | |
e822a52a | 1517 | } |
163c8a59 LC |
1518 | |
1519 | *ret_data = QOBJECT(bus_list); | |
77d4bc34 | 1520 | } |
a41b2ff2 | 1521 | |
cb457d76 AL |
1522 | static const char * const pci_nic_models[] = { |
1523 | "ne2k_pci", | |
1524 | "i82551", | |
1525 | "i82557b", | |
1526 | "i82559er", | |
1527 | "rtl8139", | |
1528 | "e1000", | |
1529 | "pcnet", | |
1530 | "virtio", | |
1531 | NULL | |
1532 | }; | |
1533 | ||
9d07d757 PB |
1534 | static const char * const pci_nic_names[] = { |
1535 | "ne2k_pci", | |
1536 | "i82551", | |
1537 | "i82557b", | |
1538 | "i82559er", | |
1539 | "rtl8139", | |
1540 | "e1000", | |
1541 | "pcnet", | |
53c25cea | 1542 | "virtio-net-pci", |
cb457d76 AL |
1543 | NULL |
1544 | }; | |
1545 | ||
a41b2ff2 | 1546 | /* Initialize a PCI NIC. */ |
33e66b86 | 1547 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1548 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1549 | const char *default_devaddr) | |
a41b2ff2 | 1550 | { |
5607c388 | 1551 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1552 | PCIBus *bus; |
1553 | int devfn; | |
5607c388 | 1554 | PCIDevice *pci_dev; |
9d07d757 | 1555 | DeviceState *dev; |
cb457d76 AL |
1556 | int i; |
1557 | ||
07caea31 MA |
1558 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1559 | if (i < 0) | |
1560 | return NULL; | |
1561 | ||
1562 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1563 | if (!bus) { | |
1ecda02b MA |
1564 | error_report("Invalid PCI device address %s for device %s", |
1565 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1566 | return NULL; |
1567 | } | |
1568 | ||
499cf102 | 1569 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1570 | dev = &pci_dev->qdev; |
1cc33683 | 1571 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1572 | if (qdev_init(dev) < 0) |
1573 | return NULL; | |
9ee05825 | 1574 | return pci_dev; |
a41b2ff2 PB |
1575 | } |
1576 | ||
07caea31 MA |
1577 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1578 | const char *default_devaddr) | |
1579 | { | |
1580 | PCIDevice *res; | |
1581 | ||
1582 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1583 | exit(0); | |
1584 | ||
1585 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1586 | if (!res) | |
1587 | exit(1); | |
1588 | return res; | |
1589 | } | |
1590 | ||
a0c7a97e IY |
1591 | static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) |
1592 | { | |
1593 | pci_update_mappings(d); | |
1594 | } | |
1595 | ||
783753fd | 1596 | void pci_bridge_update_mappings(PCIBus *b) |
a0c7a97e IY |
1597 | { |
1598 | PCIBus *child; | |
1599 | ||
1600 | pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); | |
1601 | ||
1602 | QLIST_FOREACH(child, &b->child, sibling) { | |
1603 | pci_bridge_update_mappings(child); | |
1604 | } | |
1605 | } | |
1606 | ||
929176c3 MT |
1607 | /* Whether a given bus number is in range of the secondary |
1608 | * bus of the given bridge device. */ | |
1609 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
1610 | { | |
1611 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
1612 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
1613 | dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1614 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; | |
1615 | } | |
1616 | ||
e822a52a | 1617 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 1618 | { |
470e6363 | 1619 | PCIBus *sec; |
3ae80618 | 1620 | |
470e6363 | 1621 | if (!bus) { |
e822a52a | 1622 | return NULL; |
470e6363 | 1623 | } |
3ae80618 | 1624 | |
e822a52a IY |
1625 | if (pci_bus_num(bus) == bus_num) { |
1626 | return bus; | |
1627 | } | |
1628 | ||
929176c3 MT |
1629 | /* Consider all bus numbers in range for the host pci bridge. */ |
1630 | if (bus->parent_dev && | |
1631 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { | |
1632 | return NULL; | |
1633 | } | |
1634 | ||
e822a52a | 1635 | /* try child bus */ |
929176c3 MT |
1636 | for (; bus; bus = sec) { |
1637 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1638 | assert(sec->parent_dev); | |
1639 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1640 | return sec; | |
1641 | } | |
1642 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
1643 | break; | |
c021f8e6 | 1644 | } |
e822a52a IY |
1645 | } |
1646 | } | |
1647 | ||
1648 | return NULL; | |
3ae80618 AL |
1649 | } |
1650 | ||
5256d8bf | 1651 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 1652 | { |
e822a52a | 1653 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
1654 | |
1655 | if (!bus) | |
1656 | return NULL; | |
1657 | ||
5256d8bf | 1658 | return bus->devices[devfn]; |
3ae80618 AL |
1659 | } |
1660 | ||
81a322d4 | 1661 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1662 | { |
1663 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1664 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1665 | PCIBus *bus; |
113f89df | 1666 | int rc; |
ab85ceb1 | 1667 | bool is_default_rom; |
6b1b92d3 | 1668 | |
a9f49946 IY |
1669 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1670 | if (info->is_express) { | |
1671 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1672 | } | |
1673 | ||
02e2da45 | 1674 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
113f89df IY |
1675 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, |
1676 | pci_dev->devfn, info); | |
09e3acc6 GH |
1677 | if (pci_dev == NULL) |
1678 | return -1; | |
180c22e1 GH |
1679 | if (qdev->hotplugged && info->no_hotplug) { |
1680 | qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name); | |
1681 | do_pci_unregister_device(pci_dev); | |
1682 | return -1; | |
1683 | } | |
c2afc922 IY |
1684 | if (info->init) { |
1685 | rc = info->init(pci_dev); | |
1686 | if (rc != 0) { | |
1687 | do_pci_unregister_device(pci_dev); | |
1688 | return rc; | |
1689 | } | |
925fe64a | 1690 | } |
8c52c8f3 GH |
1691 | |
1692 | /* rom loading */ | |
ab85ceb1 SW |
1693 | is_default_rom = false; |
1694 | if (pci_dev->romfile == NULL && info->romfile != NULL) { | |
8c52c8f3 | 1695 | pci_dev->romfile = qemu_strdup(info->romfile); |
ab85ceb1 SW |
1696 | is_default_rom = true; |
1697 | } | |
1698 | pci_add_option_rom(pci_dev, is_default_rom); | |
8c52c8f3 | 1699 | |
5beb8ad5 | 1700 | if (bus->hotplug) { |
e927d487 MT |
1701 | /* Let buses differentiate between hotplug and when device is |
1702 | * enabled during qemu machine creation. */ | |
1703 | rc = bus->hotplug(bus->hotplug_qdev, pci_dev, | |
1704 | qdev->hotplugged ? PCI_HOTPLUG_ENABLED: | |
1705 | PCI_COLDPLUG_ENABLED); | |
a213ff63 IY |
1706 | if (rc != 0) { |
1707 | int r = pci_unregister_device(&pci_dev->qdev); | |
1708 | assert(!r); | |
1709 | return rc; | |
1710 | } | |
1711 | } | |
ee995ffb GH |
1712 | return 0; |
1713 | } | |
1714 | ||
1715 | static int pci_unplug_device(DeviceState *qdev) | |
1716 | { | |
1717 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
180c22e1 | 1718 | PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev); |
ee995ffb | 1719 | |
180c22e1 GH |
1720 | if (info->no_hotplug) { |
1721 | qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name); | |
1722 | return -1; | |
1723 | } | |
e927d487 MT |
1724 | return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, |
1725 | PCI_HOTPLUG_DISABLED); | |
6b1b92d3 PB |
1726 | } |
1727 | ||
0aab0d3a | 1728 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1729 | { |
02e2da45 | 1730 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1731 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1732 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1733 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1734 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1735 | } |
1736 | ||
0aab0d3a GH |
1737 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1738 | { | |
1739 | while (info->qdev.name) { | |
1740 | pci_qdev_register(info); | |
1741 | info++; | |
1742 | } | |
1743 | } | |
1744 | ||
49823868 IY |
1745 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1746 | const char *name) | |
6b1b92d3 PB |
1747 | { |
1748 | DeviceState *dev; | |
1749 | ||
02e2da45 | 1750 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1751 | qdev_prop_set_uint32(dev, "addr", devfn); |
49823868 | 1752 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
71077c1c GH |
1753 | return DO_UPCAST(PCIDevice, qdev, dev); |
1754 | } | |
6b1b92d3 | 1755 | |
7cc050b1 BS |
1756 | PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn, |
1757 | bool multifunction, | |
1758 | const char *name) | |
1759 | { | |
1760 | DeviceState *dev; | |
1761 | ||
1762 | dev = qdev_try_create(&bus->qbus, name); | |
1763 | if (!dev) { | |
1764 | return NULL; | |
1765 | } | |
1766 | qdev_prop_set_uint32(dev, "addr", devfn); | |
1767 | qdev_prop_set_bit(dev, "multifunction", multifunction); | |
1768 | return DO_UPCAST(PCIDevice, qdev, dev); | |
1769 | } | |
1770 | ||
49823868 IY |
1771 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1772 | bool multifunction, | |
1773 | const char *name) | |
71077c1c | 1774 | { |
49823868 | 1775 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1776 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1777 | return dev; |
6b1b92d3 | 1778 | } |
6f4cbd39 | 1779 | |
49823868 IY |
1780 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1781 | { | |
1782 | return pci_create_multifunction(bus, devfn, false, name); | |
1783 | } | |
1784 | ||
1785 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1786 | { | |
1787 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1788 | } | |
1789 | ||
7cc050b1 BS |
1790 | PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name) |
1791 | { | |
1792 | return pci_try_create_multifunction(bus, devfn, false, name); | |
1793 | } | |
1794 | ||
6f4cbd39 MT |
1795 | static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1796 | { | |
a9f49946 | 1797 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1798 | int offset = PCI_CONFIG_HEADER_SIZE; |
1799 | int i; | |
a9f49946 | 1800 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1801 | if (pdev->used[i]) |
1802 | offset = i + 1; | |
1803 | else if (i - offset + 1 == size) | |
1804 | return offset; | |
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1809 | uint8_t *prev_p) | |
1810 | { | |
1811 | uint8_t next, prev; | |
1812 | ||
1813 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1814 | return 0; | |
1815 | ||
1816 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1817 | prev = next + PCI_CAP_LIST_NEXT) | |
1818 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1819 | break; | |
1820 | ||
1821 | if (prev_p) | |
1822 | *prev_p = prev; | |
1823 | return next; | |
1824 | } | |
1825 | ||
c2039bd0 AL |
1826 | static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1827 | { | |
1828 | cpu_register_physical_memory(addr, size, pdev->rom_offset); | |
1829 | } | |
1830 | ||
ab85ceb1 SW |
1831 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
1832 | This is needed for an option rom which is used for more than one device. */ | |
1833 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) | |
1834 | { | |
1835 | uint16_t vendor_id; | |
1836 | uint16_t device_id; | |
1837 | uint16_t rom_vendor_id; | |
1838 | uint16_t rom_device_id; | |
1839 | uint16_t rom_magic; | |
1840 | uint16_t pcir_offset; | |
1841 | uint8_t checksum; | |
1842 | ||
1843 | /* Words in rom data are little endian (like in PCI configuration), | |
1844 | so they can be read / written with pci_get_word / pci_set_word. */ | |
1845 | ||
1846 | /* Only a valid rom will be patched. */ | |
1847 | rom_magic = pci_get_word(ptr); | |
1848 | if (rom_magic != 0xaa55) { | |
1849 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
1850 | return; | |
1851 | } | |
1852 | pcir_offset = pci_get_word(ptr + 0x18); | |
1853 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
1854 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
1855 | return; | |
1856 | } | |
1857 | ||
1858 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1859 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1860 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
1861 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
1862 | ||
1863 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
1864 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
1865 | ||
1866 | checksum = ptr[6]; | |
1867 | ||
1868 | if (vendor_id != rom_vendor_id) { | |
1869 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
1870 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
1871 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
1872 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1873 | ptr[6] = checksum; | |
1874 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
1875 | } | |
1876 | ||
1877 | if (device_id != rom_device_id) { | |
1878 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
1879 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
1880 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
1881 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1882 | ptr[6] = checksum; | |
1883 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
1884 | } | |
1885 | } | |
1886 | ||
c2039bd0 | 1887 | /* Add an option rom for the device */ |
ab85ceb1 | 1888 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
c2039bd0 AL |
1889 | { |
1890 | int size; | |
1891 | char *path; | |
1892 | void *ptr; | |
1724f049 | 1893 | char name[32]; |
c2039bd0 | 1894 | |
8c52c8f3 GH |
1895 | if (!pdev->romfile) |
1896 | return 0; | |
1897 | if (strlen(pdev->romfile) == 0) | |
1898 | return 0; | |
1899 | ||
88169ddf GH |
1900 | if (!pdev->rom_bar) { |
1901 | /* | |
1902 | * Load rom via fw_cfg instead of creating a rom bar, | |
1903 | * for 0.11 compatibility. | |
1904 | */ | |
1905 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1906 | if (class == 0x0300) { | |
1907 | rom_add_vga(pdev->romfile); | |
1908 | } else { | |
2e55e842 | 1909 | rom_add_option(pdev->romfile, -1); |
88169ddf GH |
1910 | } |
1911 | return 0; | |
1912 | } | |
1913 | ||
8c52c8f3 | 1914 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1915 | if (path == NULL) { |
8c52c8f3 | 1916 | path = qemu_strdup(pdev->romfile); |
c2039bd0 AL |
1917 | } |
1918 | ||
1919 | size = get_image_size(path); | |
8c52c8f3 | 1920 | if (size < 0) { |
1ecda02b MA |
1921 | error_report("%s: failed to find romfile \"%s\"", |
1922 | __FUNCTION__, pdev->romfile); | |
386bbf45 | 1923 | qemu_free(path); |
8c52c8f3 GH |
1924 | return -1; |
1925 | } | |
c2039bd0 AL |
1926 | if (size & (size - 1)) { |
1927 | size = 1 << qemu_fls(size); | |
1928 | } | |
1929 | ||
1724f049 AW |
1930 | if (pdev->qdev.info->vmsd) |
1931 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name); | |
1932 | else | |
1933 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name); | |
1934 | pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size); | |
c2039bd0 AL |
1935 | |
1936 | ptr = qemu_get_ram_ptr(pdev->rom_offset); | |
1937 | load_image(path, ptr); | |
1938 | qemu_free(path); | |
1939 | ||
ab85ceb1 SW |
1940 | if (is_default_rom) { |
1941 | /* Only the default rom images will be patched (if needed). */ | |
1942 | pci_patch_ids(pdev, ptr, size); | |
1943 | } | |
1944 | ||
8c12f191 JB |
1945 | qemu_put_ram_ptr(ptr); |
1946 | ||
c2039bd0 AL |
1947 | pci_register_bar(pdev, PCI_ROM_SLOT, size, |
1948 | 0, pci_map_option_rom); | |
1949 | ||
1950 | return 0; | |
1951 | } | |
1952 | ||
230741dc AW |
1953 | static void pci_del_option_rom(PCIDevice *pdev) |
1954 | { | |
1955 | if (!pdev->rom_offset) | |
1956 | return; | |
1957 | ||
1958 | qemu_ram_free(pdev->rom_offset); | |
1959 | pdev->rom_offset = 0; | |
1960 | } | |
1961 | ||
ca77089d IY |
1962 | /* |
1963 | * if !offset | |
1964 | * Reserve space and add capability to the linked list in pci config space | |
1965 | * | |
1966 | * if offset = 0, | |
1967 | * Find and reserve space and add capability to the linked list | |
1968 | * in pci config space */ | |
1969 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
1970 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1971 | { |
ca77089d IY |
1972 | uint8_t *config; |
1973 | if (!offset) { | |
1974 | offset = pci_find_space(pdev, size); | |
1975 | if (!offset) { | |
1976 | return -ENOSPC; | |
1977 | } | |
1978 | } | |
1979 | ||
1980 | config = pdev->config + offset; | |
6f4cbd39 MT |
1981 | config[PCI_CAP_LIST_ID] = cap_id; |
1982 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1983 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1984 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1985 | memset(pdev->used + offset, 0xFF, size); | |
1986 | /* Make capability read-only by default */ | |
1987 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1988 | /* Check capability by default */ |
1989 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1990 | return offset; |
1991 | } | |
1992 | ||
1993 | /* Unlink capability from the pci config space. */ | |
1994 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1995 | { | |
1996 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1997 | if (!offset) | |
1998 | return; | |
1999 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 2000 | /* Make capability writable again */ |
6f4cbd39 | 2001 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 2002 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
2003 | /* Clear cmask as device-specific registers can't be checked */ |
2004 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
2005 | memset(pdev->used + offset, 0, size); |
2006 | ||
2007 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
2008 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
2009 | } | |
2010 | ||
2011 | /* Reserve space for capability at a known offset (to call after load). */ | |
2012 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
2013 | { | |
2014 | memset(pdev->used + offset, 0xff, size); | |
2015 | } | |
2016 | ||
2017 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
2018 | { | |
2019 | return pci_find_capability_list(pdev, cap_id, NULL); | |
2020 | } | |
10c4c98a GH |
2021 | |
2022 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
2023 | { | |
2024 | PCIDevice *d = (PCIDevice *)dev; | |
2025 | const pci_class_desc *desc; | |
2026 | char ctxt[64]; | |
2027 | PCIIORegion *r; | |
2028 | int i, class; | |
2029 | ||
b0ff8eb2 | 2030 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
2031 | desc = pci_class_descriptions; |
2032 | while (desc->desc && class != desc->class) | |
2033 | desc++; | |
2034 | if (desc->desc) { | |
2035 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
2036 | } else { | |
2037 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
2038 | } | |
2039 | ||
2040 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
2041 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
7f5feab4 | 2042 | indent, "", ctxt, pci_bus_num(d->bus), |
e822a52a | 2043 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
2044 | pci_get_word(d->config + PCI_VENDOR_ID), |
2045 | pci_get_word(d->config + PCI_DEVICE_ID), | |
2046 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
2047 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
2048 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2049 | r = &d->io_regions[i]; | |
2050 | if (!r->size) | |
2051 | continue; | |
89e8b13c IY |
2052 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
2053 | " [0x%"FMT_PCIBUS"]\n", | |
2054 | indent, "", | |
0392a017 | 2055 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
2056 | r->addr, r->addr + r->size - 1); |
2057 | } | |
2058 | } | |
03587182 | 2059 | |
5e0259e7 GN |
2060 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2061 | { | |
2062 | PCIDevice *d = (PCIDevice *)dev; | |
2063 | const char *name = NULL; | |
2064 | const pci_class_desc *desc = pci_class_descriptions; | |
2065 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2066 | ||
2067 | while (desc->desc && | |
2068 | (class & ~desc->fw_ign_bits) != | |
2069 | (desc->class & ~desc->fw_ign_bits)) { | |
2070 | desc++; | |
2071 | } | |
2072 | ||
2073 | if (desc->desc) { | |
2074 | name = desc->fw_name; | |
2075 | } | |
2076 | ||
2077 | if (name) { | |
2078 | pstrcpy(buf, len, name); | |
2079 | } else { | |
2080 | snprintf(buf, len, "pci%04x,%04x", | |
2081 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2082 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2083 | } | |
2084 | ||
2085 | return buf; | |
2086 | } | |
2087 | ||
2088 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2089 | { | |
2090 | PCIDevice *d = (PCIDevice *)dev; | |
2091 | char path[50], name[33]; | |
2092 | int off; | |
2093 | ||
2094 | off = snprintf(path, sizeof(path), "%s@%x", | |
2095 | pci_dev_fw_name(dev, name, sizeof name), | |
2096 | PCI_SLOT(d->devfn)); | |
2097 | if (PCI_FUNC(d->devfn)) | |
2098 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
2099 | return strdup(path); | |
2100 | } | |
2101 | ||
4f43c1ff AW |
2102 | static char *pcibus_get_dev_path(DeviceState *dev) |
2103 | { | |
a6a7005d MT |
2104 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2105 | PCIDevice *t; | |
2106 | int slot_depth; | |
2107 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2108 | * 00 is added here to make this format compatible with | |
2109 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2110 | * Slot.Function list specifies the slot and function numbers for all | |
2111 | * devices on the path from root to the specific device. */ | |
2991181a MT |
2112 | char domain[] = "DDDD:00"; |
2113 | char slot[] = ":SS.F"; | |
2114 | int domain_len = sizeof domain - 1 /* For '\0' */; | |
2115 | int slot_len = sizeof slot - 1 /* For '\0' */; | |
a6a7005d MT |
2116 | int path_len; |
2117 | char *path, *p; | |
2991181a | 2118 | int s; |
a6a7005d MT |
2119 | |
2120 | /* Calculate # of slots on path between device and root. */; | |
2121 | slot_depth = 0; | |
2122 | for (t = d; t; t = t->bus->parent_dev) { | |
2123 | ++slot_depth; | |
2124 | } | |
2125 | ||
2126 | path_len = domain_len + slot_len * slot_depth; | |
2127 | ||
2128 | /* Allocate memory, fill in the terminating null byte. */ | |
e10990c3 | 2129 | path = qemu_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2130 | path[path_len] = '\0'; |
2131 | ||
2132 | /* First field is the domain. */ | |
2991181a MT |
2133 | s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); |
2134 | assert(s == domain_len); | |
2135 | memcpy(path, domain, domain_len); | |
a6a7005d MT |
2136 | |
2137 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2138 | * them in the reverse order, last to first. */ | |
2139 | p = path + path_len; | |
2140 | for (t = d; t; t = t->bus->parent_dev) { | |
2141 | p -= slot_len; | |
2991181a | 2142 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2143 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2144 | assert(s == slot_len); |
2145 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2146 | } |
2147 | ||
2148 | return path; | |
4f43c1ff AW |
2149 | } |
2150 | ||
f3006dd1 IY |
2151 | static int pci_qdev_find_recursive(PCIBus *bus, |
2152 | const char *id, PCIDevice **pdev) | |
2153 | { | |
2154 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2155 | if (!qdev) { | |
2156 | return -ENODEV; | |
2157 | } | |
2158 | ||
2159 | /* roughly check if given qdev is pci device */ | |
2160 | if (qdev->info->init == &pci_qdev_init && | |
2161 | qdev->parent_bus->info == &pci_bus_info) { | |
2162 | *pdev = DO_UPCAST(PCIDevice, qdev, qdev); | |
2163 | return 0; | |
2164 | } | |
2165 | return -EINVAL; | |
2166 | } | |
2167 | ||
2168 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2169 | { | |
2170 | struct PCIHostBus *host; | |
2171 | int rc = -ENODEV; | |
2172 | ||
2173 | QLIST_FOREACH(host, &host_buses, next) { | |
2174 | int tmp = pci_qdev_find_recursive(host->bus, id, pdev); | |
2175 | if (!tmp) { | |
2176 | rc = 0; | |
2177 | break; | |
2178 | } | |
2179 | if (tmp != -ENODEV) { | |
2180 | rc = tmp; | |
2181 | } | |
2182 | } | |
2183 | ||
2184 | return rc; | |
2185 | } |