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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
783753fd | 26 | #include "pci_bridge.h" |
cfb0a50a | 27 | #include "pci_internals.h" |
376253ec | 28 | #include "monitor.h" |
87ecb68b | 29 | #include "net.h" |
880345c4 | 30 | #include "sysemu.h" |
c2039bd0 | 31 | #include "loader.h" |
bf1b0071 | 32 | #include "range.h" |
79627472 | 33 | #include "qmp-commands.h" |
cbd2d434 JK |
34 | #include "msi.h" |
35 | #include "msix.h" | |
817dcc53 | 36 | #include "exec-memory.h" |
69b91039 FB |
37 | |
38 | //#define DEBUG_PCI | |
d8d2e079 | 39 | #ifdef DEBUG_PCI |
2e49d64a | 40 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
41 | #else |
42 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
43 | #endif | |
69b91039 | 44 | |
10c4c98a | 45 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 46 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 47 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
9bb33586 | 48 | static int pcibus_reset(BusState *qbus); |
10c4c98a | 49 | |
3cb75a7c PB |
50 | static Property pci_props[] = { |
51 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), | |
52 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), | |
53 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), | |
54 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, | |
55 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
56 | DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, | |
57 | QEMU_PCI_CAP_SERR_BITNR, true), | |
58 | DEFINE_PROP_END_OF_LIST() | |
59 | }; | |
60 | ||
0d936928 AL |
61 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
62 | { | |
63 | BusClass *k = BUS_CLASS(klass); | |
64 | ||
65 | k->print_dev = pcibus_dev_print; | |
66 | k->get_dev_path = pcibus_get_dev_path; | |
67 | k->get_fw_dev_path = pcibus_get_fw_dev_path; | |
68 | k->reset = pcibus_reset; | |
69 | } | |
70 | ||
71 | static const TypeInfo pci_bus_info = { | |
72 | .name = TYPE_PCI_BUS, | |
73 | .parent = TYPE_BUS, | |
74 | .instance_size = sizeof(PCIBus), | |
75 | .class_init = pci_bus_class_init, | |
30468f78 | 76 | }; |
69b91039 | 77 | |
d662210a | 78 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
1941d19c | 79 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 80 | static void pci_set_irq(void *opaque, int irq_num, int level); |
ab85ceb1 | 81 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
230741dc | 82 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 83 | |
d350d97d AL |
84 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
85 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
86 | |
87 | struct PCIHostBus { | |
88 | int domain; | |
89 | struct PCIBus *bus; | |
90 | QLIST_ENTRY(PCIHostBus) next; | |
91 | }; | |
92 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 93 | |
2d1e9f96 JQ |
94 | static const VMStateDescription vmstate_pcibus = { |
95 | .name = "PCIBUS", | |
96 | .version_id = 1, | |
97 | .minimum_version_id = 1, | |
98 | .minimum_version_id_old = 1, | |
99 | .fields = (VMStateField []) { | |
100 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 101 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 102 | VMSTATE_END_OF_LIST() |
52fc1d83 | 103 | } |
2d1e9f96 | 104 | }; |
b3b11697 | 105 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 106 | { |
b3b11697 IY |
107 | uint8_t type; |
108 | ||
109 | if (reg != PCI_ROM_SLOT) | |
110 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
111 | ||
112 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
113 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
114 | } |
115 | ||
d036bb21 MT |
116 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
117 | { | |
118 | return (d->irq_state >> irq_num) & 0x1; | |
119 | } | |
120 | ||
121 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
122 | { | |
123 | d->irq_state &= ~(0x1 << irq_num); | |
124 | d->irq_state |= level << irq_num; | |
125 | } | |
126 | ||
127 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
128 | { | |
129 | PCIBus *bus; | |
130 | for (;;) { | |
131 | bus = pci_dev->bus; | |
132 | irq_num = bus->map_irq(pci_dev, irq_num); | |
133 | if (bus->set_irq) | |
134 | break; | |
135 | pci_dev = bus->parent_dev; | |
136 | } | |
137 | bus->irq_count[irq_num] += change; | |
138 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
139 | } | |
140 | ||
9ddf8437 IY |
141 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
142 | { | |
143 | assert(irq_num >= 0); | |
144 | assert(irq_num < bus->nirq); | |
145 | return !!bus->irq_count[irq_num]; | |
146 | } | |
147 | ||
f9bf77dd MT |
148 | /* Update interrupt status bit in config space on interrupt |
149 | * state change. */ | |
150 | static void pci_update_irq_status(PCIDevice *dev) | |
151 | { | |
152 | if (dev->irq_state) { | |
153 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
154 | } else { | |
155 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
156 | } | |
157 | } | |
158 | ||
4c92325b IY |
159 | void pci_device_deassert_intx(PCIDevice *dev) |
160 | { | |
161 | int i; | |
162 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
163 | qemu_set_irq(dev->irq[i], 0); | |
164 | } | |
165 | } | |
166 | ||
0ead87c8 IY |
167 | /* |
168 | * This function is called on #RST and FLR. | |
169 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
170 | */ | |
171 | void pci_device_reset(PCIDevice *dev) | |
5330de09 | 172 | { |
c0b1905b | 173 | int r; |
6fc4925b AL |
174 | |
175 | qdev_reset_all(&dev->qdev); | |
c0b1905b | 176 | |
d036bb21 | 177 | dev->irq_state = 0; |
f9bf77dd | 178 | pci_update_irq_status(dev); |
4c92325b | 179 | pci_device_deassert_intx(dev); |
ebabb67a | 180 | /* Clear all writable bits */ |
99443c21 | 181 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
182 | pci_get_word(dev->wmask + PCI_COMMAND) | |
183 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
184 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
185 | pci_get_word(dev->wmask + PCI_STATUS) | | |
186 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
c0b1905b MT |
187 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
188 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
189 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
190 | PCIIORegion *region = &dev->io_regions[r]; |
191 | if (!region->size) { | |
c0b1905b MT |
192 | continue; |
193 | } | |
71ebd6dc IY |
194 | |
195 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
196 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
197 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
198 | } else { | |
199 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
200 | } | |
c0b1905b MT |
201 | } |
202 | pci_update_mappings(dev); | |
cbd2d434 JK |
203 | |
204 | msi_reset(dev); | |
205 | msix_reset(dev); | |
5330de09 MT |
206 | } |
207 | ||
9bb33586 IY |
208 | /* |
209 | * Trigger pci bus reset under a given bus. | |
210 | * To be called on RST# assert. | |
211 | */ | |
212 | void pci_bus_reset(PCIBus *bus) | |
6eaa6847 | 213 | { |
6eaa6847 GN |
214 | int i; |
215 | ||
216 | for (i = 0; i < bus->nirq; i++) { | |
217 | bus->irq_count[i] = 0; | |
218 | } | |
5330de09 MT |
219 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
220 | if (bus->devices[i]) { | |
221 | pci_device_reset(bus->devices[i]); | |
222 | } | |
6eaa6847 GN |
223 | } |
224 | } | |
225 | ||
9bb33586 IY |
226 | static int pcibus_reset(BusState *qbus) |
227 | { | |
228 | pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); | |
229 | ||
230 | /* topology traverse is done by pci_bus_reset(). | |
231 | Tell qbus/qdev walker not to traverse the tree */ | |
232 | return 1; | |
233 | } | |
234 | ||
e822a52a IY |
235 | static void pci_host_bus_register(int domain, PCIBus *bus) |
236 | { | |
237 | struct PCIHostBus *host; | |
7267c094 | 238 | host = g_malloc0(sizeof(*host)); |
e822a52a IY |
239 | host->domain = domain; |
240 | host->bus = bus; | |
241 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
242 | } | |
243 | ||
c469e1dd | 244 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
245 | { |
246 | struct PCIHostBus *host; | |
247 | ||
248 | QLIST_FOREACH(host, &host_buses, next) { | |
249 | if (host->domain == domain) { | |
250 | return host->bus; | |
251 | } | |
252 | } | |
253 | ||
254 | return NULL; | |
255 | } | |
256 | ||
e075e788 IY |
257 | int pci_find_domain(const PCIBus *bus) |
258 | { | |
259 | PCIDevice *d; | |
260 | struct PCIHostBus *host; | |
261 | ||
262 | /* obtain root bus */ | |
263 | while ((d = bus->parent_dev) != NULL) { | |
264 | bus = d->bus; | |
265 | } | |
266 | ||
267 | QLIST_FOREACH(host, &host_buses, next) { | |
268 | if (host->bus == bus) { | |
269 | return host->domain; | |
270 | } | |
271 | } | |
272 | ||
273 | abort(); /* should not be reached */ | |
274 | return -1; | |
275 | } | |
276 | ||
21eea4b3 | 277 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
1e39101c | 278 | const char *name, |
aee97b84 AK |
279 | MemoryRegion *address_space_mem, |
280 | MemoryRegion *address_space_io, | |
1e39101c | 281 | uint8_t devfn_min) |
30468f78 | 282 | { |
0d936928 | 283 | qbus_create_inplace(&bus->qbus, TYPE_PCI_BUS, parent, name); |
6fa84913 | 284 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 285 | bus->devfn_min = devfn_min; |
5968eca3 AK |
286 | bus->address_space_mem = address_space_mem; |
287 | bus->address_space_io = address_space_io; | |
e822a52a IY |
288 | |
289 | /* host bridge */ | |
290 | QLIST_INIT(&bus->child); | |
291 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
292 | ||
0be71e32 | 293 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
21eea4b3 GH |
294 | } |
295 | ||
1e39101c | 296 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
297 | MemoryRegion *address_space_mem, |
298 | MemoryRegion *address_space_io, | |
299 | uint8_t devfn_min) | |
21eea4b3 GH |
300 | { |
301 | PCIBus *bus; | |
302 | ||
7267c094 | 303 | bus = g_malloc0(sizeof(*bus)); |
0d936928 | 304 | bus->qbus.glib_allocated = true; |
aee97b84 AK |
305 | pci_bus_new_inplace(bus, parent, name, address_space_mem, |
306 | address_space_io, devfn_min); | |
21eea4b3 GH |
307 | return bus; |
308 | } | |
309 | ||
310 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
311 | void *irq_opaque, int nirq) | |
312 | { | |
313 | bus->set_irq = set_irq; | |
314 | bus->map_irq = map_irq; | |
315 | bus->irq_opaque = irq_opaque; | |
316 | bus->nirq = nirq; | |
7267c094 | 317 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
21eea4b3 GH |
318 | } |
319 | ||
87c30546 | 320 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
321 | { |
322 | bus->qbus.allow_hotplug = 1; | |
323 | bus->hotplug = hotplug; | |
87c30546 | 324 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
325 | } |
326 | ||
21eea4b3 GH |
327 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
328 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 329 | void *irq_opaque, |
aee97b84 AK |
330 | MemoryRegion *address_space_mem, |
331 | MemoryRegion *address_space_io, | |
1e39101c | 332 | uint8_t devfn_min, int nirq) |
21eea4b3 GH |
333 | { |
334 | PCIBus *bus; | |
335 | ||
aee97b84 AK |
336 | bus = pci_bus_new(parent, name, address_space_mem, |
337 | address_space_io, devfn_min); | |
21eea4b3 | 338 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
30468f78 FB |
339 | return bus; |
340 | } | |
69b91039 | 341 | |
502a5395 PB |
342 | int pci_bus_num(PCIBus *s) |
343 | { | |
e94ff650 IY |
344 | if (!s->parent_dev) |
345 | return 0; /* pci host bridge */ | |
346 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
347 | } |
348 | ||
73534f2f | 349 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 350 | { |
73534f2f | 351 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 352 | uint8_t *config; |
52fc1d83 AZ |
353 | int i; |
354 | ||
a9f49946 | 355 | assert(size == pci_config_size(s)); |
7267c094 | 356 | config = g_malloc(size); |
a9f49946 IY |
357 | |
358 | qemu_get_buffer(f, config, size); | |
359 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
360 | if ((config[i] ^ s->config[i]) & |
361 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
7267c094 | 362 | g_free(config); |
bd4b65ee | 363 | return -EINVAL; |
a9f49946 IY |
364 | } |
365 | } | |
366 | memcpy(s->config, config, size); | |
bd4b65ee | 367 | |
1941d19c | 368 | pci_update_mappings(s); |
52fc1d83 | 369 | |
7267c094 | 370 | g_free(config); |
30ca2aab FB |
371 | return 0; |
372 | } | |
373 | ||
73534f2f | 374 | /* just put buffer */ |
84e2e3eb | 375 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 376 | { |
dbe73d7f | 377 | const uint8_t **v = pv; |
a9f49946 | 378 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 379 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
380 | } |
381 | ||
382 | static VMStateInfo vmstate_info_pci_config = { | |
383 | .name = "pci config", | |
384 | .get = get_pci_config_device, | |
385 | .put = put_pci_config_device, | |
386 | }; | |
387 | ||
d036bb21 MT |
388 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
389 | { | |
c3f8f611 | 390 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
391 | uint32_t irq_state[PCI_NUM_PINS]; |
392 | int i; | |
393 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
394 | irq_state[i] = qemu_get_be32(f); | |
395 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
396 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
397 | irq_state[i]); | |
398 | return -EINVAL; | |
399 | } | |
400 | } | |
401 | ||
402 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
403 | pci_set_irq_state(s, i, irq_state[i]); | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
410 | { | |
411 | int i; | |
c3f8f611 | 412 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
413 | |
414 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
415 | qemu_put_be32(f, pci_irq_state(s, i)); | |
416 | } | |
417 | } | |
418 | ||
419 | static VMStateInfo vmstate_info_pci_irq_state = { | |
420 | .name = "pci irq state", | |
421 | .get = get_pci_irq_state, | |
422 | .put = put_pci_irq_state, | |
423 | }; | |
424 | ||
73534f2f JQ |
425 | const VMStateDescription vmstate_pci_device = { |
426 | .name = "PCIDevice", | |
427 | .version_id = 2, | |
428 | .minimum_version_id = 1, | |
429 | .minimum_version_id_old = 1, | |
430 | .fields = (VMStateField []) { | |
431 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
432 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
433 | vmstate_info_pci_config, | |
434 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
435 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
436 | vmstate_info_pci_irq_state, | |
437 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
438 | VMSTATE_END_OF_LIST() |
439 | } | |
440 | }; | |
441 | ||
442 | const VMStateDescription vmstate_pcie_device = { | |
1de53459 | 443 | .name = "PCIEDevice", |
a9f49946 IY |
444 | .version_id = 2, |
445 | .minimum_version_id = 1, | |
446 | .minimum_version_id_old = 1, | |
447 | .fields = (VMStateField []) { | |
448 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
449 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
450 | vmstate_info_pci_config, | |
451 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
452 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
453 | vmstate_info_pci_irq_state, | |
454 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
455 | VMSTATE_END_OF_LIST() |
456 | } | |
457 | }; | |
458 | ||
a9f49946 IY |
459 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
460 | { | |
461 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
462 | } | |
463 | ||
73534f2f JQ |
464 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
465 | { | |
f9bf77dd MT |
466 | /* Clear interrupt status bit: it is implicit |
467 | * in irq_state which we are saving. | |
468 | * This makes us compatible with old devices | |
469 | * which never set or clear this bit. */ | |
470 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 471 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
472 | /* Restore the interrupt status bit. */ |
473 | pci_update_irq_status(s); | |
73534f2f JQ |
474 | } |
475 | ||
476 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
477 | { | |
f9bf77dd MT |
478 | int ret; |
479 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
480 | /* Restore the interrupt status bit. */ | |
481 | pci_update_irq_status(s); | |
482 | return ret; | |
73534f2f JQ |
483 | } |
484 | ||
5e434f4e | 485 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 486 | { |
5e434f4e IY |
487 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
488 | pci_default_sub_vendor_id); | |
489 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
490 | pci_default_sub_device_id); | |
d350d97d AL |
491 | } |
492 | ||
880345c4 | 493 | /* |
43c945f1 IY |
494 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
495 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 496 | */ |
94a09e2c | 497 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
43c945f1 | 498 | unsigned int *slotp, unsigned int *funcp) |
880345c4 AL |
499 | { |
500 | const char *p; | |
501 | char *e; | |
502 | unsigned long val; | |
503 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
504 | unsigned int slot = 0; |
505 | unsigned int func = 0; | |
880345c4 AL |
506 | |
507 | p = addr; | |
508 | val = strtoul(p, &e, 16); | |
509 | if (e == p) | |
510 | return -1; | |
511 | if (*e == ':') { | |
512 | bus = val; | |
513 | p = e + 1; | |
514 | val = strtoul(p, &e, 16); | |
515 | if (e == p) | |
516 | return -1; | |
517 | if (*e == ':') { | |
518 | dom = bus; | |
519 | bus = val; | |
520 | p = e + 1; | |
521 | val = strtoul(p, &e, 16); | |
522 | if (e == p) | |
523 | return -1; | |
524 | } | |
525 | } | |
526 | ||
880345c4 AL |
527 | slot = val; |
528 | ||
43c945f1 IY |
529 | if (funcp != NULL) { |
530 | if (*e != '.') | |
531 | return -1; | |
532 | ||
533 | p = e + 1; | |
534 | val = strtoul(p, &e, 16); | |
535 | if (e == p) | |
536 | return -1; | |
537 | ||
538 | func = val; | |
539 | } | |
540 | ||
541 | /* if funcp == NULL func is 0 */ | |
542 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
543 | return -1; | |
544 | ||
880345c4 AL |
545 | if (*e) |
546 | return -1; | |
547 | ||
880345c4 AL |
548 | *domp = dom; |
549 | *busp = bus; | |
550 | *slotp = slot; | |
43c945f1 IY |
551 | if (funcp != NULL) |
552 | *funcp = func; | |
880345c4 AL |
553 | return 0; |
554 | } | |
555 | ||
e9283f8b JK |
556 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
557 | unsigned *slotp) | |
880345c4 | 558 | { |
e9283f8b JK |
559 | /* strip legacy tag */ |
560 | if (!strncmp(addr, "pci_addr=", 9)) { | |
561 | addr += 9; | |
562 | } | |
43c945f1 | 563 | if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { |
e9283f8b | 564 | monitor_printf(mon, "Invalid pci address\n"); |
880345c4 | 565 | return -1; |
e9283f8b JK |
566 | } |
567 | return 0; | |
880345c4 AL |
568 | } |
569 | ||
49bd1458 | 570 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
571 | { |
572 | int dom, bus; | |
573 | unsigned slot; | |
574 | ||
575 | if (!devaddr) { | |
576 | *devfnp = -1; | |
d662210a | 577 | return pci_find_bus_nr(pci_find_root_bus(0), 0); |
5607c388 MA |
578 | } |
579 | ||
43c945f1 | 580 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
581 | return NULL; |
582 | } | |
583 | ||
6ff534b6 | 584 | *devfnp = PCI_DEVFN(slot, 0); |
d662210a | 585 | return pci_find_bus_nr(pci_find_root_bus(dom), bus); |
5607c388 MA |
586 | } |
587 | ||
bd4b65ee MT |
588 | static void pci_init_cmask(PCIDevice *dev) |
589 | { | |
590 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
591 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
592 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
593 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
594 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
595 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
596 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
597 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
598 | } | |
599 | ||
b7ee1603 MT |
600 | static void pci_init_wmask(PCIDevice *dev) |
601 | { | |
a9f49946 IY |
602 | int config_size = pci_config_size(dev); |
603 | ||
b7ee1603 MT |
604 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
605 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 606 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
607 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
608 | PCI_COMMAND_INTX_DISABLE); | |
b1aeb926 IY |
609 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
610 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); | |
611 | } | |
3e21ffc9 IY |
612 | |
613 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
614 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
615 | } |
616 | ||
89d437df IY |
617 | static void pci_init_w1cmask(PCIDevice *dev) |
618 | { | |
619 | /* | |
f6bdfcc9 | 620 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
621 | * long as their value is hardwired to 0. |
622 | */ | |
623 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
624 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
625 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
626 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
627 | } | |
628 | ||
d5f27e88 | 629 | static void pci_init_mask_bridge(PCIDevice *d) |
fb231628 IY |
630 | { |
631 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
632 | PCI_SEC_LETENCY_TIMER */ | |
633 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
634 | ||
635 | /* base and limit */ | |
636 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
637 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
638 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
639 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
640 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
641 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
642 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
643 | PCI_PREF_RANGE_MASK & 0xffff); | |
644 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
645 | PCI_PREF_RANGE_MASK & 0xffff); | |
646 | ||
647 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
648 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
649 | ||
d5f27e88 | 650 | /* Supported memory and i/o types */ |
68917102 MT |
651 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
652 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; | |
d5f27e88 MT |
653 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
654 | PCI_PREF_RANGE_TYPE_64); | |
655 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, | |
656 | PCI_PREF_RANGE_TYPE_64); | |
657 | ||
f6bdfcc9 MT |
658 | /* TODO: add this define to pci_regs.h in linux and then in qemu. */ |
659 | #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ | |
660 | #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ | |
661 | #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ | |
662 | #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ | |
663 | #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ | |
664 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, | |
665 | PCI_BRIDGE_CTL_PARITY | | |
666 | PCI_BRIDGE_CTL_SERR | | |
667 | PCI_BRIDGE_CTL_ISA | | |
668 | PCI_BRIDGE_CTL_VGA | | |
669 | PCI_BRIDGE_CTL_VGA_16BIT | | |
670 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
671 | PCI_BRIDGE_CTL_BUS_RESET | | |
672 | PCI_BRIDGE_CTL_FAST_BACK | | |
673 | PCI_BRIDGE_CTL_DISCARD | | |
674 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
675 | PCI_BRIDGE_CTL_DISCARD_SERR); |
676 | /* Below does not do anything as we never set this bit, put here for | |
677 | * completeness. */ | |
678 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
679 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
d5f27e88 | 680 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
15ab7a75 | 681 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
d5f27e88 MT |
682 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
683 | PCI_PREF_RANGE_TYPE_MASK); | |
15ab7a75 MT |
684 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
685 | PCI_PREF_RANGE_TYPE_MASK); | |
fb231628 IY |
686 | } |
687 | ||
6eab3de1 IY |
688 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
689 | { | |
690 | uint8_t slot = PCI_SLOT(dev->devfn); | |
691 | uint8_t func; | |
692 | ||
693 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
694 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
695 | } | |
696 | ||
697 | /* | |
b0cd712c | 698 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
699 | * - all functions must set the bit to 1. |
700 | * Example: Intel X53 | |
701 | * - function 0 must set the bit, but the rest function (> 0) | |
702 | * is allowed to leave the bit to 0. | |
703 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
704 | * | |
705 | * So OS (at least Linux) checks the bit of only function 0, | |
706 | * and doesn't see the bit of function > 0. | |
707 | * | |
708 | * The below check allows both interpretation. | |
709 | */ | |
710 | if (PCI_FUNC(dev->devfn)) { | |
711 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
712 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
713 | /* function 0 should set multifunction bit */ | |
714 | error_report("PCI: single function device can't be populated " | |
715 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
716 | return -1; | |
717 | } | |
718 | return 0; | |
719 | } | |
720 | ||
721 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
722 | return 0; | |
723 | } | |
724 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
725 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
726 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
727 | error_report("PCI: %x.0 indicates single function, " | |
728 | "but %x.%x is already populated.", | |
729 | slot, slot, func); | |
730 | return -1; | |
731 | } | |
732 | } | |
733 | return 0; | |
734 | } | |
735 | ||
a9f49946 IY |
736 | static void pci_config_alloc(PCIDevice *pci_dev) |
737 | { | |
738 | int config_size = pci_config_size(pci_dev); | |
739 | ||
7267c094 AL |
740 | pci_dev->config = g_malloc0(config_size); |
741 | pci_dev->cmask = g_malloc0(config_size); | |
742 | pci_dev->wmask = g_malloc0(config_size); | |
743 | pci_dev->w1cmask = g_malloc0(config_size); | |
744 | pci_dev->used = g_malloc0(config_size); | |
a9f49946 IY |
745 | } |
746 | ||
747 | static void pci_config_free(PCIDevice *pci_dev) | |
748 | { | |
7267c094 AL |
749 | g_free(pci_dev->config); |
750 | g_free(pci_dev->cmask); | |
751 | g_free(pci_dev->wmask); | |
752 | g_free(pci_dev->w1cmask); | |
753 | g_free(pci_dev->used); | |
a9f49946 IY |
754 | } |
755 | ||
69b91039 | 756 | /* -1 for devfn means auto assign */ |
6b1b92d3 | 757 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
40021f08 | 758 | const char *name, int devfn) |
69b91039 | 759 | { |
40021f08 AL |
760 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
761 | PCIConfigReadFunc *config_read = pc->config_read; | |
762 | PCIConfigWriteFunc *config_write = pc->config_write; | |
113f89df | 763 | |
69b91039 | 764 | if (devfn < 0) { |
b47b0706 | 765 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 766 | devfn += PCI_FUNC_MAX) { |
30468f78 | 767 | if (!bus->devices[devfn]) |
69b91039 FB |
768 | goto found; |
769 | } | |
3709c1b7 | 770 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 771 | return NULL; |
69b91039 | 772 | found: ; |
07b7d053 | 773 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
774 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
775 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 776 | return NULL; |
69b91039 | 777 | } |
30468f78 | 778 | pci_dev->bus = bus; |
5fa45de5 DG |
779 | if (bus->dma_context_fn) { |
780 | pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn); | |
817dcc53 AK |
781 | } else { |
782 | /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is | |
783 | * taken unconditionally */ | |
784 | /* FIXME: inherit memory region from bus creator */ | |
1c380f94 AK |
785 | memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master", |
786 | get_system_memory(), 0, | |
787 | memory_region_size(get_system_memory())); | |
788 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); | |
789 | address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region); | |
817dcc53 AK |
790 | pci_dev->dma = g_new(DMAContext, 1); |
791 | dma_context_init(pci_dev->dma, &pci_dev->bus_master_as, NULL, NULL, NULL); | |
5fa45de5 | 792 | } |
69b91039 FB |
793 | pci_dev->devfn = devfn; |
794 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 795 | pci_dev->irq_state = 0; |
a9f49946 | 796 | pci_config_alloc(pci_dev); |
fb231628 | 797 | |
40021f08 AL |
798 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
799 | pci_config_set_device_id(pci_dev->config, pc->device_id); | |
800 | pci_config_set_revision(pci_dev->config, pc->revision); | |
801 | pci_config_set_class(pci_dev->config, pc->class_id); | |
113f89df | 802 | |
40021f08 AL |
803 | if (!pc->is_bridge) { |
804 | if (pc->subsystem_vendor_id || pc->subsystem_id) { | |
113f89df | 805 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
40021f08 | 806 | pc->subsystem_vendor_id); |
113f89df | 807 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
40021f08 | 808 | pc->subsystem_id); |
113f89df IY |
809 | } else { |
810 | pci_set_default_subsystem_id(pci_dev); | |
811 | } | |
812 | } else { | |
813 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
40021f08 AL |
814 | assert(!pc->subsystem_vendor_id); |
815 | assert(!pc->subsystem_id); | |
fb231628 | 816 | } |
bd4b65ee | 817 | pci_init_cmask(pci_dev); |
b7ee1603 | 818 | pci_init_wmask(pci_dev); |
89d437df | 819 | pci_init_w1cmask(pci_dev); |
40021f08 | 820 | if (pc->is_bridge) { |
d5f27e88 | 821 | pci_init_mask_bridge(pci_dev); |
fb231628 | 822 | } |
6eab3de1 IY |
823 | if (pci_init_multifunction(bus, pci_dev)) { |
824 | pci_config_free(pci_dev); | |
825 | return NULL; | |
826 | } | |
0ac32c83 FB |
827 | |
828 | if (!config_read) | |
829 | config_read = pci_default_read_config; | |
830 | if (!config_write) | |
831 | config_write = pci_default_write_config; | |
69b91039 FB |
832 | pci_dev->config_read = config_read; |
833 | pci_dev->config_write = config_write; | |
30468f78 | 834 | bus->devices[devfn] = pci_dev; |
e369cad7 | 835 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 836 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
837 | return pci_dev; |
838 | } | |
839 | ||
925fe64a AW |
840 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
841 | { | |
842 | qemu_free_irqs(pci_dev->irq); | |
843 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
844 | pci_config_free(pci_dev); | |
817dcc53 AK |
845 | |
846 | if (!pci_dev->bus->dma_context_fn) { | |
847 | address_space_destroy(&pci_dev->bus_master_as); | |
1c380f94 | 848 | memory_region_destroy(&pci_dev->bus_master_enable_region); |
817dcc53 AK |
849 | g_free(pci_dev->dma); |
850 | pci_dev->dma = NULL; | |
851 | } | |
925fe64a AW |
852 | } |
853 | ||
5851e08c AL |
854 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
855 | { | |
856 | PCIIORegion *r; | |
857 | int i; | |
858 | ||
859 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
860 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 861 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 862 | continue; |
03952339 | 863 | memory_region_del_subregion(r->address_space, r->memory); |
5851e08c AL |
864 | } |
865 | } | |
866 | ||
a36a344d | 867 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 868 | { |
40021f08 AL |
869 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
870 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); | |
5851e08c AL |
871 | |
872 | pci_unregister_io_regions(pci_dev); | |
230741dc | 873 | pci_del_option_rom(pci_dev); |
7cf1b0fd | 874 | |
f90c2bcd AW |
875 | if (pc->exit) { |
876 | pc->exit(pci_dev); | |
877 | } | |
5851e08c | 878 | |
925fe64a | 879 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
880 | return 0; |
881 | } | |
882 | ||
e824b2cc AK |
883 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
884 | uint8_t type, MemoryRegion *memory) | |
69b91039 FB |
885 | { |
886 | PCIIORegion *r; | |
d7ce493a | 887 | uint32_t addr; |
5a9ff381 | 888 | uint64_t wmask; |
cfc0be25 | 889 | pcibus_t size = memory_region_size(memory); |
a4c20c6a | 890 | |
2bbb9c2f IY |
891 | assert(region_num >= 0); |
892 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
893 | if (size & (size-1)) { |
894 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 895 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
896 | exit(1); |
897 | } | |
898 | ||
69b91039 | 899 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 900 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
901 | r->size = size; |
902 | r->type = type; | |
79ff8cb0 | 903 | r->memory = NULL; |
b7ee1603 MT |
904 | |
905 | wmask = ~(size - 1); | |
b3b11697 | 906 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 907 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 908 | /* ROM enable bit is writable */ |
5330de09 | 909 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 910 | } |
b0ff8eb2 | 911 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
912 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
913 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
914 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
915 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
916 | } else { | |
917 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
918 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
919 | } | |
79ff8cb0 | 920 | pci_dev->io_regions[region_num].memory = memory; |
5968eca3 | 921 | pci_dev->io_regions[region_num].address_space |
cfc0be25 | 922 | = type & PCI_BASE_ADDRESS_SPACE_IO |
5968eca3 AK |
923 | ? pci_dev->bus->address_space_io |
924 | : pci_dev->bus->address_space_mem; | |
79ff8cb0 AK |
925 | } |
926 | ||
16a96f28 AK |
927 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
928 | { | |
929 | return pci_dev->io_regions[region_num].addr; | |
930 | } | |
931 | ||
876a350d MT |
932 | static pcibus_t pci_bar_address(PCIDevice *d, |
933 | int reg, uint8_t type, pcibus_t size) | |
934 | { | |
935 | pcibus_t new_addr, last_addr; | |
936 | int bar = pci_bar(d, reg); | |
937 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
938 | ||
939 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
940 | if (!(cmd & PCI_COMMAND_IO)) { | |
941 | return PCI_BAR_UNMAPPED; | |
942 | } | |
943 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
944 | last_addr = new_addr + size - 1; | |
945 | /* NOTE: we have only 64K ioports on PC */ | |
946 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
947 | return PCI_BAR_UNMAPPED; | |
948 | } | |
949 | return new_addr; | |
950 | } | |
951 | ||
952 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
953 | return PCI_BAR_UNMAPPED; | |
954 | } | |
955 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
956 | new_addr = pci_get_quad(d->config + bar); | |
957 | } else { | |
958 | new_addr = pci_get_long(d->config + bar); | |
959 | } | |
960 | /* the ROM slot has a specific enable bit */ | |
961 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
962 | return PCI_BAR_UNMAPPED; | |
963 | } | |
964 | new_addr &= ~(size - 1); | |
965 | last_addr = new_addr + size - 1; | |
966 | /* NOTE: we do not support wrapping */ | |
967 | /* XXX: as we cannot support really dynamic | |
968 | mappings, we handle specific values as invalid | |
969 | mappings. */ | |
970 | if (last_addr <= new_addr || new_addr == 0 || | |
971 | last_addr == PCI_BAR_UNMAPPED) { | |
972 | return PCI_BAR_UNMAPPED; | |
973 | } | |
974 | ||
975 | /* Now pcibus_t is 64bit. | |
976 | * Check if 32 bit BAR wraps around explicitly. | |
977 | * Without this, PC ide doesn't work well. | |
978 | * TODO: remove this work around. | |
979 | */ | |
980 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
981 | return PCI_BAR_UNMAPPED; | |
982 | } | |
983 | ||
984 | /* | |
985 | * OS is allowed to set BAR beyond its addressable | |
986 | * bits. For example, 32 bit OS can set 64bit bar | |
987 | * to >4G. Check it. TODO: we might need to support | |
988 | * it in the future for e.g. PAE. | |
989 | */ | |
a8170e5e | 990 | if (last_addr >= HWADDR_MAX) { |
876a350d MT |
991 | return PCI_BAR_UNMAPPED; |
992 | } | |
993 | ||
994 | return new_addr; | |
995 | } | |
996 | ||
0ac32c83 FB |
997 | static void pci_update_mappings(PCIDevice *d) |
998 | { | |
999 | PCIIORegion *r; | |
876a350d | 1000 | int i; |
7df32ca0 | 1001 | pcibus_t new_addr; |
3b46e624 | 1002 | |
8a8696a3 | 1003 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1004 | r = &d->io_regions[i]; |
a9688570 IY |
1005 | |
1006 | /* this region isn't registered */ | |
ec503442 | 1007 | if (!r->size) |
a9688570 IY |
1008 | continue; |
1009 | ||
876a350d | 1010 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 IY |
1011 | |
1012 | /* This bar isn't changed */ | |
7df32ca0 | 1013 | if (new_addr == r->addr) |
a9688570 IY |
1014 | continue; |
1015 | ||
1016 | /* now do the real mapping */ | |
1017 | if (r->addr != PCI_BAR_UNMAPPED) { | |
03952339 | 1018 | memory_region_del_subregion(r->address_space, r->memory); |
0ac32c83 | 1019 | } |
a9688570 IY |
1020 | r->addr = new_addr; |
1021 | if (r->addr != PCI_BAR_UNMAPPED) { | |
8b881e77 AK |
1022 | memory_region_add_subregion_overlap(r->address_space, |
1023 | r->addr, r->memory, 1); | |
a9688570 | 1024 | } |
0ac32c83 FB |
1025 | } |
1026 | } | |
1027 | ||
a7b15a5c MT |
1028 | static inline int pci_irq_disabled(PCIDevice *d) |
1029 | { | |
1030 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1031 | } | |
1032 | ||
1033 | /* Called after interrupt disabled field update in config space, | |
1034 | * assert/deassert interrupts if necessary. | |
1035 | * Gets original interrupt disable bit value (before update). */ | |
1036 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1037 | { | |
1038 | int i, disabled = pci_irq_disabled(d); | |
1039 | if (disabled == was_irq_disabled) | |
1040 | return; | |
1041 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1042 | int state = pci_irq_state(d, i); | |
1043 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1044 | } | |
1045 | } | |
1046 | ||
5fafdf24 | 1047 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1048 | uint32_t address, int len) |
69b91039 | 1049 | { |
5029fe12 | 1050 | uint32_t val = 0; |
42e4126b | 1051 | |
5029fe12 IY |
1052 | memcpy(&val, d->config + address, len); |
1053 | return le32_to_cpu(val); | |
0ac32c83 FB |
1054 | } |
1055 | ||
b7ee1603 | 1056 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 1057 | { |
a7b15a5c | 1058 | int i, was_irq_disabled = pci_irq_disabled(d); |
0ac32c83 | 1059 | |
42e4126b | 1060 | for (i = 0; i < l; val >>= 8, ++i) { |
91011d4f | 1061 | uint8_t wmask = d->wmask[addr + i]; |
92ba5f51 IY |
1062 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1063 | assert(!(wmask & w1cmask)); | |
91011d4f | 1064 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1065 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1066 | } |
260c0cd3 | 1067 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1068 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1069 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1070 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1071 | pci_update_mappings(d); |
a7b15a5c | 1072 | |
1c380f94 | 1073 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
a7b15a5c | 1074 | pci_update_irq_disabled(d, was_irq_disabled); |
1c380f94 AK |
1075 | memory_region_set_enabled(&d->bus_master_enable_region, |
1076 | pci_get_word(d->config + PCI_COMMAND) | |
1077 | & PCI_COMMAND_MASTER); | |
1078 | } | |
95d65800 JK |
1079 | |
1080 | msi_write_config(d, addr, val, l); | |
1081 | msix_write_config(d, addr, val, l); | |
69b91039 FB |
1082 | } |
1083 | ||
502a5395 PB |
1084 | /***********************************************************/ |
1085 | /* generic PCI irq support */ | |
30468f78 | 1086 | |
502a5395 | 1087 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1088 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1089 | { |
a60380a5 | 1090 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1091 | int change; |
3b46e624 | 1092 | |
d036bb21 | 1093 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1094 | if (!change) |
1095 | return; | |
d2b59317 | 1096 | |
d036bb21 | 1097 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1098 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1099 | if (pci_irq_disabled(pci_dev)) |
1100 | return; | |
d036bb21 | 1101 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1102 | } |
1103 | ||
3afa9bb4 MT |
1104 | /* Special hooks used by device assignment */ |
1105 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) | |
1106 | { | |
1107 | assert(!bus->parent_dev); | |
1108 | bus->route_intx_to_irq = route_intx_to_irq; | |
1109 | } | |
1110 | ||
1111 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) | |
1112 | { | |
1113 | PCIBus *bus; | |
1114 | ||
1115 | do { | |
1116 | bus = dev->bus; | |
1117 | pin = bus->map_irq(dev, pin); | |
1118 | dev = bus->parent_dev; | |
1119 | } while (dev); | |
05c0621e AW |
1120 | |
1121 | if (!bus->route_intx_to_irq) { | |
1122 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)\n", | |
1123 | object_get_typename(OBJECT(bus->qbus.parent))); | |
1124 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; | |
1125 | } | |
1126 | ||
3afa9bb4 | 1127 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
0ae16251 JK |
1128 | } |
1129 | ||
d6e65d54 AW |
1130 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1131 | { | |
1132 | return old->mode != new->mode || old->irq != new->irq; | |
1133 | } | |
1134 | ||
0ae16251 JK |
1135 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1136 | { | |
1137 | PCIDevice *dev; | |
1138 | PCIBus *sec; | |
1139 | int i; | |
1140 | ||
1141 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1142 | dev = bus->devices[i]; | |
1143 | if (dev && dev->intx_routing_notifier) { | |
1144 | dev->intx_routing_notifier(dev); | |
1145 | } | |
1146 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1147 | pci_bus_fire_intx_routing_notifier(sec); | |
1148 | } | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
1153 | PCIINTxRoutingNotifier notifier) | |
1154 | { | |
1155 | dev->intx_routing_notifier = notifier; | |
69b91039 FB |
1156 | } |
1157 | ||
91e56159 IY |
1158 | /* |
1159 | * PCI-to-PCI bridge specification | |
1160 | * 9.1: Interrupt routing. Table 9-1 | |
1161 | * | |
1162 | * the PCI Express Base Specification, Revision 2.1 | |
1163 | * 2.2.8.1: INTx interrutp signaling - Rules | |
1164 | * the Implementation Note | |
1165 | * Table 2-20 | |
1166 | */ | |
1167 | /* | |
1168 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD | |
1169 | * 0-origin unlike PCI interrupt pin register. | |
1170 | */ | |
1171 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) | |
1172 | { | |
1173 | return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; | |
1174 | } | |
1175 | ||
502a5395 PB |
1176 | /***********************************************************/ |
1177 | /* monitor info on PCI */ | |
0ac32c83 | 1178 | |
6650ee6d PB |
1179 | typedef struct { |
1180 | uint16_t class; | |
1181 | const char *desc; | |
5e0259e7 GN |
1182 | const char *fw_name; |
1183 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1184 | } pci_class_desc; |
1185 | ||
09bc878a | 1186 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1187 | { |
5e0259e7 GN |
1188 | { 0x0001, "VGA controller", "display"}, |
1189 | { 0x0100, "SCSI controller", "scsi"}, | |
1190 | { 0x0101, "IDE controller", "ide"}, | |
1191 | { 0x0102, "Floppy controller", "fdc"}, | |
1192 | { 0x0103, "IPI controller", "ipi"}, | |
1193 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1194 | { 0x0106, "SATA controller"}, |
1195 | { 0x0107, "SAS controller"}, | |
1196 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1197 | { 0x0200, "Ethernet controller", "ethernet"}, |
1198 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1199 | { 0x0202, "FDDI controller", "fddi"}, | |
1200 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1201 | { 0x0280, "Network controller"}, |
5e0259e7 | 1202 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1203 | { 0x0301, "XGA controller"}, |
1204 | { 0x0302, "3D controller"}, | |
1205 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1206 | { 0x0400, "Video controller", "video"}, |
1207 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1208 | { 0x0402, "Phone"}, |
602ef4d9 | 1209 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1210 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1211 | { 0x0500, "RAM controller", "memory"}, |
1212 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1213 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1214 | { 0x0600, "Host bridge", "host"}, |
1215 | { 0x0601, "ISA bridge", "isa"}, | |
1216 | { 0x0602, "EISA bridge", "eisa"}, | |
1217 | { 0x0603, "MC bridge", "mca"}, | |
1218 | { 0x0604, "PCI bridge", "pci"}, | |
1219 | { 0x0605, "PCMCIA bridge", "pcmcia"}, | |
1220 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1221 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1222 | { 0x0608, "RACEWAY bridge"}, |
1223 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1224 | { 0x0700, "Serial port", "serial"}, |
1225 | { 0x0701, "Parallel port", "parallel"}, | |
1226 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1227 | { 0x0801, "DMA controller", "dma-controller"}, | |
1228 | { 0x0802, "Timer", "timer"}, | |
1229 | { 0x0803, "RTC", "rtc"}, | |
1230 | { 0x0900, "Keyboard", "keyboard"}, | |
1231 | { 0x0901, "Pen", "pen"}, | |
1232 | { 0x0902, "Mouse", "mouse"}, | |
1233 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1234 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
1235 | { 0x0c00, "Fireware contorller", "fireware"}, | |
1236 | { 0x0c01, "Access bus controller", "access-bus"}, | |
1237 | { 0x0c02, "SSA controller", "ssa"}, | |
1238 | { 0x0c03, "USB controller", "usb"}, | |
1239 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
f7748569 | 1240 | { 0x0c05, "SMBus"}, |
6650ee6d PB |
1241 | { 0, NULL} |
1242 | }; | |
1243 | ||
163c8a59 | 1244 | static void pci_for_each_device_under_bus(PCIBus *bus, |
7aa8cbb9 AP |
1245 | void (*fn)(PCIBus *b, PCIDevice *d, |
1246 | void *opaque), | |
1247 | void *opaque) | |
30468f78 | 1248 | { |
163c8a59 LC |
1249 | PCIDevice *d; |
1250 | int devfn; | |
30468f78 | 1251 | |
163c8a59 LC |
1252 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1253 | d = bus->devices[devfn]; | |
1254 | if (d) { | |
7aa8cbb9 | 1255 | fn(bus, d, opaque); |
163c8a59 LC |
1256 | } |
1257 | } | |
1258 | } | |
1259 | ||
1260 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
7aa8cbb9 AP |
1261 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1262 | void *opaque) | |
163c8a59 | 1263 | { |
d662210a | 1264 | bus = pci_find_bus_nr(bus, bus_num); |
163c8a59 LC |
1265 | |
1266 | if (bus) { | |
7aa8cbb9 | 1267 | pci_for_each_device_under_bus(bus, fn, opaque); |
163c8a59 LC |
1268 | } |
1269 | } | |
1270 | ||
79627472 | 1271 | static const pci_class_desc *get_class_desc(int class) |
163c8a59 | 1272 | { |
79627472 | 1273 | const pci_class_desc *desc; |
163c8a59 | 1274 | |
79627472 LC |
1275 | desc = pci_class_descriptions; |
1276 | while (desc->desc && class != desc->class) { | |
1277 | desc++; | |
30468f78 | 1278 | } |
b4dccd8d | 1279 | |
79627472 LC |
1280 | return desc; |
1281 | } | |
14421258 | 1282 | |
79627472 | 1283 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
163c8a59 | 1284 | |
79627472 LC |
1285 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1286 | { | |
1287 | PciMemoryRegionList *head = NULL, *cur_item = NULL; | |
1288 | int i; | |
163c8a59 | 1289 | |
79627472 LC |
1290 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1291 | const PCIIORegion *r = &dev->io_regions[i]; | |
1292 | PciMemoryRegionList *region; | |
1293 | ||
1294 | if (!r->size) { | |
1295 | continue; | |
502a5395 | 1296 | } |
163c8a59 | 1297 | |
79627472 LC |
1298 | region = g_malloc0(sizeof(*region)); |
1299 | region->value = g_malloc0(sizeof(*region->value)); | |
163c8a59 | 1300 | |
79627472 LC |
1301 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1302 | region->value->type = g_strdup("io"); | |
1303 | } else { | |
1304 | region->value->type = g_strdup("memory"); | |
1305 | region->value->has_prefetch = true; | |
1306 | region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1307 | region->value->has_mem_type_64 = true; | |
1308 | region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
d5e4acf7 | 1309 | } |
163c8a59 | 1310 | |
79627472 LC |
1311 | region->value->bar = i; |
1312 | region->value->address = r->addr; | |
1313 | region->value->size = r->size; | |
163c8a59 | 1314 | |
79627472 LC |
1315 | /* XXX: waiting for the qapi to support GSList */ |
1316 | if (!cur_item) { | |
1317 | head = cur_item = region; | |
1318 | } else { | |
1319 | cur_item->next = region; | |
1320 | cur_item = region; | |
163c8a59 | 1321 | } |
80b3ada7 | 1322 | } |
384d8876 | 1323 | |
79627472 | 1324 | return head; |
163c8a59 LC |
1325 | } |
1326 | ||
79627472 LC |
1327 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1328 | int bus_num) | |
163c8a59 | 1329 | { |
79627472 | 1330 | PciBridgeInfo *info; |
163c8a59 | 1331 | |
79627472 | 1332 | info = g_malloc0(sizeof(*info)); |
163c8a59 | 1333 | |
79627472 LC |
1334 | info->bus.number = dev->config[PCI_PRIMARY_BUS]; |
1335 | info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; | |
1336 | info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
163c8a59 | 1337 | |
79627472 LC |
1338 | info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); |
1339 | info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
1340 | info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
163c8a59 | 1341 | |
79627472 LC |
1342 | info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); |
1343 | info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
1344 | info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
163c8a59 | 1345 | |
79627472 LC |
1346 | info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); |
1347 | info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1348 | info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
163c8a59 | 1349 | |
79627472 | 1350 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
d662210a | 1351 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
79627472 LC |
1352 | if (child_bus) { |
1353 | info->has_devices = true; | |
1354 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); | |
1355 | } | |
163c8a59 LC |
1356 | } |
1357 | ||
79627472 | 1358 | return info; |
163c8a59 LC |
1359 | } |
1360 | ||
79627472 LC |
1361 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1362 | int bus_num) | |
163c8a59 | 1363 | { |
79627472 LC |
1364 | const pci_class_desc *desc; |
1365 | PciDeviceInfo *info; | |
b5937f29 | 1366 | uint8_t type; |
79627472 | 1367 | int class; |
163c8a59 | 1368 | |
79627472 LC |
1369 | info = g_malloc0(sizeof(*info)); |
1370 | info->bus = bus_num; | |
1371 | info->slot = PCI_SLOT(dev->devfn); | |
1372 | info->function = PCI_FUNC(dev->devfn); | |
1373 | ||
1374 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1375 | info->class_info.class = class; | |
1376 | desc = get_class_desc(class); | |
1377 | if (desc->desc) { | |
1378 | info->class_info.has_desc = true; | |
1379 | info->class_info.desc = g_strdup(desc->desc); | |
1380 | } | |
1381 | ||
1382 | info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); | |
1383 | info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); | |
1384 | info->regions = qmp_query_pci_regions(dev); | |
1385 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); | |
163c8a59 LC |
1386 | |
1387 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
79627472 LC |
1388 | info->has_irq = true; |
1389 | info->irq = dev->config[PCI_INTERRUPT_LINE]; | |
163c8a59 LC |
1390 | } |
1391 | ||
b5937f29 IY |
1392 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1393 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
79627472 LC |
1394 | info->has_pci_bridge = true; |
1395 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); | |
163c8a59 LC |
1396 | } |
1397 | ||
79627472 | 1398 | return info; |
163c8a59 LC |
1399 | } |
1400 | ||
79627472 | 1401 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
384d8876 | 1402 | { |
79627472 | 1403 | PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
163c8a59 | 1404 | PCIDevice *dev; |
79627472 | 1405 | int devfn; |
163c8a59 LC |
1406 | |
1407 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1408 | dev = bus->devices[devfn]; | |
1409 | if (dev) { | |
79627472 LC |
1410 | info = g_malloc0(sizeof(*info)); |
1411 | info->value = qmp_query_pci_device(dev, bus, bus_num); | |
1412 | ||
1413 | /* XXX: waiting for the qapi to support GSList */ | |
1414 | if (!cur_item) { | |
1415 | head = cur_item = info; | |
1416 | } else { | |
1417 | cur_item->next = info; | |
1418 | cur_item = info; | |
1419 | } | |
163c8a59 | 1420 | } |
1074df4f | 1421 | } |
163c8a59 | 1422 | |
79627472 | 1423 | return head; |
1074df4f IY |
1424 | } |
1425 | ||
79627472 | 1426 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1074df4f | 1427 | { |
79627472 LC |
1428 | PciInfo *info = NULL; |
1429 | ||
d662210a | 1430 | bus = pci_find_bus_nr(bus, bus_num); |
502a5395 | 1431 | if (bus) { |
79627472 LC |
1432 | info = g_malloc0(sizeof(*info)); |
1433 | info->bus = bus_num; | |
1434 | info->devices = qmp_query_pci_devices(bus, bus_num); | |
f2aa58c6 | 1435 | } |
163c8a59 | 1436 | |
79627472 | 1437 | return info; |
f2aa58c6 FB |
1438 | } |
1439 | ||
79627472 | 1440 | PciInfoList *qmp_query_pci(Error **errp) |
f2aa58c6 | 1441 | { |
79627472 | 1442 | PciInfoList *info, *head = NULL, *cur_item = NULL; |
e822a52a | 1443 | struct PCIHostBus *host; |
163c8a59 | 1444 | |
e822a52a | 1445 | QLIST_FOREACH(host, &host_buses, next) { |
79627472 LC |
1446 | info = g_malloc0(sizeof(*info)); |
1447 | info->value = qmp_query_pci_bus(host->bus, 0); | |
1448 | ||
1449 | /* XXX: waiting for the qapi to support GSList */ | |
1450 | if (!cur_item) { | |
1451 | head = cur_item = info; | |
1452 | } else { | |
1453 | cur_item->next = info; | |
1454 | cur_item = info; | |
163c8a59 | 1455 | } |
e822a52a | 1456 | } |
163c8a59 | 1457 | |
79627472 | 1458 | return head; |
77d4bc34 | 1459 | } |
a41b2ff2 | 1460 | |
cb457d76 AL |
1461 | static const char * const pci_nic_models[] = { |
1462 | "ne2k_pci", | |
1463 | "i82551", | |
1464 | "i82557b", | |
1465 | "i82559er", | |
1466 | "rtl8139", | |
1467 | "e1000", | |
1468 | "pcnet", | |
1469 | "virtio", | |
1470 | NULL | |
1471 | }; | |
1472 | ||
9d07d757 PB |
1473 | static const char * const pci_nic_names[] = { |
1474 | "ne2k_pci", | |
1475 | "i82551", | |
1476 | "i82557b", | |
1477 | "i82559er", | |
1478 | "rtl8139", | |
1479 | "e1000", | |
1480 | "pcnet", | |
53c25cea | 1481 | "virtio-net-pci", |
cb457d76 AL |
1482 | NULL |
1483 | }; | |
1484 | ||
a41b2ff2 | 1485 | /* Initialize a PCI NIC. */ |
33e66b86 | 1486 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1487 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1488 | const char *default_devaddr) | |
a41b2ff2 | 1489 | { |
5607c388 | 1490 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1491 | PCIBus *bus; |
1492 | int devfn; | |
5607c388 | 1493 | PCIDevice *pci_dev; |
9d07d757 | 1494 | DeviceState *dev; |
cb457d76 AL |
1495 | int i; |
1496 | ||
07caea31 MA |
1497 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1498 | if (i < 0) | |
1499 | return NULL; | |
1500 | ||
1501 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1502 | if (!bus) { | |
1ecda02b MA |
1503 | error_report("Invalid PCI device address %s for device %s", |
1504 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1505 | return NULL; |
1506 | } | |
1507 | ||
499cf102 | 1508 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1509 | dev = &pci_dev->qdev; |
1cc33683 | 1510 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1511 | if (qdev_init(dev) < 0) |
1512 | return NULL; | |
9ee05825 | 1513 | return pci_dev; |
a41b2ff2 PB |
1514 | } |
1515 | ||
07caea31 MA |
1516 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1517 | const char *default_devaddr) | |
1518 | { | |
1519 | PCIDevice *res; | |
1520 | ||
1521 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1522 | exit(0); | |
1523 | ||
1524 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1525 | if (!res) | |
1526 | exit(1); | |
1527 | return res; | |
1528 | } | |
1529 | ||
129d42fb AJ |
1530 | PCIDevice *pci_vga_init(PCIBus *bus) |
1531 | { | |
1532 | switch (vga_interface_type) { | |
1533 | case VGA_CIRRUS: | |
1534 | return pci_create_simple(bus, -1, "cirrus-vga"); | |
1535 | case VGA_QXL: | |
1536 | return pci_create_simple(bus, -1, "qxl-vga"); | |
1537 | case VGA_STD: | |
1538 | return pci_create_simple(bus, -1, "VGA"); | |
1539 | case VGA_VMWARE: | |
1540 | return pci_create_simple(bus, -1, "vmware-svga"); | |
1541 | case VGA_NONE: | |
1542 | default: /* Other non-PCI types. Checking for unsupported types is already | |
1543 | done in vl.c. */ | |
1544 | return NULL; | |
1545 | } | |
1546 | } | |
1547 | ||
929176c3 MT |
1548 | /* Whether a given bus number is in range of the secondary |
1549 | * bus of the given bridge device. */ | |
1550 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
1551 | { | |
1552 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
1553 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
1554 | dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1555 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; | |
1556 | } | |
1557 | ||
d662210a | 1558 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
3ae80618 | 1559 | { |
470e6363 | 1560 | PCIBus *sec; |
3ae80618 | 1561 | |
470e6363 | 1562 | if (!bus) { |
e822a52a | 1563 | return NULL; |
470e6363 | 1564 | } |
3ae80618 | 1565 | |
e822a52a IY |
1566 | if (pci_bus_num(bus) == bus_num) { |
1567 | return bus; | |
1568 | } | |
1569 | ||
929176c3 MT |
1570 | /* Consider all bus numbers in range for the host pci bridge. */ |
1571 | if (bus->parent_dev && | |
1572 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { | |
1573 | return NULL; | |
1574 | } | |
1575 | ||
e822a52a | 1576 | /* try child bus */ |
929176c3 MT |
1577 | for (; bus; bus = sec) { |
1578 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1579 | assert(sec->parent_dev); | |
1580 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1581 | return sec; | |
1582 | } | |
1583 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
1584 | break; | |
c021f8e6 | 1585 | } |
e822a52a IY |
1586 | } |
1587 | } | |
1588 | ||
1589 | return NULL; | |
3ae80618 AL |
1590 | } |
1591 | ||
5256d8bf | 1592 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 1593 | { |
d662210a | 1594 | bus = pci_find_bus_nr(bus, bus_num); |
3ae80618 AL |
1595 | |
1596 | if (!bus) | |
1597 | return NULL; | |
1598 | ||
5256d8bf | 1599 | return bus->devices[devfn]; |
3ae80618 AL |
1600 | } |
1601 | ||
d307af79 | 1602 | static int pci_qdev_init(DeviceState *qdev) |
6b1b92d3 PB |
1603 | { |
1604 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
40021f08 | 1605 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
6b1b92d3 | 1606 | PCIBus *bus; |
113f89df | 1607 | int rc; |
ab85ceb1 | 1608 | bool is_default_rom; |
6b1b92d3 | 1609 | |
a9f49946 | 1610 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
40021f08 | 1611 | if (pc->is_express) { |
a9f49946 IY |
1612 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1613 | } | |
1614 | ||
02e2da45 | 1615 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
6e008585 AL |
1616 | pci_dev = do_pci_register_device(pci_dev, bus, |
1617 | object_get_typename(OBJECT(qdev)), | |
1618 | pci_dev->devfn); | |
09e3acc6 GH |
1619 | if (pci_dev == NULL) |
1620 | return -1; | |
40021f08 | 1621 | if (qdev->hotplugged && pc->no_hotplug) { |
f79f2bfc | 1622 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); |
180c22e1 GH |
1623 | do_pci_unregister_device(pci_dev); |
1624 | return -1; | |
1625 | } | |
40021f08 AL |
1626 | if (pc->init) { |
1627 | rc = pc->init(pci_dev); | |
c2afc922 IY |
1628 | if (rc != 0) { |
1629 | do_pci_unregister_device(pci_dev); | |
1630 | return rc; | |
1631 | } | |
925fe64a | 1632 | } |
8c52c8f3 GH |
1633 | |
1634 | /* rom loading */ | |
ab85ceb1 | 1635 | is_default_rom = false; |
40021f08 AL |
1636 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1637 | pci_dev->romfile = g_strdup(pc->romfile); | |
ab85ceb1 SW |
1638 | is_default_rom = true; |
1639 | } | |
1640 | pci_add_option_rom(pci_dev, is_default_rom); | |
8c52c8f3 | 1641 | |
5beb8ad5 | 1642 | if (bus->hotplug) { |
e927d487 MT |
1643 | /* Let buses differentiate between hotplug and when device is |
1644 | * enabled during qemu machine creation. */ | |
1645 | rc = bus->hotplug(bus->hotplug_qdev, pci_dev, | |
1646 | qdev->hotplugged ? PCI_HOTPLUG_ENABLED: | |
1647 | PCI_COLDPLUG_ENABLED); | |
a213ff63 IY |
1648 | if (rc != 0) { |
1649 | int r = pci_unregister_device(&pci_dev->qdev); | |
1650 | assert(!r); | |
1651 | return rc; | |
1652 | } | |
1653 | } | |
ee995ffb GH |
1654 | return 0; |
1655 | } | |
1656 | ||
1657 | static int pci_unplug_device(DeviceState *qdev) | |
1658 | { | |
40021f08 AL |
1659 | PCIDevice *dev = PCI_DEVICE(qdev); |
1660 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
ee995ffb | 1661 | |
40021f08 | 1662 | if (pc->no_hotplug) { |
f79f2bfc | 1663 | qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); |
180c22e1 GH |
1664 | return -1; |
1665 | } | |
e927d487 MT |
1666 | return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, |
1667 | PCI_HOTPLUG_DISABLED); | |
6b1b92d3 PB |
1668 | } |
1669 | ||
49823868 IY |
1670 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1671 | const char *name) | |
6b1b92d3 PB |
1672 | { |
1673 | DeviceState *dev; | |
1674 | ||
02e2da45 | 1675 | dev = qdev_create(&bus->qbus, name); |
09f1bbcd | 1676 | qdev_prop_set_int32(dev, "addr", devfn); |
49823868 | 1677 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
40021f08 | 1678 | return PCI_DEVICE(dev); |
71077c1c | 1679 | } |
6b1b92d3 | 1680 | |
49823868 IY |
1681 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1682 | bool multifunction, | |
1683 | const char *name) | |
71077c1c | 1684 | { |
49823868 | 1685 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1686 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1687 | return dev; |
6b1b92d3 | 1688 | } |
6f4cbd39 | 1689 | |
49823868 IY |
1690 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1691 | { | |
1692 | return pci_create_multifunction(bus, devfn, false, name); | |
1693 | } | |
1694 | ||
1695 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1696 | { | |
1697 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1698 | } | |
1699 | ||
b56d701f | 1700 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
6f4cbd39 MT |
1701 | { |
1702 | int offset = PCI_CONFIG_HEADER_SIZE; | |
1703 | int i; | |
b56d701f | 1704 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
6f4cbd39 MT |
1705 | if (pdev->used[i]) |
1706 | offset = i + 1; | |
1707 | else if (i - offset + 1 == size) | |
1708 | return offset; | |
b56d701f | 1709 | } |
6f4cbd39 MT |
1710 | return 0; |
1711 | } | |
1712 | ||
1713 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1714 | uint8_t *prev_p) | |
1715 | { | |
1716 | uint8_t next, prev; | |
1717 | ||
1718 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1719 | return 0; | |
1720 | ||
1721 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1722 | prev = next + PCI_CAP_LIST_NEXT) | |
1723 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1724 | break; | |
1725 | ||
1726 | if (prev_p) | |
1727 | *prev_p = prev; | |
1728 | return next; | |
1729 | } | |
1730 | ||
c9abe111 JK |
1731 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
1732 | { | |
1733 | uint8_t next, prev, found = 0; | |
1734 | ||
1735 | if (!(pdev->used[offset])) { | |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); | |
1740 | ||
1741 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1742 | prev = next + PCI_CAP_LIST_NEXT) { | |
1743 | if (next <= offset && next > found) { | |
1744 | found = next; | |
1745 | } | |
1746 | } | |
1747 | return found; | |
1748 | } | |
1749 | ||
ab85ceb1 SW |
1750 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
1751 | This is needed for an option rom which is used for more than one device. */ | |
1752 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) | |
1753 | { | |
1754 | uint16_t vendor_id; | |
1755 | uint16_t device_id; | |
1756 | uint16_t rom_vendor_id; | |
1757 | uint16_t rom_device_id; | |
1758 | uint16_t rom_magic; | |
1759 | uint16_t pcir_offset; | |
1760 | uint8_t checksum; | |
1761 | ||
1762 | /* Words in rom data are little endian (like in PCI configuration), | |
1763 | so they can be read / written with pci_get_word / pci_set_word. */ | |
1764 | ||
1765 | /* Only a valid rom will be patched. */ | |
1766 | rom_magic = pci_get_word(ptr); | |
1767 | if (rom_magic != 0xaa55) { | |
1768 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
1769 | return; | |
1770 | } | |
1771 | pcir_offset = pci_get_word(ptr + 0x18); | |
1772 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
1773 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
1774 | return; | |
1775 | } | |
1776 | ||
1777 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1778 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1779 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
1780 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
1781 | ||
1782 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
1783 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
1784 | ||
1785 | checksum = ptr[6]; | |
1786 | ||
1787 | if (vendor_id != rom_vendor_id) { | |
1788 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
1789 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
1790 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
1791 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1792 | ptr[6] = checksum; | |
1793 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
1794 | } | |
1795 | ||
1796 | if (device_id != rom_device_id) { | |
1797 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
1798 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
1799 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
1800 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1801 | ptr[6] = checksum; | |
1802 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
1803 | } | |
1804 | } | |
1805 | ||
c2039bd0 | 1806 | /* Add an option rom for the device */ |
ab85ceb1 | 1807 | static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
c2039bd0 AL |
1808 | { |
1809 | int size; | |
1810 | char *path; | |
1811 | void *ptr; | |
1724f049 | 1812 | char name[32]; |
4be9f0d1 | 1813 | const VMStateDescription *vmsd; |
c2039bd0 | 1814 | |
8c52c8f3 GH |
1815 | if (!pdev->romfile) |
1816 | return 0; | |
1817 | if (strlen(pdev->romfile) == 0) | |
1818 | return 0; | |
1819 | ||
88169ddf GH |
1820 | if (!pdev->rom_bar) { |
1821 | /* | |
1822 | * Load rom via fw_cfg instead of creating a rom bar, | |
1823 | * for 0.11 compatibility. | |
1824 | */ | |
1825 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1826 | if (class == 0x0300) { | |
1827 | rom_add_vga(pdev->romfile); | |
1828 | } else { | |
2e55e842 | 1829 | rom_add_option(pdev->romfile, -1); |
88169ddf GH |
1830 | } |
1831 | return 0; | |
1832 | } | |
1833 | ||
8c52c8f3 | 1834 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1835 | if (path == NULL) { |
7267c094 | 1836 | path = g_strdup(pdev->romfile); |
c2039bd0 AL |
1837 | } |
1838 | ||
1839 | size = get_image_size(path); | |
8c52c8f3 | 1840 | if (size < 0) { |
1ecda02b MA |
1841 | error_report("%s: failed to find romfile \"%s\"", |
1842 | __FUNCTION__, pdev->romfile); | |
7267c094 | 1843 | g_free(path); |
8c52c8f3 GH |
1844 | return -1; |
1845 | } | |
c2039bd0 AL |
1846 | if (size & (size - 1)) { |
1847 | size = 1 << qemu_fls(size); | |
1848 | } | |
1849 | ||
4be9f0d1 AL |
1850 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
1851 | ||
1852 | if (vmsd) { | |
1853 | snprintf(name, sizeof(name), "%s.rom", vmsd->name); | |
1854 | } else { | |
f79f2bfc | 1855 | snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
4be9f0d1 | 1856 | } |
14caaf7f | 1857 | pdev->has_rom = true; |
c5705a77 AK |
1858 | memory_region_init_ram(&pdev->rom, name, size); |
1859 | vmstate_register_ram(&pdev->rom, &pdev->qdev); | |
14caaf7f | 1860 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
c2039bd0 | 1861 | load_image(path, ptr); |
7267c094 | 1862 | g_free(path); |
c2039bd0 | 1863 | |
ab85ceb1 SW |
1864 | if (is_default_rom) { |
1865 | /* Only the default rom images will be patched (if needed). */ | |
1866 | pci_patch_ids(pdev, ptr, size); | |
1867 | } | |
1868 | ||
8c12f191 JB |
1869 | qemu_put_ram_ptr(ptr); |
1870 | ||
e824b2cc | 1871 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
c2039bd0 AL |
1872 | |
1873 | return 0; | |
1874 | } | |
1875 | ||
230741dc AW |
1876 | static void pci_del_option_rom(PCIDevice *pdev) |
1877 | { | |
14caaf7f | 1878 | if (!pdev->has_rom) |
230741dc AW |
1879 | return; |
1880 | ||
c5705a77 | 1881 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
14caaf7f AK |
1882 | memory_region_destroy(&pdev->rom); |
1883 | pdev->has_rom = false; | |
230741dc AW |
1884 | } |
1885 | ||
ca77089d IY |
1886 | /* |
1887 | * if !offset | |
1888 | * Reserve space and add capability to the linked list in pci config space | |
1889 | * | |
1890 | * if offset = 0, | |
1891 | * Find and reserve space and add capability to the linked list | |
1892 | * in pci config space */ | |
1893 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
1894 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1895 | { |
ca77089d | 1896 | uint8_t *config; |
c9abe111 JK |
1897 | int i, overlapping_cap; |
1898 | ||
ca77089d IY |
1899 | if (!offset) { |
1900 | offset = pci_find_space(pdev, size); | |
1901 | if (!offset) { | |
1902 | return -ENOSPC; | |
1903 | } | |
c9abe111 JK |
1904 | } else { |
1905 | /* Verify that capabilities don't overlap. Note: device assignment | |
1906 | * depends on this check to verify that the device is not broken. | |
1907 | * Should never trigger for emulated devices, but it's helpful | |
1908 | * for debugging these. */ | |
1909 | for (i = offset; i < offset + size; i++) { | |
1910 | overlapping_cap = pci_find_capability_at_offset(pdev, i); | |
1911 | if (overlapping_cap) { | |
1912 | fprintf(stderr, "ERROR: %04x:%02x:%02x.%x " | |
1913 | "Attempt to add PCI capability %x at offset " | |
1914 | "%x overlaps existing capability %x at offset %x\n", | |
1915 | pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), | |
1916 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1917 | cap_id, offset, overlapping_cap, i); | |
1918 | return -EINVAL; | |
1919 | } | |
1920 | } | |
ca77089d IY |
1921 | } |
1922 | ||
1923 | config = pdev->config + offset; | |
6f4cbd39 MT |
1924 | config[PCI_CAP_LIST_ID] = cap_id; |
1925 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1926 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1927 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
e26631b7 | 1928 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
1929 | /* Make capability read-only by default */ |
1930 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1931 | /* Check capability by default */ |
1932 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1933 | return offset; |
1934 | } | |
1935 | ||
1936 | /* Unlink capability from the pci config space. */ | |
1937 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1938 | { | |
1939 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1940 | if (!offset) | |
1941 | return; | |
1942 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 1943 | /* Make capability writable again */ |
6f4cbd39 | 1944 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 1945 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
1946 | /* Clear cmask as device-specific registers can't be checked */ |
1947 | memset(pdev->cmask + offset, 0, size); | |
e26631b7 | 1948 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
1949 | |
1950 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1951 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1952 | } | |
1953 | ||
6f4cbd39 MT |
1954 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
1955 | { | |
1956 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1957 | } | |
10c4c98a GH |
1958 | |
1959 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1960 | { | |
1961 | PCIDevice *d = (PCIDevice *)dev; | |
1962 | const pci_class_desc *desc; | |
1963 | char ctxt[64]; | |
1964 | PCIIORegion *r; | |
1965 | int i, class; | |
1966 | ||
b0ff8eb2 | 1967 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1968 | desc = pci_class_descriptions; |
1969 | while (desc->desc && class != desc->class) | |
1970 | desc++; | |
1971 | if (desc->desc) { | |
1972 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1973 | } else { | |
1974 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1975 | } | |
1976 | ||
1977 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1978 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
7f5feab4 | 1979 | indent, "", ctxt, pci_bus_num(d->bus), |
e822a52a | 1980 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
1981 | pci_get_word(d->config + PCI_VENDOR_ID), |
1982 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1983 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1984 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1985 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1986 | r = &d->io_regions[i]; | |
1987 | if (!r->size) | |
1988 | continue; | |
89e8b13c IY |
1989 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1990 | " [0x%"FMT_PCIBUS"]\n", | |
1991 | indent, "", | |
0392a017 | 1992 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1993 | r->addr, r->addr + r->size - 1); |
1994 | } | |
1995 | } | |
03587182 | 1996 | |
5e0259e7 GN |
1997 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
1998 | { | |
1999 | PCIDevice *d = (PCIDevice *)dev; | |
2000 | const char *name = NULL; | |
2001 | const pci_class_desc *desc = pci_class_descriptions; | |
2002 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2003 | ||
2004 | while (desc->desc && | |
2005 | (class & ~desc->fw_ign_bits) != | |
2006 | (desc->class & ~desc->fw_ign_bits)) { | |
2007 | desc++; | |
2008 | } | |
2009 | ||
2010 | if (desc->desc) { | |
2011 | name = desc->fw_name; | |
2012 | } | |
2013 | ||
2014 | if (name) { | |
2015 | pstrcpy(buf, len, name); | |
2016 | } else { | |
2017 | snprintf(buf, len, "pci%04x,%04x", | |
2018 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2019 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2020 | } | |
2021 | ||
2022 | return buf; | |
2023 | } | |
2024 | ||
2025 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2026 | { | |
2027 | PCIDevice *d = (PCIDevice *)dev; | |
2028 | char path[50], name[33]; | |
2029 | int off; | |
2030 | ||
2031 | off = snprintf(path, sizeof(path), "%s@%x", | |
2032 | pci_dev_fw_name(dev, name, sizeof name), | |
2033 | PCI_SLOT(d->devfn)); | |
2034 | if (PCI_FUNC(d->devfn)) | |
2035 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
a5cf8262 | 2036 | return g_strdup(path); |
5e0259e7 GN |
2037 | } |
2038 | ||
4f43c1ff AW |
2039 | static char *pcibus_get_dev_path(DeviceState *dev) |
2040 | { | |
a6a7005d MT |
2041 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2042 | PCIDevice *t; | |
2043 | int slot_depth; | |
2044 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2045 | * 00 is added here to make this format compatible with | |
2046 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2047 | * Slot.Function list specifies the slot and function numbers for all | |
2048 | * devices on the path from root to the specific device. */ | |
2991181a MT |
2049 | char domain[] = "DDDD:00"; |
2050 | char slot[] = ":SS.F"; | |
2051 | int domain_len = sizeof domain - 1 /* For '\0' */; | |
2052 | int slot_len = sizeof slot - 1 /* For '\0' */; | |
a6a7005d MT |
2053 | int path_len; |
2054 | char *path, *p; | |
2991181a | 2055 | int s; |
a6a7005d MT |
2056 | |
2057 | /* Calculate # of slots on path between device and root. */; | |
2058 | slot_depth = 0; | |
2059 | for (t = d; t; t = t->bus->parent_dev) { | |
2060 | ++slot_depth; | |
2061 | } | |
2062 | ||
2063 | path_len = domain_len + slot_len * slot_depth; | |
2064 | ||
2065 | /* Allocate memory, fill in the terminating null byte. */ | |
7267c094 | 2066 | path = g_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2067 | path[path_len] = '\0'; |
2068 | ||
2069 | /* First field is the domain. */ | |
2991181a MT |
2070 | s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); |
2071 | assert(s == domain_len); | |
2072 | memcpy(path, domain, domain_len); | |
a6a7005d MT |
2073 | |
2074 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2075 | * them in the reverse order, last to first. */ | |
2076 | p = path + path_len; | |
2077 | for (t = d; t; t = t->bus->parent_dev) { | |
2078 | p -= slot_len; | |
2991181a | 2079 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2080 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2081 | assert(s == slot_len); |
2082 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2083 | } |
2084 | ||
2085 | return path; | |
4f43c1ff AW |
2086 | } |
2087 | ||
f3006dd1 IY |
2088 | static int pci_qdev_find_recursive(PCIBus *bus, |
2089 | const char *id, PCIDevice **pdev) | |
2090 | { | |
2091 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2092 | if (!qdev) { | |
2093 | return -ENODEV; | |
2094 | } | |
2095 | ||
2096 | /* roughly check if given qdev is pci device */ | |
4be9f0d1 | 2097 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
40021f08 | 2098 | *pdev = PCI_DEVICE(qdev); |
f3006dd1 IY |
2099 | return 0; |
2100 | } | |
2101 | return -EINVAL; | |
2102 | } | |
2103 | ||
2104 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2105 | { | |
2106 | struct PCIHostBus *host; | |
2107 | int rc = -ENODEV; | |
2108 | ||
2109 | QLIST_FOREACH(host, &host_buses, next) { | |
2110 | int tmp = pci_qdev_find_recursive(host->bus, id, pdev); | |
2111 | if (!tmp) { | |
2112 | rc = 0; | |
2113 | break; | |
2114 | } | |
2115 | if (tmp != -ENODEV) { | |
2116 | rc = tmp; | |
2117 | } | |
2118 | } | |
2119 | ||
2120 | return rc; | |
2121 | } | |
f5e6fed8 AK |
2122 | |
2123 | MemoryRegion *pci_address_space(PCIDevice *dev) | |
2124 | { | |
2125 | return dev->bus->address_space_mem; | |
2126 | } | |
e11d6439 RH |
2127 | |
2128 | MemoryRegion *pci_address_space_io(PCIDevice *dev) | |
2129 | { | |
2130 | return dev->bus->address_space_io; | |
2131 | } | |
40021f08 | 2132 | |
39bffca2 AL |
2133 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2134 | { | |
2135 | DeviceClass *k = DEVICE_CLASS(klass); | |
2136 | k->init = pci_qdev_init; | |
2137 | k->unplug = pci_unplug_device; | |
2138 | k->exit = pci_unregister_device; | |
0d936928 | 2139 | k->bus_type = TYPE_PCI_BUS; |
bce54474 | 2140 | k->props = pci_props; |
39bffca2 AL |
2141 | } |
2142 | ||
5fa45de5 DG |
2143 | void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque) |
2144 | { | |
2145 | bus->dma_context_fn = fn; | |
2146 | bus->dma_context_opaque = opaque; | |
2147 | } | |
2148 | ||
40021f08 AL |
2149 | static TypeInfo pci_device_type_info = { |
2150 | .name = TYPE_PCI_DEVICE, | |
2151 | .parent = TYPE_DEVICE, | |
2152 | .instance_size = sizeof(PCIDevice), | |
2153 | .abstract = true, | |
2154 | .class_size = sizeof(PCIDeviceClass), | |
39bffca2 | 2155 | .class_init = pci_device_class_init, |
40021f08 AL |
2156 | }; |
2157 | ||
83f7d43a | 2158 | static void pci_register_types(void) |
40021f08 | 2159 | { |
0d936928 | 2160 | type_register_static(&pci_bus_info); |
40021f08 AL |
2161 | type_register_static(&pci_device_type_info); |
2162 | } | |
2163 | ||
83f7d43a | 2164 | type_init(pci_register_types) |