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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
a9f49946 | 26 | #include "pci_host.h" |
376253ec | 27 | #include "monitor.h" |
87ecb68b | 28 | #include "net.h" |
880345c4 | 29 | #include "sysemu.h" |
69b91039 FB |
30 | |
31 | //#define DEBUG_PCI | |
d8d2e079 | 32 | #ifdef DEBUG_PCI |
2e49d64a | 33 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
34 | #else |
35 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
36 | #endif | |
69b91039 | 37 | |
30468f78 | 38 | struct PCIBus { |
02e2da45 | 39 | BusState qbus; |
30468f78 | 40 | int devfn_min; |
502a5395 | 41 | pci_set_irq_fn set_irq; |
d2b59317 | 42 | pci_map_irq_fn map_irq; |
ee995ffb | 43 | pci_hotplug_fn hotplug; |
30468f78 | 44 | uint32_t config_reg; /* XXX: suppress */ |
5d4e84c8 | 45 | void *irq_opaque; |
30468f78 | 46 | PCIDevice *devices[256]; |
80b3ada7 | 47 | PCIDevice *parent_dev; |
e822a52a IY |
48 | |
49 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
50 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
51 | ||
d2b59317 PB |
52 | /* The bus IRQ state is the logical OR of the connected devices. |
53 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 54 | int nirq; |
10c4c98a GH |
55 | int *irq_count; |
56 | }; | |
57 | ||
58 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
59 | ||
60 | static struct BusInfo pci_bus_info = { | |
61 | .name = "PCI", | |
62 | .size = sizeof(PCIBus), | |
63 | .print_dev = pcibus_dev_print, | |
ee6847d1 | 64 | .props = (Property[]) { |
54586bd1 GH |
65 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
66 | DEFINE_PROP_END_OF_LIST() | |
ee6847d1 | 67 | } |
30468f78 | 68 | }; |
69b91039 | 69 | |
1941d19c | 70 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 71 | static void pci_set_irq(void *opaque, int irq_num, int level); |
1941d19c | 72 | |
c227f099 | 73 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
74 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
75 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
76 | |
77 | struct PCIHostBus { | |
78 | int domain; | |
79 | struct PCIBus *bus; | |
80 | QLIST_ENTRY(PCIHostBus) next; | |
81 | }; | |
82 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 83 | |
2d1e9f96 JQ |
84 | static const VMStateDescription vmstate_pcibus = { |
85 | .name = "PCIBUS", | |
86 | .version_id = 1, | |
87 | .minimum_version_id = 1, | |
88 | .minimum_version_id_old = 1, | |
89 | .fields = (VMStateField []) { | |
90 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 91 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 92 | VMSTATE_END_OF_LIST() |
52fc1d83 | 93 | } |
2d1e9f96 | 94 | }; |
52fc1d83 | 95 | |
b3b11697 | 96 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 97 | { |
b3b11697 IY |
98 | uint8_t type; |
99 | ||
100 | if (reg != PCI_ROM_SLOT) | |
101 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
102 | ||
103 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
104 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
105 | } |
106 | ||
107 | static void pci_device_reset(PCIDevice *dev) | |
108 | { | |
c0b1905b MT |
109 | int r; |
110 | ||
5330de09 | 111 | memset(dev->irq_state, 0, sizeof dev->irq_state); |
c0b1905b MT |
112 | dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
113 | PCI_COMMAND_MASTER); | |
114 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; | |
115 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
116 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
117 | if (!dev->io_regions[r].size) { | |
118 | continue; | |
119 | } | |
b3b11697 | 120 | pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
c0b1905b MT |
121 | } |
122 | pci_update_mappings(dev); | |
5330de09 MT |
123 | } |
124 | ||
6eaa6847 GN |
125 | static void pci_bus_reset(void *opaque) |
126 | { | |
a60380a5 | 127 | PCIBus *bus = opaque; |
6eaa6847 GN |
128 | int i; |
129 | ||
130 | for (i = 0; i < bus->nirq; i++) { | |
131 | bus->irq_count[i] = 0; | |
132 | } | |
5330de09 MT |
133 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
134 | if (bus->devices[i]) { | |
135 | pci_device_reset(bus->devices[i]); | |
136 | } | |
6eaa6847 GN |
137 | } |
138 | } | |
139 | ||
e822a52a IY |
140 | static void pci_host_bus_register(int domain, PCIBus *bus) |
141 | { | |
142 | struct PCIHostBus *host; | |
143 | host = qemu_mallocz(sizeof(*host)); | |
144 | host->domain = domain; | |
145 | host->bus = bus; | |
146 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
147 | } | |
148 | ||
149 | PCIBus *pci_find_host_bus(int domain) | |
150 | { | |
151 | struct PCIHostBus *host; | |
152 | ||
153 | QLIST_FOREACH(host, &host_buses, next) { | |
154 | if (host->domain == domain) { | |
155 | return host->bus; | |
156 | } | |
157 | } | |
158 | ||
159 | return NULL; | |
160 | } | |
161 | ||
21eea4b3 GH |
162 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
163 | const char *name, int devfn_min) | |
30468f78 | 164 | { |
52fc1d83 AZ |
165 | static int nbus = 0; |
166 | ||
21eea4b3 | 167 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
502a5395 | 168 | bus->devfn_min = devfn_min; |
e822a52a IY |
169 | |
170 | /* host bridge */ | |
171 | QLIST_INIT(&bus->child); | |
172 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
173 | ||
2d1e9f96 | 174 | vmstate_register(nbus++, &vmstate_pcibus, bus); |
a08d4367 | 175 | qemu_register_reset(pci_bus_reset, bus); |
21eea4b3 GH |
176 | } |
177 | ||
178 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) | |
179 | { | |
180 | PCIBus *bus; | |
181 | ||
182 | bus = qemu_mallocz(sizeof(*bus)); | |
183 | bus->qbus.qdev_allocated = 1; | |
184 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
185 | return bus; | |
186 | } | |
187 | ||
188 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
189 | void *irq_opaque, int nirq) | |
190 | { | |
191 | bus->set_irq = set_irq; | |
192 | bus->map_irq = map_irq; | |
193 | bus->irq_opaque = irq_opaque; | |
194 | bus->nirq = nirq; | |
195 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
196 | } | |
197 | ||
ee995ffb GH |
198 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug) |
199 | { | |
200 | bus->qbus.allow_hotplug = 1; | |
201 | bus->hotplug = hotplug; | |
202 | } | |
203 | ||
21eea4b3 GH |
204 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
205 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
206 | void *irq_opaque, int devfn_min, int nirq) | |
207 | { | |
208 | PCIBus *bus; | |
209 | ||
210 | bus = pci_bus_new(parent, name, devfn_min); | |
211 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
212 | return bus; |
213 | } | |
69b91039 | 214 | |
e822a52a IY |
215 | static void pci_register_secondary_bus(PCIBus *parent, |
216 | PCIBus *bus, | |
03587182 GH |
217 | PCIDevice *dev, |
218 | pci_map_irq_fn map_irq, | |
219 | const char *name) | |
80b3ada7 | 220 | { |
03587182 | 221 | qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
80b3ada7 PB |
222 | bus->map_irq = map_irq; |
223 | bus->parent_dev = dev; | |
e822a52a IY |
224 | |
225 | QLIST_INIT(&bus->child); | |
226 | QLIST_INSERT_HEAD(&parent->child, bus, sibling); | |
227 | } | |
228 | ||
229 | static void pci_unregister_secondary_bus(PCIBus *bus) | |
230 | { | |
231 | assert(QLIST_EMPTY(&bus->child)); | |
232 | QLIST_REMOVE(bus, sibling); | |
80b3ada7 PB |
233 | } |
234 | ||
502a5395 PB |
235 | int pci_bus_num(PCIBus *s) |
236 | { | |
e94ff650 IY |
237 | if (!s->parent_dev) |
238 | return 0; /* pci host bridge */ | |
239 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
240 | } |
241 | ||
e822a52a IY |
242 | static uint8_t pci_sub_bus(PCIBus *s) |
243 | { | |
244 | if (!s->parent_dev) | |
245 | return 255; /* pci host bridge */ | |
246 | return s->parent_dev->config[PCI_SUBORDINATE_BUS]; | |
247 | } | |
248 | ||
73534f2f | 249 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 250 | { |
73534f2f | 251 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 252 | uint8_t *config; |
52fc1d83 AZ |
253 | int i; |
254 | ||
a9f49946 IY |
255 | assert(size == pci_config_size(s)); |
256 | config = qemu_malloc(size); | |
257 | ||
258 | qemu_get_buffer(f, config, size); | |
259 | for (i = 0; i < size; ++i) { | |
260 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) { | |
261 | qemu_free(config); | |
bd4b65ee | 262 | return -EINVAL; |
a9f49946 IY |
263 | } |
264 | } | |
265 | memcpy(s->config, config, size); | |
bd4b65ee | 266 | |
1941d19c | 267 | pci_update_mappings(s); |
52fc1d83 | 268 | |
a9f49946 | 269 | qemu_free(config); |
30ca2aab FB |
270 | return 0; |
271 | } | |
272 | ||
73534f2f | 273 | /* just put buffer */ |
84e2e3eb | 274 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f JQ |
275 | { |
276 | const uint8_t *v = pv; | |
a9f49946 | 277 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
73534f2f JQ |
278 | qemu_put_buffer(f, v, size); |
279 | } | |
280 | ||
281 | static VMStateInfo vmstate_info_pci_config = { | |
282 | .name = "pci config", | |
283 | .get = get_pci_config_device, | |
284 | .put = put_pci_config_device, | |
285 | }; | |
286 | ||
287 | const VMStateDescription vmstate_pci_device = { | |
288 | .name = "PCIDevice", | |
289 | .version_id = 2, | |
290 | .minimum_version_id = 1, | |
291 | .minimum_version_id_old = 1, | |
292 | .fields = (VMStateField []) { | |
293 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
294 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
295 | vmstate_info_pci_config, | |
296 | PCI_CONFIG_SPACE_SIZE), | |
297 | VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2), | |
298 | VMSTATE_END_OF_LIST() | |
299 | } | |
300 | }; | |
301 | ||
302 | const VMStateDescription vmstate_pcie_device = { | |
303 | .name = "PCIDevice", | |
304 | .version_id = 2, | |
305 | .minimum_version_id = 1, | |
306 | .minimum_version_id_old = 1, | |
307 | .fields = (VMStateField []) { | |
308 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
309 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
310 | vmstate_info_pci_config, | |
311 | PCIE_CONFIG_SPACE_SIZE), | |
e369cad7 | 312 | VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2), |
73534f2f JQ |
313 | VMSTATE_END_OF_LIST() |
314 | } | |
315 | }; | |
316 | ||
a9f49946 IY |
317 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
318 | { | |
319 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
320 | } | |
321 | ||
73534f2f JQ |
322 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
323 | { | |
a9f49946 | 324 | vmstate_save_state(f, pci_get_vmstate(s), s); |
73534f2f JQ |
325 | } |
326 | ||
327 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
328 | { | |
a9f49946 | 329 | return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); |
73534f2f JQ |
330 | } |
331 | ||
d350d97d AL |
332 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
333 | { | |
334 | uint16_t *id; | |
335 | ||
336 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
337 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
338 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
339 | return 0; | |
340 | } | |
341 | ||
880345c4 AL |
342 | /* |
343 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
344 | */ | |
345 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
346 | { | |
347 | const char *p; | |
348 | char *e; | |
349 | unsigned long val; | |
350 | unsigned long dom = 0, bus = 0; | |
351 | unsigned slot = 0; | |
352 | ||
353 | p = addr; | |
354 | val = strtoul(p, &e, 16); | |
355 | if (e == p) | |
356 | return -1; | |
357 | if (*e == ':') { | |
358 | bus = val; | |
359 | p = e + 1; | |
360 | val = strtoul(p, &e, 16); | |
361 | if (e == p) | |
362 | return -1; | |
363 | if (*e == ':') { | |
364 | dom = bus; | |
365 | bus = val; | |
366 | p = e + 1; | |
367 | val = strtoul(p, &e, 16); | |
368 | if (e == p) | |
369 | return -1; | |
370 | } | |
371 | } | |
372 | ||
373 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
374 | return -1; | |
375 | ||
376 | slot = val; | |
377 | ||
378 | if (*e) | |
379 | return -1; | |
380 | ||
381 | /* Note: QEMU doesn't implement domains other than 0 */ | |
e822a52a | 382 | if (!pci_find_bus(pci_find_host_bus(dom), bus)) |
880345c4 AL |
383 | return -1; |
384 | ||
385 | *domp = dom; | |
386 | *busp = bus; | |
387 | *slotp = slot; | |
388 | return 0; | |
389 | } | |
390 | ||
e9283f8b JK |
391 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
392 | unsigned *slotp) | |
880345c4 | 393 | { |
e9283f8b JK |
394 | /* strip legacy tag */ |
395 | if (!strncmp(addr, "pci_addr=", 9)) { | |
396 | addr += 9; | |
397 | } | |
398 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
399 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 400 | return -1; |
e9283f8b JK |
401 | } |
402 | return 0; | |
880345c4 AL |
403 | } |
404 | ||
49bd1458 | 405 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
406 | { |
407 | int dom, bus; | |
408 | unsigned slot; | |
409 | ||
410 | if (!devaddr) { | |
411 | *devfnp = -1; | |
e822a52a | 412 | return pci_find_bus(pci_find_host_bus(0), 0); |
5607c388 MA |
413 | } |
414 | ||
415 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
416 | return NULL; | |
417 | } | |
418 | ||
419 | *devfnp = slot << 3; | |
e822a52a | 420 | return pci_find_bus(pci_find_host_bus(0), bus); |
5607c388 MA |
421 | } |
422 | ||
bd4b65ee MT |
423 | static void pci_init_cmask(PCIDevice *dev) |
424 | { | |
425 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
426 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
427 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
428 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
429 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
430 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
431 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
432 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
433 | } | |
434 | ||
b7ee1603 MT |
435 | static void pci_init_wmask(PCIDevice *dev) |
436 | { | |
437 | int i; | |
a9f49946 IY |
438 | int config_size = pci_config_size(dev); |
439 | ||
b7ee1603 MT |
440 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
441 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 IY |
442 | pci_set_word(dev->wmask + PCI_COMMAND, |
443 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
a9f49946 | 444 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
b7ee1603 MT |
445 | dev->wmask[i] = 0xff; |
446 | } | |
447 | ||
a9f49946 IY |
448 | static void pci_config_alloc(PCIDevice *pci_dev) |
449 | { | |
450 | int config_size = pci_config_size(pci_dev); | |
451 | ||
452 | pci_dev->config = qemu_mallocz(config_size); | |
453 | pci_dev->cmask = qemu_mallocz(config_size); | |
454 | pci_dev->wmask = qemu_mallocz(config_size); | |
455 | pci_dev->used = qemu_mallocz(config_size); | |
456 | } | |
457 | ||
458 | static void pci_config_free(PCIDevice *pci_dev) | |
459 | { | |
460 | qemu_free(pci_dev->config); | |
461 | qemu_free(pci_dev->cmask); | |
462 | qemu_free(pci_dev->wmask); | |
463 | qemu_free(pci_dev->used); | |
464 | } | |
465 | ||
69b91039 | 466 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
467 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
468 | const char *name, int devfn, | |
469 | PCIConfigReadFunc *config_read, | |
470 | PCIConfigWriteFunc *config_write) | |
69b91039 | 471 | { |
69b91039 | 472 | if (devfn < 0) { |
30468f78 FB |
473 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
474 | if (!bus->devices[devfn]) | |
69b91039 FB |
475 | goto found; |
476 | } | |
477 | return NULL; | |
478 | found: ; | |
07b7d053 MA |
479 | } else if (bus->devices[devfn]) { |
480 | return NULL; | |
69b91039 | 481 | } |
30468f78 | 482 | pci_dev->bus = bus; |
69b91039 FB |
483 | pci_dev->devfn = devfn; |
484 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d2b59317 | 485 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
a9f49946 | 486 | pci_config_alloc(pci_dev); |
d350d97d | 487 | pci_set_default_subsystem_id(pci_dev); |
bd4b65ee | 488 | pci_init_cmask(pci_dev); |
b7ee1603 | 489 | pci_init_wmask(pci_dev); |
0ac32c83 FB |
490 | |
491 | if (!config_read) | |
492 | config_read = pci_default_read_config; | |
493 | if (!config_write) | |
494 | config_write = pci_default_write_config; | |
69b91039 FB |
495 | pci_dev->config_read = config_read; |
496 | pci_dev->config_write = config_write; | |
30468f78 | 497 | bus->devices[devfn] = pci_dev; |
e369cad7 | 498 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 499 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
500 | return pci_dev; |
501 | } | |
502 | ||
6b1b92d3 PB |
503 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
504 | int instance_size, int devfn, | |
505 | PCIConfigReadFunc *config_read, | |
506 | PCIConfigWriteFunc *config_write) | |
507 | { | |
508 | PCIDevice *pci_dev; | |
509 | ||
510 | pci_dev = qemu_mallocz(instance_size); | |
511 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
512 | config_read, config_write); | |
513 | return pci_dev; | |
514 | } | |
c227f099 | 515 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
5851e08c AL |
516 | { |
517 | return addr + pci_mem_base; | |
518 | } | |
519 | ||
520 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
521 | { | |
522 | PCIIORegion *r; | |
523 | int i; | |
524 | ||
525 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
526 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 527 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 528 | continue; |
0392a017 | 529 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
5851e08c AL |
530 | isa_unassign_ioport(r->addr, r->size); |
531 | } else { | |
532 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
533 | r->size, | |
534 | IO_MEM_UNASSIGNED); | |
535 | } | |
536 | } | |
537 | } | |
538 | ||
a36a344d | 539 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 540 | { |
a36a344d | 541 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 542 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
543 | int ret = 0; |
544 | ||
e3936fa5 GH |
545 | if (info->exit) |
546 | ret = info->exit(pci_dev); | |
5851e08c AL |
547 | if (ret) |
548 | return ret; | |
549 | ||
550 | pci_unregister_io_regions(pci_dev); | |
551 | ||
552 | qemu_free_irqs(pci_dev->irq); | |
5851e08c | 553 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
a9f49946 | 554 | pci_config_free(pci_dev); |
5851e08c AL |
555 | return 0; |
556 | } | |
557 | ||
28c2c264 | 558 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 559 | pcibus_t size, int type, |
69b91039 FB |
560 | PCIMapIORegionFunc *map_func) |
561 | { | |
562 | PCIIORegion *r; | |
d7ce493a | 563 | uint32_t addr; |
6e355d90 | 564 | pcibus_t wmask; |
69b91039 | 565 | |
8a8696a3 | 566 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 567 | return; |
a4c20c6a AL |
568 | |
569 | if (size & (size-1)) { | |
570 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 571 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
572 | exit(1); |
573 | } | |
574 | ||
69b91039 | 575 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 576 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
577 | r->size = size; |
578 | r->type = type; | |
579 | r->map_func = map_func; | |
b7ee1603 MT |
580 | |
581 | wmask = ~(size - 1); | |
b3b11697 | 582 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 583 | if (region_num == PCI_ROM_SLOT) { |
b7ee1603 | 584 | /* ROM enable bit is writeable */ |
5330de09 | 585 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 586 | } |
b0ff8eb2 | 587 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
588 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
589 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
590 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
591 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
592 | } else { | |
593 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
594 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
595 | } | |
69b91039 FB |
596 | } |
597 | ||
0ac32c83 FB |
598 | static void pci_update_mappings(PCIDevice *d) |
599 | { | |
600 | PCIIORegion *r; | |
601 | int cmd, i; | |
6e355d90 | 602 | pcibus_t last_addr, new_addr; |
3b46e624 | 603 | |
b0ff8eb2 | 604 | cmd = pci_get_word(d->config + PCI_COMMAND); |
8a8696a3 | 605 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 FB |
606 | r = &d->io_regions[i]; |
607 | if (r->size != 0) { | |
0392a017 | 608 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
0ac32c83 | 609 | if (cmd & PCI_COMMAND_IO) { |
b3b11697 | 610 | new_addr = pci_get_long(d->config + pci_bar(d, i)); |
0ac32c83 FB |
611 | new_addr = new_addr & ~(r->size - 1); |
612 | last_addr = new_addr + r->size - 1; | |
613 | /* NOTE: we have only 64K ioports on PC */ | |
614 | if (last_addr <= new_addr || new_addr == 0 || | |
615 | last_addr >= 0x10000) { | |
182f9c8a | 616 | new_addr = PCI_BAR_UNMAPPED; |
0ac32c83 FB |
617 | } |
618 | } else { | |
182f9c8a | 619 | new_addr = PCI_BAR_UNMAPPED; |
0ac32c83 FB |
620 | } |
621 | } else { | |
622 | if (cmd & PCI_COMMAND_MEMORY) { | |
14421258 IY |
623 | if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
624 | new_addr = pci_get_quad(d->config + pci_bar(d, i)); | |
625 | } else { | |
626 | new_addr = pci_get_long(d->config + pci_bar(d, i)); | |
627 | } | |
8a8696a3 | 628 | /* the ROM slot has a specific enable bit */ |
5330de09 | 629 | if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) |
8a8696a3 | 630 | goto no_mem_map; |
0ac32c83 FB |
631 | new_addr = new_addr & ~(r->size - 1); |
632 | last_addr = new_addr + r->size - 1; | |
633 | /* NOTE: we do not support wrapping */ | |
634 | /* XXX: as we cannot support really dynamic | |
635 | mappings, we handle specific values as invalid | |
636 | mappings. */ | |
637 | if (last_addr <= new_addr || new_addr == 0 || | |
4f8589e1 IY |
638 | last_addr == PCI_BAR_UNMAPPED || |
639 | ||
640 | /* Now pcibus_t is 64bit. | |
641 | * Check if 32 bit BAR wrap around explicitly. | |
642 | * Without this, PC ide doesn't work well. | |
643 | * TODO: remove this work around. | |
644 | */ | |
14421258 IY |
645 | (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) && |
646 | last_addr >= UINT32_MAX) || | |
647 | ||
648 | /* | |
649 | * OS is allowed to set BAR beyond its addressable | |
650 | * bits. For example, 32 bit OS can set 64bit bar | |
651 | * to >4G. Check it. | |
652 | */ | |
653 | last_addr >= TARGET_PHYS_ADDR_MAX) { | |
182f9c8a | 654 | new_addr = PCI_BAR_UNMAPPED; |
0ac32c83 FB |
655 | } |
656 | } else { | |
8a8696a3 | 657 | no_mem_map: |
182f9c8a | 658 | new_addr = PCI_BAR_UNMAPPED; |
0ac32c83 FB |
659 | } |
660 | } | |
661 | /* now do the real mapping */ | |
662 | if (new_addr != r->addr) { | |
182f9c8a | 663 | if (r->addr != PCI_BAR_UNMAPPED) { |
0392a017 | 664 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
0ac32c83 FB |
665 | int class; |
666 | /* NOTE: specific hack for IDE in PC case: | |
667 | only one byte must be mapped. */ | |
5330de09 | 668 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
0ac32c83 FB |
669 | if (class == 0x0101 && r->size == 4) { |
670 | isa_unassign_ioport(r->addr + 2, 1); | |
671 | } else { | |
672 | isa_unassign_ioport(r->addr, r->size); | |
673 | } | |
674 | } else { | |
502a5395 | 675 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
5fafdf24 | 676 | r->size, |
0ac32c83 | 677 | IO_MEM_UNASSIGNED); |
f65ed4c1 | 678 | qemu_unregister_coalesced_mmio(r->addr, r->size); |
0ac32c83 FB |
679 | } |
680 | } | |
681 | r->addr = new_addr; | |
182f9c8a | 682 | if (r->addr != PCI_BAR_UNMAPPED) { |
0ac32c83 FB |
683 | r->map_func(d, i, r->addr, r->size, r->type); |
684 | } | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
5fafdf24 | 690 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 691 | uint32_t address, int len) |
69b91039 | 692 | { |
5029fe12 IY |
693 | uint32_t val = 0; |
694 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 695 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
696 | memcpy(&val, d->config + address, len); |
697 | return le32_to_cpu(val); | |
0ac32c83 FB |
698 | } |
699 | ||
b7ee1603 | 700 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 701 | { |
b7ee1603 | 702 | int i; |
a9f49946 | 703 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 704 | |
a9f49946 | 705 | for(i = 0; i < l && addr < config_size; val >>= 8, ++i, ++addr) { |
b7ee1603 MT |
706 | uint8_t wmask = d->wmask[addr]; |
707 | d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); | |
0ac32c83 | 708 | } |
260c0cd3 IY |
709 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
710 | range_covers_byte(addr, l, PCI_COMMAND)) | |
0ac32c83 | 711 | pci_update_mappings(d); |
69b91039 FB |
712 | } |
713 | ||
502a5395 PB |
714 | /***********************************************************/ |
715 | /* generic PCI irq support */ | |
30468f78 | 716 | |
502a5395 | 717 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 718 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 719 | { |
a60380a5 | 720 | PCIDevice *pci_dev = opaque; |
80b3ada7 PB |
721 | PCIBus *bus; |
722 | int change; | |
3b46e624 | 723 | |
80b3ada7 PB |
724 | change = level - pci_dev->irq_state[irq_num]; |
725 | if (!change) | |
726 | return; | |
d2b59317 | 727 | |
d2b59317 | 728 | pci_dev->irq_state[irq_num] = level; |
5e966ce6 PB |
729 | for (;;) { |
730 | bus = pci_dev->bus; | |
80b3ada7 | 731 | irq_num = bus->map_irq(pci_dev, irq_num); |
5e966ce6 PB |
732 | if (bus->set_irq) |
733 | break; | |
80b3ada7 | 734 | pci_dev = bus->parent_dev; |
80b3ada7 PB |
735 | } |
736 | bus->irq_count[irq_num] += change; | |
d2b59317 | 737 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
69b91039 FB |
738 | } |
739 | ||
502a5395 PB |
740 | /***********************************************************/ |
741 | /* monitor info on PCI */ | |
0ac32c83 | 742 | |
6650ee6d PB |
743 | typedef struct { |
744 | uint16_t class; | |
745 | const char *desc; | |
746 | } pci_class_desc; | |
747 | ||
09bc878a | 748 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 749 | { |
4ca9c76f | 750 | { 0x0100, "SCSI controller"}, |
6650ee6d | 751 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
752 | { 0x0102, "Floppy controller"}, |
753 | { 0x0103, "IPI controller"}, | |
754 | { 0x0104, "RAID controller"}, | |
755 | { 0x0106, "SATA controller"}, | |
756 | { 0x0107, "SAS controller"}, | |
757 | { 0x0180, "Storage controller"}, | |
6650ee6d | 758 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
759 | { 0x0201, "Token Ring controller"}, |
760 | { 0x0202, "FDDI controller"}, | |
761 | { 0x0203, "ATM controller"}, | |
762 | { 0x0280, "Network controller"}, | |
6650ee6d | 763 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
764 | { 0x0301, "XGA controller"}, |
765 | { 0x0302, "3D controller"}, | |
766 | { 0x0380, "Display controller"}, | |
767 | { 0x0400, "Video controller"}, | |
768 | { 0x0401, "Audio controller"}, | |
769 | { 0x0402, "Phone"}, | |
770 | { 0x0480, "Multimedia controller"}, | |
771 | { 0x0500, "RAM controller"}, | |
772 | { 0x0501, "Flash controller"}, | |
773 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
774 | { 0x0600, "Host bridge"}, |
775 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
776 | { 0x0602, "EISA bridge"}, |
777 | { 0x0603, "MC bridge"}, | |
6650ee6d | 778 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
779 | { 0x0605, "PCMCIA bridge"}, |
780 | { 0x0606, "NUBUS bridge"}, | |
781 | { 0x0607, "CARDBUS bridge"}, | |
782 | { 0x0608, "RACEWAY bridge"}, | |
783 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
784 | { 0x0c03, "USB controller"}, |
785 | { 0, NULL} | |
786 | }; | |
787 | ||
e822a52a | 788 | static void pci_info_device(PCIBus *bus, PCIDevice *d) |
30468f78 | 789 | { |
376253ec | 790 | Monitor *mon = cur_mon; |
502a5395 PB |
791 | int i, class; |
792 | PCIIORegion *r; | |
09bc878a | 793 | const pci_class_desc *desc; |
30468f78 | 794 | |
376253ec | 795 | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", |
e94ff650 IY |
796 | pci_bus_num(d->bus), |
797 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); | |
b0ff8eb2 | 798 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
376253ec | 799 | monitor_printf(mon, " "); |
6650ee6d PB |
800 | desc = pci_class_descriptions; |
801 | while (desc->desc && class != desc->class) | |
802 | desc++; | |
803 | if (desc->desc) { | |
376253ec | 804 | monitor_printf(mon, "%s", desc->desc); |
6650ee6d | 805 | } else { |
376253ec | 806 | monitor_printf(mon, "Class %04x", class); |
72cc6cfe | 807 | } |
376253ec | 808 | monitor_printf(mon, ": PCI device %04x:%04x\n", |
b0ff8eb2 IY |
809 | pci_get_word(d->config + PCI_VENDOR_ID), |
810 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
30468f78 | 811 | |
502a5395 | 812 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
376253ec AL |
813 | monitor_printf(mon, " IRQ %d.\n", |
814 | d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 815 | } |
80b3ada7 | 816 | if (class == 0x0604) { |
376253ec | 817 | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
80b3ada7 | 818 | } |
502a5395 PB |
819 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
820 | r = &d->io_regions[i]; | |
821 | if (r->size != 0) { | |
376253ec | 822 | monitor_printf(mon, " BAR%d: ", i); |
0392a017 | 823 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
89e8b13c IY |
824 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS |
825 | " [0x%04"FMT_PCIBUS"].\n", | |
376253ec | 826 | r->addr, r->addr + r->size - 1); |
502a5395 | 827 | } else { |
14421258 IY |
828 | const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ? |
829 | "64 bit" : "32 bit"; | |
830 | const char *prefetch = | |
831 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ? | |
832 | " prefetchable" : ""; | |
833 | ||
834 | monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 835 | " [0x%08"FMT_PCIBUS"].\n", |
14421258 | 836 | type, prefetch, |
376253ec | 837 | r->addr, r->addr + r->size - 1); |
502a5395 PB |
838 | } |
839 | } | |
77d4bc34 | 840 | } |
8ad12514 | 841 | monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
80b3ada7 | 842 | if (class == 0x0604 && d->config[0x19] != 0) { |
e822a52a | 843 | pci_for_each_device(bus, d->config[0x19], pci_info_device); |
80b3ada7 | 844 | } |
384d8876 FB |
845 | } |
846 | ||
e822a52a IY |
847 | void pci_for_each_device(PCIBus *bus, int bus_num, |
848 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
384d8876 | 849 | { |
384d8876 | 850 | PCIDevice *d; |
502a5395 | 851 | int devfn; |
3b46e624 | 852 | |
e822a52a | 853 | bus = pci_find_bus(bus, bus_num); |
502a5395 PB |
854 | if (bus) { |
855 | for(devfn = 0; devfn < 256; devfn++) { | |
856 | d = bus->devices[devfn]; | |
857 | if (d) | |
e822a52a | 858 | fn(bus, d); |
502a5395 | 859 | } |
f2aa58c6 | 860 | } |
f2aa58c6 FB |
861 | } |
862 | ||
376253ec | 863 | void pci_info(Monitor *mon) |
f2aa58c6 | 864 | { |
e822a52a IY |
865 | struct PCIHostBus *host; |
866 | QLIST_FOREACH(host, &host_buses, next) { | |
867 | pci_for_each_device(host->bus, 0, pci_info_device); | |
868 | } | |
77d4bc34 | 869 | } |
a41b2ff2 | 870 | |
cb457d76 AL |
871 | static const char * const pci_nic_models[] = { |
872 | "ne2k_pci", | |
873 | "i82551", | |
874 | "i82557b", | |
875 | "i82559er", | |
876 | "rtl8139", | |
877 | "e1000", | |
878 | "pcnet", | |
879 | "virtio", | |
880 | NULL | |
881 | }; | |
882 | ||
9d07d757 PB |
883 | static const char * const pci_nic_names[] = { |
884 | "ne2k_pci", | |
885 | "i82551", | |
886 | "i82557b", | |
887 | "i82559er", | |
888 | "rtl8139", | |
889 | "e1000", | |
890 | "pcnet", | |
53c25cea | 891 | "virtio-net-pci", |
cb457d76 AL |
892 | NULL |
893 | }; | |
894 | ||
a41b2ff2 | 895 | /* Initialize a PCI NIC. */ |
33e66b86 | 896 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
897 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
898 | const char *default_devaddr) | |
a41b2ff2 | 899 | { |
5607c388 | 900 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
901 | PCIBus *bus; |
902 | int devfn; | |
5607c388 | 903 | PCIDevice *pci_dev; |
9d07d757 | 904 | DeviceState *dev; |
cb457d76 AL |
905 | int i; |
906 | ||
07caea31 MA |
907 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
908 | if (i < 0) | |
909 | return NULL; | |
910 | ||
911 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
912 | if (!bus) { | |
913 | qemu_error("Invalid PCI device address %s for device %s\n", | |
914 | devaddr, pci_nic_names[i]); | |
915 | return NULL; | |
916 | } | |
917 | ||
499cf102 | 918 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 919 | dev = &pci_dev->qdev; |
dea7b3b9 MM |
920 | if (nd->name) |
921 | dev->id = qemu_strdup(nd->name); | |
1cc33683 | 922 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
923 | if (qdev_init(dev) < 0) |
924 | return NULL; | |
9ee05825 | 925 | return pci_dev; |
a41b2ff2 PB |
926 | } |
927 | ||
07caea31 MA |
928 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
929 | const char *default_devaddr) | |
930 | { | |
931 | PCIDevice *res; | |
932 | ||
933 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
934 | exit(0); | |
935 | ||
936 | res = pci_nic_init(nd, default_model, default_devaddr); | |
937 | if (!res) | |
938 | exit(1); | |
939 | return res; | |
940 | } | |
941 | ||
80b3ada7 PB |
942 | typedef struct { |
943 | PCIDevice dev; | |
03587182 GH |
944 | PCIBus bus; |
945 | uint32_t vid; | |
946 | uint32_t did; | |
80b3ada7 PB |
947 | } PCIBridge; |
948 | ||
9596ebb7 | 949 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
950 | uint32_t address, uint32_t val, int len) |
951 | { | |
80b3ada7 PB |
952 | pci_default_write_config(d, address, val, len); |
953 | } | |
954 | ||
e822a52a | 955 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 956 | { |
e822a52a | 957 | PCIBus *sec; |
3ae80618 | 958 | |
e822a52a IY |
959 | if (!bus) |
960 | return NULL; | |
3ae80618 | 961 | |
e822a52a IY |
962 | if (pci_bus_num(bus) == bus_num) { |
963 | return bus; | |
964 | } | |
965 | ||
966 | /* try child bus */ | |
967 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
968 | if (pci_bus_num(sec) <= bus_num && bus_num <= pci_sub_bus(sec)) { | |
969 | return pci_find_bus(sec, bus_num); | |
970 | } | |
971 | } | |
972 | ||
973 | return NULL; | |
3ae80618 AL |
974 | } |
975 | ||
e822a52a | 976 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
3ae80618 | 977 | { |
e822a52a | 978 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
979 | |
980 | if (!bus) | |
981 | return NULL; | |
982 | ||
983 | return bus->devices[PCI_DEVFN(slot, function)]; | |
984 | } | |
985 | ||
03587182 | 986 | static int pci_bridge_initfn(PCIDevice *dev) |
80b3ada7 | 987 | { |
03587182 | 988 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
480b9f24 | 989 | |
03587182 GH |
990 | pci_config_set_vendor_id(s->dev.config, s->vid); |
991 | pci_config_set_device_id(s->dev.config, s->did); | |
480b9f24 | 992 | |
74c01823 IY |
993 | /* TODO: intial value |
994 | * command register: | |
995 | * According to PCI bridge spec, after reset | |
996 | * bus master bit is off | |
997 | * memory space enable bit is off | |
998 | * According to manual (805-1251.pdf).(See abp_pbi.c for its links.) | |
999 | * the reset value should be zero unless the boot pin is tied high | |
1000 | * (which is tru) and thus it should be PCI_COMMAND_MEMORY. | |
1001 | * | |
1002 | * For now, don't touch the value. | |
1003 | * Later command register will be set to zero and apb_pci.c will | |
1004 | * override the value. | |
1005 | * Same for latency timer, and multi function bit of header type. | |
1006 | */ | |
1007 | pci_set_word(dev->config + PCI_COMMAND, | |
1008 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
1009 | ||
1010 | pci_set_word(dev->config + PCI_STATUS, | |
1011 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
1012 | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); | |
1013 | dev->config[PCI_LATENCY_TIMER] = 0x10; | |
1014 | dev->config[PCI_HEADER_TYPE] = | |
1015 | PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; | |
1016 | pci_set_word(dev->config + PCI_SEC_STATUS, | |
1017 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
03587182 GH |
1018 | return 0; |
1019 | } | |
80b3ada7 | 1020 | |
e822a52a IY |
1021 | static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1022 | { | |
1023 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); | |
1024 | PCIBus *bus = &s->bus; | |
1025 | pci_unregister_secondary_bus(bus); | |
1026 | return 0; | |
1027 | } | |
1028 | ||
03587182 GH |
1029 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
1030 | pci_map_irq_fn map_irq, const char *name) | |
1031 | { | |
1032 | PCIDevice *dev; | |
1033 | PCIBridge *s; | |
1034 | ||
499cf102 | 1035 | dev = pci_create(bus, devfn, "pci-bridge"); |
03587182 GH |
1036 | qdev_prop_set_uint32(&dev->qdev, "vendorid", vid); |
1037 | qdev_prop_set_uint32(&dev->qdev, "deviceid", did); | |
e23a1b33 | 1038 | qdev_init_nofail(&dev->qdev); |
03587182 GH |
1039 | |
1040 | s = DO_UPCAST(PCIBridge, dev, dev); | |
e822a52a | 1041 | pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
03587182 | 1042 | return &s->bus; |
80b3ada7 | 1043 | } |
6b1b92d3 | 1044 | |
81a322d4 | 1045 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1046 | { |
1047 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1048 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1049 | PCIBus *bus; |
ee995ffb | 1050 | int devfn, rc; |
6b1b92d3 | 1051 | |
a9f49946 IY |
1052 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1053 | if (info->is_express) { | |
1054 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1055 | } | |
1056 | ||
02e2da45 | 1057 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 1058 | devfn = pci_dev->devfn; |
16eaedf2 | 1059 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
0aab0d3a | 1060 | info->config_read, info->config_write); |
6b1b92d3 | 1061 | assert(pci_dev); |
ee995ffb GH |
1062 | rc = info->init(pci_dev); |
1063 | if (rc != 0) | |
1064 | return rc; | |
1065 | if (qdev->hotplugged) | |
1066 | bus->hotplug(pci_dev, 1); | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static int pci_unplug_device(DeviceState *qdev) | |
1071 | { | |
1072 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
1073 | ||
1074 | dev->bus->hotplug(dev, 0); | |
1075 | return 0; | |
6b1b92d3 PB |
1076 | } |
1077 | ||
0aab0d3a | 1078 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1079 | { |
02e2da45 | 1080 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1081 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1082 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1083 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1084 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1085 | } |
1086 | ||
0aab0d3a GH |
1087 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1088 | { | |
1089 | while (info->qdev.name) { | |
1090 | pci_qdev_register(info); | |
1091 | info++; | |
1092 | } | |
1093 | } | |
1094 | ||
499cf102 | 1095 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
6b1b92d3 PB |
1096 | { |
1097 | DeviceState *dev; | |
1098 | ||
02e2da45 | 1099 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1100 | qdev_prop_set_uint32(dev, "addr", devfn); |
71077c1c GH |
1101 | return DO_UPCAST(PCIDevice, qdev, dev); |
1102 | } | |
6b1b92d3 | 1103 | |
71077c1c GH |
1104 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1105 | { | |
499cf102 | 1106 | PCIDevice *dev = pci_create(bus, devfn, name); |
e23a1b33 | 1107 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1108 | return dev; |
6b1b92d3 | 1109 | } |
6f4cbd39 MT |
1110 | |
1111 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
1112 | { | |
a9f49946 | 1113 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1114 | int offset = PCI_CONFIG_HEADER_SIZE; |
1115 | int i; | |
a9f49946 | 1116 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1117 | if (pdev->used[i]) |
1118 | offset = i + 1; | |
1119 | else if (i - offset + 1 == size) | |
1120 | return offset; | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1125 | uint8_t *prev_p) | |
1126 | { | |
1127 | uint8_t next, prev; | |
1128 | ||
1129 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1130 | return 0; | |
1131 | ||
1132 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1133 | prev = next + PCI_CAP_LIST_NEXT) | |
1134 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1135 | break; | |
1136 | ||
1137 | if (prev_p) | |
1138 | *prev_p = prev; | |
1139 | return next; | |
1140 | } | |
1141 | ||
1142 | /* Reserve space and add capability to the linked list in pci config space */ | |
1143 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1144 | { | |
1145 | uint8_t offset = pci_find_space(pdev, size); | |
1146 | uint8_t *config = pdev->config + offset; | |
1147 | if (!offset) | |
1148 | return -ENOSPC; | |
1149 | config[PCI_CAP_LIST_ID] = cap_id; | |
1150 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1151 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1152 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1153 | memset(pdev->used + offset, 0xFF, size); | |
1154 | /* Make capability read-only by default */ | |
1155 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1156 | /* Check capability by default */ |
1157 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1158 | return offset; |
1159 | } | |
1160 | ||
1161 | /* Unlink capability from the pci config space. */ | |
1162 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1163 | { | |
1164 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1165 | if (!offset) | |
1166 | return; | |
1167 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
1168 | /* Make capability writeable again */ | |
1169 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
1170 | /* Clear cmask as device-specific registers can't be checked */ |
1171 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1172 | memset(pdev->used + offset, 0, size); |
1173 | ||
1174 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1175 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1176 | } | |
1177 | ||
1178 | /* Reserve space for capability at a known offset (to call after load). */ | |
1179 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1180 | { | |
1181 | memset(pdev->used + offset, 0xff, size); | |
1182 | } | |
1183 | ||
1184 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1185 | { | |
1186 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1187 | } | |
10c4c98a GH |
1188 | |
1189 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1190 | { | |
1191 | PCIDevice *d = (PCIDevice *)dev; | |
1192 | const pci_class_desc *desc; | |
1193 | char ctxt[64]; | |
1194 | PCIIORegion *r; | |
1195 | int i, class; | |
1196 | ||
b0ff8eb2 | 1197 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1198 | desc = pci_class_descriptions; |
1199 | while (desc->desc && class != desc->class) | |
1200 | desc++; | |
1201 | if (desc->desc) { | |
1202 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1203 | } else { | |
1204 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1205 | } | |
1206 | ||
1207 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1208 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1209 | indent, "", ctxt, | |
e822a52a IY |
1210 | d->config[PCI_SECONDARY_BUS], |
1211 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), | |
b0ff8eb2 IY |
1212 | pci_get_word(d->config + PCI_VENDOR_ID), |
1213 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1214 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1215 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1216 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1217 | r = &d->io_regions[i]; | |
1218 | if (!r->size) | |
1219 | continue; | |
89e8b13c IY |
1220 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1221 | " [0x%"FMT_PCIBUS"]\n", | |
1222 | indent, "", | |
0392a017 | 1223 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1224 | r->addr, r->addr + r->size - 1); |
1225 | } | |
1226 | } | |
03587182 GH |
1227 | |
1228 | static PCIDeviceInfo bridge_info = { | |
1229 | .qdev.name = "pci-bridge", | |
1230 | .qdev.size = sizeof(PCIBridge), | |
1231 | .init = pci_bridge_initfn, | |
e822a52a | 1232 | .exit = pci_bridge_exitfn, |
03587182 GH |
1233 | .config_write = pci_bridge_write_config, |
1234 | .qdev.props = (Property[]) { | |
1235 | DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), | |
1236 | DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), | |
1237 | DEFINE_PROP_END_OF_LIST(), | |
1238 | } | |
1239 | }; | |
1240 | ||
1241 | static void pci_register_devices(void) | |
1242 | { | |
1243 | pci_qdev_register(&bridge_info); | |
1244 | } | |
1245 | ||
1246 | device_init(pci_register_devices) |