]>
Commit | Line | Data |
---|---|---|
69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
c2039bd0 | 29 | #include "loader.h" |
163c8a59 | 30 | #include "qemu-objects.h" |
69b91039 FB |
31 | |
32 | //#define DEBUG_PCI | |
d8d2e079 | 33 | #ifdef DEBUG_PCI |
2e49d64a | 34 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
35 | #else |
36 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
37 | #endif | |
69b91039 | 38 | |
30468f78 | 39 | struct PCIBus { |
02e2da45 | 40 | BusState qbus; |
30468f78 | 41 | int devfn_min; |
502a5395 | 42 | pci_set_irq_fn set_irq; |
d2b59317 | 43 | pci_map_irq_fn map_irq; |
ee995ffb | 44 | pci_hotplug_fn hotplug; |
87c30546 | 45 | DeviceState *hotplug_qdev; |
5d4e84c8 | 46 | void *irq_opaque; |
30468f78 | 47 | PCIDevice *devices[256]; |
80b3ada7 | 48 | PCIDevice *parent_dev; |
2e01c8cf | 49 | target_phys_addr_t mem_base; |
e822a52a IY |
50 | |
51 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
52 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
53 | ||
d2b59317 PB |
54 | /* The bus IRQ state is the logical OR of the connected devices. |
55 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 56 | int nirq; |
10c4c98a GH |
57 | int *irq_count; |
58 | }; | |
59 | ||
60 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
4f43c1ff | 61 | static char *pcibus_get_dev_path(DeviceState *dev); |
10c4c98a GH |
62 | |
63 | static struct BusInfo pci_bus_info = { | |
64 | .name = "PCI", | |
65 | .size = sizeof(PCIBus), | |
66 | .print_dev = pcibus_dev_print, | |
4f43c1ff | 67 | .get_dev_path = pcibus_get_dev_path, |
ee6847d1 | 68 | .props = (Property[]) { |
54586bd1 | 69 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
8c52c8f3 | 70 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), |
88169ddf | 71 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
49823868 IY |
72 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, |
73 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
54586bd1 | 74 | DEFINE_PROP_END_OF_LIST() |
ee6847d1 | 75 | } |
30468f78 | 76 | }; |
69b91039 | 77 | |
1941d19c | 78 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 79 | static void pci_set_irq(void *opaque, int irq_num, int level); |
8c52c8f3 | 80 | static int pci_add_option_rom(PCIDevice *pdev); |
230741dc | 81 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 82 | |
d350d97d AL |
83 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
84 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
85 | |
86 | struct PCIHostBus { | |
87 | int domain; | |
88 | struct PCIBus *bus; | |
89 | QLIST_ENTRY(PCIHostBus) next; | |
90 | }; | |
91 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 92 | |
2d1e9f96 JQ |
93 | static const VMStateDescription vmstate_pcibus = { |
94 | .name = "PCIBUS", | |
95 | .version_id = 1, | |
96 | .minimum_version_id = 1, | |
97 | .minimum_version_id_old = 1, | |
98 | .fields = (VMStateField []) { | |
99 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 100 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 101 | VMSTATE_END_OF_LIST() |
52fc1d83 | 102 | } |
2d1e9f96 | 103 | }; |
52fc1d83 | 104 | |
b3b11697 | 105 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 106 | { |
b3b11697 IY |
107 | uint8_t type; |
108 | ||
109 | if (reg != PCI_ROM_SLOT) | |
110 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
111 | ||
112 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
113 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
114 | } |
115 | ||
d036bb21 MT |
116 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
117 | { | |
118 | return (d->irq_state >> irq_num) & 0x1; | |
119 | } | |
120 | ||
121 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
122 | { | |
123 | d->irq_state &= ~(0x1 << irq_num); | |
124 | d->irq_state |= level << irq_num; | |
125 | } | |
126 | ||
127 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
128 | { | |
129 | PCIBus *bus; | |
130 | for (;;) { | |
131 | bus = pci_dev->bus; | |
132 | irq_num = bus->map_irq(pci_dev, irq_num); | |
133 | if (bus->set_irq) | |
134 | break; | |
135 | pci_dev = bus->parent_dev; | |
136 | } | |
137 | bus->irq_count[irq_num] += change; | |
138 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
139 | } | |
140 | ||
f9bf77dd MT |
141 | /* Update interrupt status bit in config space on interrupt |
142 | * state change. */ | |
143 | static void pci_update_irq_status(PCIDevice *dev) | |
144 | { | |
145 | if (dev->irq_state) { | |
146 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
147 | } else { | |
148 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
149 | } | |
150 | } | |
151 | ||
5330de09 MT |
152 | static void pci_device_reset(PCIDevice *dev) |
153 | { | |
c0b1905b MT |
154 | int r; |
155 | ||
d036bb21 | 156 | dev->irq_state = 0; |
f9bf77dd | 157 | pci_update_irq_status(dev); |
c0b1905b MT |
158 | dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
159 | PCI_COMMAND_MASTER); | |
160 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; | |
161 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
162 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
163 | if (!dev->io_regions[r].size) { | |
164 | continue; | |
165 | } | |
b3b11697 | 166 | pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
c0b1905b MT |
167 | } |
168 | pci_update_mappings(dev); | |
5330de09 MT |
169 | } |
170 | ||
6eaa6847 GN |
171 | static void pci_bus_reset(void *opaque) |
172 | { | |
a60380a5 | 173 | PCIBus *bus = opaque; |
6eaa6847 GN |
174 | int i; |
175 | ||
176 | for (i = 0; i < bus->nirq; i++) { | |
177 | bus->irq_count[i] = 0; | |
178 | } | |
5330de09 MT |
179 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
180 | if (bus->devices[i]) { | |
181 | pci_device_reset(bus->devices[i]); | |
182 | } | |
6eaa6847 GN |
183 | } |
184 | } | |
185 | ||
e822a52a IY |
186 | static void pci_host_bus_register(int domain, PCIBus *bus) |
187 | { | |
188 | struct PCIHostBus *host; | |
189 | host = qemu_mallocz(sizeof(*host)); | |
190 | host->domain = domain; | |
191 | host->bus = bus; | |
192 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
193 | } | |
194 | ||
c469e1dd | 195 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
196 | { |
197 | struct PCIHostBus *host; | |
198 | ||
199 | QLIST_FOREACH(host, &host_buses, next) { | |
200 | if (host->domain == domain) { | |
201 | return host->bus; | |
202 | } | |
203 | } | |
204 | ||
205 | return NULL; | |
206 | } | |
207 | ||
e075e788 IY |
208 | int pci_find_domain(const PCIBus *bus) |
209 | { | |
210 | PCIDevice *d; | |
211 | struct PCIHostBus *host; | |
212 | ||
213 | /* obtain root bus */ | |
214 | while ((d = bus->parent_dev) != NULL) { | |
215 | bus = d->bus; | |
216 | } | |
217 | ||
218 | QLIST_FOREACH(host, &host_buses, next) { | |
219 | if (host->bus == bus) { | |
220 | return host->domain; | |
221 | } | |
222 | } | |
223 | ||
224 | abort(); /* should not be reached */ | |
225 | return -1; | |
226 | } | |
227 | ||
21eea4b3 GH |
228 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
229 | const char *name, int devfn_min) | |
30468f78 | 230 | { |
21eea4b3 | 231 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
6fa84913 | 232 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 233 | bus->devfn_min = devfn_min; |
e822a52a IY |
234 | |
235 | /* host bridge */ | |
236 | QLIST_INIT(&bus->child); | |
237 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
238 | ||
0be71e32 | 239 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
a08d4367 | 240 | qemu_register_reset(pci_bus_reset, bus); |
21eea4b3 GH |
241 | } |
242 | ||
243 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) | |
244 | { | |
245 | PCIBus *bus; | |
246 | ||
247 | bus = qemu_mallocz(sizeof(*bus)); | |
248 | bus->qbus.qdev_allocated = 1; | |
249 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
250 | return bus; | |
251 | } | |
252 | ||
253 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
254 | void *irq_opaque, int nirq) | |
255 | { | |
256 | bus->set_irq = set_irq; | |
257 | bus->map_irq = map_irq; | |
258 | bus->irq_opaque = irq_opaque; | |
259 | bus->nirq = nirq; | |
260 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
261 | } | |
262 | ||
87c30546 | 263 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
264 | { |
265 | bus->qbus.allow_hotplug = 1; | |
266 | bus->hotplug = hotplug; | |
87c30546 | 267 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
268 | } |
269 | ||
2e01c8cf BS |
270 | void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base) |
271 | { | |
272 | bus->mem_base = base; | |
273 | } | |
274 | ||
21eea4b3 GH |
275 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
276 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
277 | void *irq_opaque, int devfn_min, int nirq) | |
278 | { | |
279 | PCIBus *bus; | |
280 | ||
281 | bus = pci_bus_new(parent, name, devfn_min); | |
282 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
283 | return bus; |
284 | } | |
69b91039 | 285 | |
e822a52a IY |
286 | static void pci_register_secondary_bus(PCIBus *parent, |
287 | PCIBus *bus, | |
03587182 GH |
288 | PCIDevice *dev, |
289 | pci_map_irq_fn map_irq, | |
290 | const char *name) | |
80b3ada7 | 291 | { |
03587182 | 292 | qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
80b3ada7 PB |
293 | bus->map_irq = map_irq; |
294 | bus->parent_dev = dev; | |
e822a52a IY |
295 | |
296 | QLIST_INIT(&bus->child); | |
297 | QLIST_INSERT_HEAD(&parent->child, bus, sibling); | |
298 | } | |
299 | ||
300 | static void pci_unregister_secondary_bus(PCIBus *bus) | |
301 | { | |
302 | assert(QLIST_EMPTY(&bus->child)); | |
303 | QLIST_REMOVE(bus, sibling); | |
80b3ada7 PB |
304 | } |
305 | ||
502a5395 PB |
306 | int pci_bus_num(PCIBus *s) |
307 | { | |
e94ff650 IY |
308 | if (!s->parent_dev) |
309 | return 0; /* pci host bridge */ | |
310 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
311 | } |
312 | ||
73534f2f | 313 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 314 | { |
73534f2f | 315 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 316 | uint8_t *config; |
52fc1d83 AZ |
317 | int i; |
318 | ||
a9f49946 IY |
319 | assert(size == pci_config_size(s)); |
320 | config = qemu_malloc(size); | |
321 | ||
322 | qemu_get_buffer(f, config, size); | |
323 | for (i = 0; i < size; ++i) { | |
324 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) { | |
325 | qemu_free(config); | |
bd4b65ee | 326 | return -EINVAL; |
a9f49946 IY |
327 | } |
328 | } | |
329 | memcpy(s->config, config, size); | |
bd4b65ee | 330 | |
1941d19c | 331 | pci_update_mappings(s); |
52fc1d83 | 332 | |
a9f49946 | 333 | qemu_free(config); |
30ca2aab FB |
334 | return 0; |
335 | } | |
336 | ||
73534f2f | 337 | /* just put buffer */ |
84e2e3eb | 338 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 339 | { |
dbe73d7f | 340 | const uint8_t **v = pv; |
a9f49946 | 341 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 342 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
343 | } |
344 | ||
345 | static VMStateInfo vmstate_info_pci_config = { | |
346 | .name = "pci config", | |
347 | .get = get_pci_config_device, | |
348 | .put = put_pci_config_device, | |
349 | }; | |
350 | ||
d036bb21 MT |
351 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
352 | { | |
c3f8f611 | 353 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
354 | uint32_t irq_state[PCI_NUM_PINS]; |
355 | int i; | |
356 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
357 | irq_state[i] = qemu_get_be32(f); | |
358 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
359 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
360 | irq_state[i]); | |
361 | return -EINVAL; | |
362 | } | |
363 | } | |
364 | ||
365 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
366 | pci_set_irq_state(s, i, irq_state[i]); | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
373 | { | |
374 | int i; | |
c3f8f611 | 375 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
376 | |
377 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
378 | qemu_put_be32(f, pci_irq_state(s, i)); | |
379 | } | |
380 | } | |
381 | ||
382 | static VMStateInfo vmstate_info_pci_irq_state = { | |
383 | .name = "pci irq state", | |
384 | .get = get_pci_irq_state, | |
385 | .put = put_pci_irq_state, | |
386 | }; | |
387 | ||
73534f2f JQ |
388 | const VMStateDescription vmstate_pci_device = { |
389 | .name = "PCIDevice", | |
390 | .version_id = 2, | |
391 | .minimum_version_id = 1, | |
392 | .minimum_version_id_old = 1, | |
393 | .fields = (VMStateField []) { | |
394 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
395 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
396 | vmstate_info_pci_config, | |
397 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
398 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
399 | vmstate_info_pci_irq_state, | |
400 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
401 | VMSTATE_END_OF_LIST() |
402 | } | |
403 | }; | |
404 | ||
405 | const VMStateDescription vmstate_pcie_device = { | |
406 | .name = "PCIDevice", | |
407 | .version_id = 2, | |
408 | .minimum_version_id = 1, | |
409 | .minimum_version_id_old = 1, | |
410 | .fields = (VMStateField []) { | |
411 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
412 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
413 | vmstate_info_pci_config, | |
414 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
415 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
416 | vmstate_info_pci_irq_state, | |
417 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
418 | VMSTATE_END_OF_LIST() |
419 | } | |
420 | }; | |
421 | ||
a9f49946 IY |
422 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
423 | { | |
424 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
425 | } | |
426 | ||
73534f2f JQ |
427 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
428 | { | |
f9bf77dd MT |
429 | /* Clear interrupt status bit: it is implicit |
430 | * in irq_state which we are saving. | |
431 | * This makes us compatible with old devices | |
432 | * which never set or clear this bit. */ | |
433 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 434 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
435 | /* Restore the interrupt status bit. */ |
436 | pci_update_irq_status(s); | |
73534f2f JQ |
437 | } |
438 | ||
439 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
440 | { | |
f9bf77dd MT |
441 | int ret; |
442 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
443 | /* Restore the interrupt status bit. */ | |
444 | pci_update_irq_status(s); | |
445 | return ret; | |
73534f2f JQ |
446 | } |
447 | ||
5e434f4e | 448 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 449 | { |
5e434f4e IY |
450 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
451 | pci_default_sub_vendor_id); | |
452 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
453 | pci_default_sub_device_id); | |
d350d97d AL |
454 | } |
455 | ||
880345c4 AL |
456 | /* |
457 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
458 | */ | |
459 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
460 | { | |
461 | const char *p; | |
462 | char *e; | |
463 | unsigned long val; | |
464 | unsigned long dom = 0, bus = 0; | |
465 | unsigned slot = 0; | |
466 | ||
467 | p = addr; | |
468 | val = strtoul(p, &e, 16); | |
469 | if (e == p) | |
470 | return -1; | |
471 | if (*e == ':') { | |
472 | bus = val; | |
473 | p = e + 1; | |
474 | val = strtoul(p, &e, 16); | |
475 | if (e == p) | |
476 | return -1; | |
477 | if (*e == ':') { | |
478 | dom = bus; | |
479 | bus = val; | |
480 | p = e + 1; | |
481 | val = strtoul(p, &e, 16); | |
482 | if (e == p) | |
483 | return -1; | |
484 | } | |
485 | } | |
486 | ||
487 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
488 | return -1; | |
489 | ||
490 | slot = val; | |
491 | ||
492 | if (*e) | |
493 | return -1; | |
494 | ||
495 | /* Note: QEMU doesn't implement domains other than 0 */ | |
c469e1dd | 496 | if (!pci_find_bus(pci_find_root_bus(dom), bus)) |
880345c4 AL |
497 | return -1; |
498 | ||
499 | *domp = dom; | |
500 | *busp = bus; | |
501 | *slotp = slot; | |
502 | return 0; | |
503 | } | |
504 | ||
e9283f8b JK |
505 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
506 | unsigned *slotp) | |
880345c4 | 507 | { |
e9283f8b JK |
508 | /* strip legacy tag */ |
509 | if (!strncmp(addr, "pci_addr=", 9)) { | |
510 | addr += 9; | |
511 | } | |
512 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
513 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 514 | return -1; |
e9283f8b JK |
515 | } |
516 | return 0; | |
880345c4 AL |
517 | } |
518 | ||
49bd1458 | 519 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
520 | { |
521 | int dom, bus; | |
522 | unsigned slot; | |
523 | ||
524 | if (!devaddr) { | |
525 | *devfnp = -1; | |
c469e1dd | 526 | return pci_find_bus(pci_find_root_bus(0), 0); |
5607c388 MA |
527 | } |
528 | ||
529 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
530 | return NULL; | |
531 | } | |
532 | ||
533 | *devfnp = slot << 3; | |
e075e788 | 534 | return pci_find_bus(pci_find_root_bus(dom), bus); |
5607c388 MA |
535 | } |
536 | ||
bd4b65ee MT |
537 | static void pci_init_cmask(PCIDevice *dev) |
538 | { | |
539 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
540 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
541 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
542 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
543 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
544 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
545 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
546 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
547 | } | |
548 | ||
b7ee1603 MT |
549 | static void pci_init_wmask(PCIDevice *dev) |
550 | { | |
a9f49946 IY |
551 | int config_size = pci_config_size(dev); |
552 | ||
b7ee1603 MT |
553 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
554 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 555 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
556 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
557 | PCI_COMMAND_INTX_DISABLE); | |
3e21ffc9 IY |
558 | |
559 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
560 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
561 | } |
562 | ||
fb231628 IY |
563 | static void pci_init_wmask_bridge(PCIDevice *d) |
564 | { | |
565 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
566 | PCI_SEC_LETENCY_TIMER */ | |
567 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
568 | ||
569 | /* base and limit */ | |
570 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
571 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
572 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
573 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
574 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
575 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
576 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
577 | PCI_PREF_RANGE_MASK & 0xffff); | |
578 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
579 | PCI_PREF_RANGE_MASK & 0xffff); | |
580 | ||
581 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
582 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
583 | ||
584 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); | |
585 | } | |
586 | ||
6eab3de1 IY |
587 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
588 | { | |
589 | uint8_t slot = PCI_SLOT(dev->devfn); | |
590 | uint8_t func; | |
591 | ||
592 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
593 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
594 | } | |
595 | ||
596 | /* | |
597 | * multifuction bit is interpreted in two ways as follows. | |
598 | * - all functions must set the bit to 1. | |
599 | * Example: Intel X53 | |
600 | * - function 0 must set the bit, but the rest function (> 0) | |
601 | * is allowed to leave the bit to 0. | |
602 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
603 | * | |
604 | * So OS (at least Linux) checks the bit of only function 0, | |
605 | * and doesn't see the bit of function > 0. | |
606 | * | |
607 | * The below check allows both interpretation. | |
608 | */ | |
609 | if (PCI_FUNC(dev->devfn)) { | |
610 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
611 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
612 | /* function 0 should set multifunction bit */ | |
613 | error_report("PCI: single function device can't be populated " | |
614 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
615 | return -1; | |
616 | } | |
617 | return 0; | |
618 | } | |
619 | ||
620 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
621 | return 0; | |
622 | } | |
623 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
624 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
625 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
626 | error_report("PCI: %x.0 indicates single function, " | |
627 | "but %x.%x is already populated.", | |
628 | slot, slot, func); | |
629 | return -1; | |
630 | } | |
631 | } | |
632 | return 0; | |
633 | } | |
634 | ||
a9f49946 IY |
635 | static void pci_config_alloc(PCIDevice *pci_dev) |
636 | { | |
637 | int config_size = pci_config_size(pci_dev); | |
638 | ||
639 | pci_dev->config = qemu_mallocz(config_size); | |
640 | pci_dev->cmask = qemu_mallocz(config_size); | |
641 | pci_dev->wmask = qemu_mallocz(config_size); | |
642 | pci_dev->used = qemu_mallocz(config_size); | |
643 | } | |
644 | ||
645 | static void pci_config_free(PCIDevice *pci_dev) | |
646 | { | |
647 | qemu_free(pci_dev->config); | |
648 | qemu_free(pci_dev->cmask); | |
649 | qemu_free(pci_dev->wmask); | |
650 | qemu_free(pci_dev->used); | |
651 | } | |
652 | ||
69b91039 | 653 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
654 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
655 | const char *name, int devfn, | |
656 | PCIConfigReadFunc *config_read, | |
fb231628 | 657 | PCIConfigWriteFunc *config_write, |
e327e323 | 658 | bool is_bridge) |
69b91039 | 659 | { |
69b91039 | 660 | if (devfn < 0) { |
b47b0706 | 661 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 662 | devfn += PCI_FUNC_MAX) { |
30468f78 | 663 | if (!bus->devices[devfn]) |
69b91039 FB |
664 | goto found; |
665 | } | |
3709c1b7 | 666 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 667 | return NULL; |
69b91039 | 668 | found: ; |
07b7d053 | 669 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
670 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
671 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 672 | return NULL; |
69b91039 | 673 | } |
30468f78 | 674 | pci_dev->bus = bus; |
69b91039 FB |
675 | pci_dev->devfn = devfn; |
676 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 677 | pci_dev->irq_state = 0; |
a9f49946 | 678 | pci_config_alloc(pci_dev); |
fb231628 | 679 | |
e327e323 | 680 | if (!is_bridge) { |
fb231628 IY |
681 | pci_set_default_subsystem_id(pci_dev); |
682 | } | |
bd4b65ee | 683 | pci_init_cmask(pci_dev); |
b7ee1603 | 684 | pci_init_wmask(pci_dev); |
e327e323 | 685 | if (is_bridge) { |
fb231628 IY |
686 | pci_init_wmask_bridge(pci_dev); |
687 | } | |
6eab3de1 IY |
688 | if (pci_init_multifunction(bus, pci_dev)) { |
689 | pci_config_free(pci_dev); | |
690 | return NULL; | |
691 | } | |
0ac32c83 FB |
692 | |
693 | if (!config_read) | |
694 | config_read = pci_default_read_config; | |
695 | if (!config_write) | |
696 | config_write = pci_default_write_config; | |
69b91039 FB |
697 | pci_dev->config_read = config_read; |
698 | pci_dev->config_write = config_write; | |
30468f78 | 699 | bus->devices[devfn] = pci_dev; |
e369cad7 | 700 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 701 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
702 | return pci_dev; |
703 | } | |
704 | ||
925fe64a AW |
705 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
706 | { | |
707 | qemu_free_irqs(pci_dev->irq); | |
708 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
709 | pci_config_free(pci_dev); | |
710 | } | |
711 | ||
6b1b92d3 PB |
712 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
713 | int instance_size, int devfn, | |
714 | PCIConfigReadFunc *config_read, | |
715 | PCIConfigWriteFunc *config_write) | |
716 | { | |
717 | PCIDevice *pci_dev; | |
718 | ||
719 | pci_dev = qemu_mallocz(instance_size); | |
720 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
fb231628 IY |
721 | config_read, config_write, |
722 | PCI_HEADER_TYPE_NORMAL); | |
09e3acc6 GH |
723 | if (pci_dev == NULL) { |
724 | hw_error("PCI: can't register device\n"); | |
725 | } | |
6b1b92d3 PB |
726 | return pci_dev; |
727 | } | |
2e01c8cf BS |
728 | |
729 | static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus, | |
730 | target_phys_addr_t addr) | |
5851e08c | 731 | { |
2e01c8cf | 732 | return addr + bus->mem_base; |
5851e08c AL |
733 | } |
734 | ||
735 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
736 | { | |
737 | PCIIORegion *r; | |
738 | int i; | |
739 | ||
740 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
741 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 742 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 743 | continue; |
0392a017 | 744 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
a0c7a97e | 745 | isa_unassign_ioport(r->addr, r->filtered_size); |
5851e08c | 746 | } else { |
2e01c8cf BS |
747 | cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, |
748 | r->addr), | |
749 | r->filtered_size, | |
750 | IO_MEM_UNASSIGNED); | |
5851e08c AL |
751 | } |
752 | } | |
753 | } | |
754 | ||
a36a344d | 755 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 756 | { |
a36a344d | 757 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 758 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
759 | int ret = 0; |
760 | ||
e3936fa5 GH |
761 | if (info->exit) |
762 | ret = info->exit(pci_dev); | |
5851e08c AL |
763 | if (ret) |
764 | return ret; | |
765 | ||
766 | pci_unregister_io_regions(pci_dev); | |
230741dc | 767 | pci_del_option_rom(pci_dev); |
925fe64a | 768 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
769 | return 0; |
770 | } | |
771 | ||
28c2c264 | 772 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 773 | pcibus_t size, int type, |
69b91039 FB |
774 | PCIMapIORegionFunc *map_func) |
775 | { | |
776 | PCIIORegion *r; | |
d7ce493a | 777 | uint32_t addr; |
6e355d90 | 778 | pcibus_t wmask; |
69b91039 | 779 | |
8a8696a3 | 780 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 781 | return; |
a4c20c6a AL |
782 | |
783 | if (size & (size-1)) { | |
784 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 785 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
786 | exit(1); |
787 | } | |
788 | ||
69b91039 | 789 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 790 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 | 791 | r->size = size; |
a0c7a97e | 792 | r->filtered_size = size; |
69b91039 FB |
793 | r->type = type; |
794 | r->map_func = map_func; | |
b7ee1603 MT |
795 | |
796 | wmask = ~(size - 1); | |
b3b11697 | 797 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 798 | if (region_num == PCI_ROM_SLOT) { |
b7ee1603 | 799 | /* ROM enable bit is writeable */ |
5330de09 | 800 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 801 | } |
b0ff8eb2 | 802 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
803 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
804 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
805 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
806 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
807 | } else { | |
808 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
809 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
810 | } | |
69b91039 FB |
811 | } |
812 | ||
a0c7a97e IY |
813 | static uint32_t pci_config_get_io_base(PCIDevice *d, |
814 | uint32_t base, uint32_t base_upper16) | |
815 | { | |
816 | uint32_t val; | |
817 | ||
818 | val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; | |
819 | if (d->config[base] & PCI_IO_RANGE_TYPE_32) { | |
10c9c329 | 820 | val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; |
a0c7a97e IY |
821 | } |
822 | return val; | |
823 | } | |
824 | ||
d46636b8 | 825 | static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base) |
a0c7a97e | 826 | { |
d46636b8 | 827 | return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) |
a0c7a97e IY |
828 | << 16; |
829 | } | |
830 | ||
d46636b8 | 831 | static pcibus_t pci_config_get_pref_base(PCIDevice *d, |
a0c7a97e IY |
832 | uint32_t base, uint32_t upper) |
833 | { | |
d46636b8 IY |
834 | pcibus_t tmp; |
835 | pcibus_t val; | |
836 | ||
837 | tmp = (pcibus_t)pci_get_word(d->config + base); | |
838 | val = (tmp & PCI_PREF_RANGE_MASK) << 16; | |
839 | if (tmp & PCI_PREF_RANGE_TYPE_64) { | |
840 | val |= (pcibus_t)pci_get_long(d->config + upper) << 32; | |
841 | } | |
a0c7a97e IY |
842 | return val; |
843 | } | |
844 | ||
845 | static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type) | |
846 | { | |
847 | pcibus_t base; | |
848 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
849 | base = pci_config_get_io_base(bridge, | |
850 | PCI_IO_BASE, PCI_IO_BASE_UPPER16); | |
851 | } else { | |
852 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
853 | base = pci_config_get_pref_base( | |
854 | bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); | |
855 | } else { | |
856 | base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); | |
857 | } | |
858 | } | |
859 | ||
860 | return base; | |
861 | } | |
862 | ||
863 | static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type) | |
864 | { | |
865 | pcibus_t limit; | |
866 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
867 | limit = pci_config_get_io_base(bridge, | |
868 | PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); | |
869 | limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ | |
870 | } else { | |
871 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
872 | limit = pci_config_get_pref_base( | |
873 | bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); | |
874 | } else { | |
875 | limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); | |
876 | } | |
877 | limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ | |
878 | } | |
879 | return limit; | |
880 | } | |
881 | ||
882 | static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, | |
883 | uint8_t type) | |
884 | { | |
885 | pcibus_t base = *addr; | |
886 | pcibus_t limit = *addr + *size - 1; | |
887 | PCIDevice *br; | |
888 | ||
889 | for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { | |
890 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
891 | ||
892 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
893 | if (!(cmd & PCI_COMMAND_IO)) { | |
894 | goto no_map; | |
895 | } | |
896 | } else { | |
897 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
898 | goto no_map; | |
899 | } | |
900 | } | |
901 | ||
902 | base = MAX(base, pci_bridge_get_base(br, type)); | |
903 | limit = MIN(limit, pci_bridge_get_limit(br, type)); | |
904 | } | |
905 | ||
906 | if (base > limit) { | |
88a95564 | 907 | goto no_map; |
a0c7a97e | 908 | } |
88a95564 MT |
909 | *addr = base; |
910 | *size = limit - base + 1; | |
911 | return; | |
912 | no_map: | |
913 | *addr = PCI_BAR_UNMAPPED; | |
914 | *size = 0; | |
a0c7a97e IY |
915 | } |
916 | ||
876a350d MT |
917 | static pcibus_t pci_bar_address(PCIDevice *d, |
918 | int reg, uint8_t type, pcibus_t size) | |
919 | { | |
920 | pcibus_t new_addr, last_addr; | |
921 | int bar = pci_bar(d, reg); | |
922 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
923 | ||
924 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
925 | if (!(cmd & PCI_COMMAND_IO)) { | |
926 | return PCI_BAR_UNMAPPED; | |
927 | } | |
928 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
929 | last_addr = new_addr + size - 1; | |
930 | /* NOTE: we have only 64K ioports on PC */ | |
931 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
932 | return PCI_BAR_UNMAPPED; | |
933 | } | |
934 | return new_addr; | |
935 | } | |
936 | ||
937 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
938 | return PCI_BAR_UNMAPPED; | |
939 | } | |
940 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
941 | new_addr = pci_get_quad(d->config + bar); | |
942 | } else { | |
943 | new_addr = pci_get_long(d->config + bar); | |
944 | } | |
945 | /* the ROM slot has a specific enable bit */ | |
946 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
947 | return PCI_BAR_UNMAPPED; | |
948 | } | |
949 | new_addr &= ~(size - 1); | |
950 | last_addr = new_addr + size - 1; | |
951 | /* NOTE: we do not support wrapping */ | |
952 | /* XXX: as we cannot support really dynamic | |
953 | mappings, we handle specific values as invalid | |
954 | mappings. */ | |
955 | if (last_addr <= new_addr || new_addr == 0 || | |
956 | last_addr == PCI_BAR_UNMAPPED) { | |
957 | return PCI_BAR_UNMAPPED; | |
958 | } | |
959 | ||
960 | /* Now pcibus_t is 64bit. | |
961 | * Check if 32 bit BAR wraps around explicitly. | |
962 | * Without this, PC ide doesn't work well. | |
963 | * TODO: remove this work around. | |
964 | */ | |
965 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
966 | return PCI_BAR_UNMAPPED; | |
967 | } | |
968 | ||
969 | /* | |
970 | * OS is allowed to set BAR beyond its addressable | |
971 | * bits. For example, 32 bit OS can set 64bit bar | |
972 | * to >4G. Check it. TODO: we might need to support | |
973 | * it in the future for e.g. PAE. | |
974 | */ | |
975 | if (last_addr >= TARGET_PHYS_ADDR_MAX) { | |
976 | return PCI_BAR_UNMAPPED; | |
977 | } | |
978 | ||
979 | return new_addr; | |
980 | } | |
981 | ||
0ac32c83 FB |
982 | static void pci_update_mappings(PCIDevice *d) |
983 | { | |
984 | PCIIORegion *r; | |
876a350d | 985 | int i; |
c71b5b4a | 986 | pcibus_t new_addr, filtered_size; |
3b46e624 | 987 | |
8a8696a3 | 988 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 989 | r = &d->io_regions[i]; |
a9688570 IY |
990 | |
991 | /* this region isn't registered */ | |
ec503442 | 992 | if (!r->size) |
a9688570 IY |
993 | continue; |
994 | ||
876a350d | 995 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 | 996 | |
a0c7a97e IY |
997 | /* bridge filtering */ |
998 | filtered_size = r->size; | |
999 | if (new_addr != PCI_BAR_UNMAPPED) { | |
1000 | pci_bridge_filter(d, &new_addr, &filtered_size, r->type); | |
1001 | } | |
1002 | ||
a9688570 | 1003 | /* This bar isn't changed */ |
a0c7a97e | 1004 | if (new_addr == r->addr && filtered_size == r->filtered_size) |
a9688570 IY |
1005 | continue; |
1006 | ||
1007 | /* now do the real mapping */ | |
1008 | if (r->addr != PCI_BAR_UNMAPPED) { | |
1009 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1010 | int class; | |
1011 | /* NOTE: specific hack for IDE in PC case: | |
1012 | only one byte must be mapped. */ | |
1013 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
1014 | if (class == 0x0101 && r->size == 4) { | |
1015 | isa_unassign_ioport(r->addr + 2, 1); | |
1016 | } else { | |
a0c7a97e | 1017 | isa_unassign_ioport(r->addr, r->filtered_size); |
0ac32c83 | 1018 | } |
a9688570 | 1019 | } else { |
c71b5b4a | 1020 | cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), |
a0c7a97e | 1021 | r->filtered_size, |
a9688570 | 1022 | IO_MEM_UNASSIGNED); |
a0c7a97e | 1023 | qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
0ac32c83 FB |
1024 | } |
1025 | } | |
a9688570 | 1026 | r->addr = new_addr; |
a0c7a97e | 1027 | r->filtered_size = filtered_size; |
a9688570 | 1028 | if (r->addr != PCI_BAR_UNMAPPED) { |
a0c7a97e IY |
1029 | /* |
1030 | * TODO: currently almost all the map funcions assumes | |
1031 | * filtered_size == size and addr & ~(size - 1) == addr. | |
1032 | * However with bridge filtering, they aren't always true. | |
1033 | * Teach them such cases, such that filtered_size < size and | |
1034 | * addr & (size - 1) != 0. | |
1035 | */ | |
cf616802 BS |
1036 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1037 | r->map_func(d, i, r->addr, r->filtered_size, r->type); | |
1038 | } else { | |
1039 | r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr), | |
1040 | r->filtered_size, r->type); | |
1041 | } | |
a9688570 | 1042 | } |
0ac32c83 FB |
1043 | } |
1044 | } | |
1045 | ||
a7b15a5c MT |
1046 | static inline int pci_irq_disabled(PCIDevice *d) |
1047 | { | |
1048 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1049 | } | |
1050 | ||
1051 | /* Called after interrupt disabled field update in config space, | |
1052 | * assert/deassert interrupts if necessary. | |
1053 | * Gets original interrupt disable bit value (before update). */ | |
1054 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1055 | { | |
1056 | int i, disabled = pci_irq_disabled(d); | |
1057 | if (disabled == was_irq_disabled) | |
1058 | return; | |
1059 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1060 | int state = pci_irq_state(d, i); | |
1061 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1062 | } | |
1063 | } | |
1064 | ||
5fafdf24 | 1065 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1066 | uint32_t address, int len) |
69b91039 | 1067 | { |
5029fe12 IY |
1068 | uint32_t val = 0; |
1069 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 1070 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
1071 | memcpy(&val, d->config + address, len); |
1072 | return le32_to_cpu(val); | |
0ac32c83 FB |
1073 | } |
1074 | ||
b7ee1603 | 1075 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 1076 | { |
a7b15a5c | 1077 | int i, was_irq_disabled = pci_irq_disabled(d); |
a9f49946 | 1078 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 1079 | |
91011d4f SW |
1080 | for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
1081 | uint8_t wmask = d->wmask[addr + i]; | |
1082 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); | |
0ac32c83 | 1083 | } |
260c0cd3 | 1084 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1085 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1086 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1087 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1088 | pci_update_mappings(d); |
a7b15a5c MT |
1089 | |
1090 | if (range_covers_byte(addr, l, PCI_COMMAND)) | |
1091 | pci_update_irq_disabled(d, was_irq_disabled); | |
69b91039 FB |
1092 | } |
1093 | ||
502a5395 PB |
1094 | /***********************************************************/ |
1095 | /* generic PCI irq support */ | |
30468f78 | 1096 | |
502a5395 | 1097 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1098 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1099 | { |
a60380a5 | 1100 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1101 | int change; |
3b46e624 | 1102 | |
d036bb21 | 1103 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1104 | if (!change) |
1105 | return; | |
d2b59317 | 1106 | |
d036bb21 | 1107 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1108 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1109 | if (pci_irq_disabled(pci_dev)) |
1110 | return; | |
d036bb21 | 1111 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1112 | } |
1113 | ||
502a5395 PB |
1114 | /***********************************************************/ |
1115 | /* monitor info on PCI */ | |
0ac32c83 | 1116 | |
6650ee6d PB |
1117 | typedef struct { |
1118 | uint16_t class; | |
1119 | const char *desc; | |
1120 | } pci_class_desc; | |
1121 | ||
09bc878a | 1122 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1123 | { |
4ca9c76f | 1124 | { 0x0100, "SCSI controller"}, |
6650ee6d | 1125 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
1126 | { 0x0102, "Floppy controller"}, |
1127 | { 0x0103, "IPI controller"}, | |
1128 | { 0x0104, "RAID controller"}, | |
1129 | { 0x0106, "SATA controller"}, | |
1130 | { 0x0107, "SAS controller"}, | |
1131 | { 0x0180, "Storage controller"}, | |
6650ee6d | 1132 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
1133 | { 0x0201, "Token Ring controller"}, |
1134 | { 0x0202, "FDDI controller"}, | |
1135 | { 0x0203, "ATM controller"}, | |
1136 | { 0x0280, "Network controller"}, | |
6650ee6d | 1137 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
1138 | { 0x0301, "XGA controller"}, |
1139 | { 0x0302, "3D controller"}, | |
1140 | { 0x0380, "Display controller"}, | |
1141 | { 0x0400, "Video controller"}, | |
1142 | { 0x0401, "Audio controller"}, | |
1143 | { 0x0402, "Phone"}, | |
1144 | { 0x0480, "Multimedia controller"}, | |
1145 | { 0x0500, "RAM controller"}, | |
1146 | { 0x0501, "Flash controller"}, | |
1147 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
1148 | { 0x0600, "Host bridge"}, |
1149 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
1150 | { 0x0602, "EISA bridge"}, |
1151 | { 0x0603, "MC bridge"}, | |
6650ee6d | 1152 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
1153 | { 0x0605, "PCMCIA bridge"}, |
1154 | { 0x0606, "NUBUS bridge"}, | |
1155 | { 0x0607, "CARDBUS bridge"}, | |
1156 | { 0x0608, "RACEWAY bridge"}, | |
1157 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
1158 | { 0x0c03, "USB controller"}, |
1159 | { 0, NULL} | |
1160 | }; | |
1161 | ||
163c8a59 LC |
1162 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1163 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
30468f78 | 1164 | { |
163c8a59 LC |
1165 | PCIDevice *d; |
1166 | int devfn; | |
30468f78 | 1167 | |
163c8a59 LC |
1168 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1169 | d = bus->devices[devfn]; | |
1170 | if (d) { | |
1171 | fn(bus, d); | |
1172 | } | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
1177 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
1178 | { | |
1179 | bus = pci_find_bus(bus, bus_num); | |
1180 | ||
1181 | if (bus) { | |
1182 | pci_for_each_device_under_bus(bus, fn); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | static void pci_device_print(Monitor *mon, QDict *device) | |
1187 | { | |
1188 | QDict *qdict; | |
1189 | QListEntry *entry; | |
1190 | uint64_t addr, size; | |
1191 | ||
1192 | monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus")); | |
1193 | monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n", | |
1194 | qdict_get_int(device, "slot"), | |
1195 | qdict_get_int(device, "function")); | |
376253ec | 1196 | monitor_printf(mon, " "); |
163c8a59 LC |
1197 | |
1198 | qdict = qdict_get_qdict(device, "class_info"); | |
1199 | if (qdict_haskey(qdict, "desc")) { | |
1200 | monitor_printf(mon, "%s", qdict_get_str(qdict, "desc")); | |
6650ee6d | 1201 | } else { |
163c8a59 | 1202 | monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class")); |
72cc6cfe | 1203 | } |
30468f78 | 1204 | |
163c8a59 LC |
1205 | qdict = qdict_get_qdict(device, "id"); |
1206 | monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", | |
1207 | qdict_get_int(qdict, "device"), | |
1208 | qdict_get_int(qdict, "vendor")); | |
1209 | ||
1210 | if (qdict_haskey(device, "irq")) { | |
1211 | monitor_printf(mon, " IRQ %" PRId64 ".\n", | |
1212 | qdict_get_int(device, "irq")); | |
30468f78 | 1213 | } |
b4dccd8d | 1214 | |
163c8a59 LC |
1215 | if (qdict_haskey(device, "pci_bridge")) { |
1216 | QDict *info; | |
1217 | ||
1218 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1219 | ||
1220 | info = qdict_get_qdict(qdict, "bus"); | |
1221 | monitor_printf(mon, " BUS %" PRId64 ".\n", | |
1222 | qdict_get_int(info, "number")); | |
1223 | monitor_printf(mon, " secondary bus %" PRId64 ".\n", | |
1224 | qdict_get_int(info, "secondary")); | |
1225 | monitor_printf(mon, " subordinate bus %" PRId64 ".\n", | |
1226 | qdict_get_int(info, "subordinate")); | |
b4dccd8d | 1227 | |
163c8a59 | 1228 | info = qdict_get_qdict(qdict, "io_range"); |
b4dccd8d | 1229 | monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
163c8a59 LC |
1230 | qdict_get_int(info, "base"), |
1231 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1232 | |
163c8a59 | 1233 | info = qdict_get_qdict(qdict, "memory_range"); |
b4dccd8d IY |
1234 | monitor_printf(mon, |
1235 | " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", | |
163c8a59 LC |
1236 | qdict_get_int(info, "base"), |
1237 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1238 | |
163c8a59 | 1239 | info = qdict_get_qdict(qdict, "prefetchable_range"); |
b4dccd8d | 1240 | monitor_printf(mon, " prefetchable memory range " |
163c8a59 LC |
1241 | "[0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1242 | qdict_get_int(info, "base"), | |
1243 | qdict_get_int(info, "limit")); | |
80b3ada7 | 1244 | } |
14421258 | 1245 | |
163c8a59 LC |
1246 | QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) { |
1247 | qdict = qobject_to_qdict(qlist_entry_obj(entry)); | |
1248 | monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar")); | |
1249 | ||
1250 | addr = qdict_get_int(qdict, "address"); | |
1251 | size = qdict_get_int(qdict, "size"); | |
1252 | ||
1253 | if (!strcmp(qdict_get_str(qdict, "type"), "io")) { | |
1254 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS | |
1255 | " [0x%04"FMT_PCIBUS"].\n", | |
1256 | addr, addr + size - 1); | |
1257 | } else { | |
1258 | monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 1259 | " [0x%08"FMT_PCIBUS"].\n", |
163c8a59 LC |
1260 | qdict_get_bool(qdict, "mem_type_64") ? 64 : 32, |
1261 | qdict_get_bool(qdict, "prefetch") ? | |
1262 | " prefetchable" : "", addr, addr + size - 1); | |
502a5395 | 1263 | } |
77d4bc34 | 1264 | } |
163c8a59 LC |
1265 | |
1266 | monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id")); | |
1267 | ||
d5e4acf7 LC |
1268 | if (qdict_haskey(device, "pci_bridge")) { |
1269 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1270 | if (qdict_haskey(qdict, "devices")) { | |
1271 | QListEntry *dev; | |
1272 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1273 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1274 | } | |
1275 | } | |
1276 | } | |
163c8a59 LC |
1277 | } |
1278 | ||
1279 | void do_pci_info_print(Monitor *mon, const QObject *data) | |
1280 | { | |
1281 | QListEntry *bus, *dev; | |
1282 | ||
1283 | QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) { | |
1284 | QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus)); | |
1285 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1286 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1287 | } | |
80b3ada7 | 1288 | } |
384d8876 FB |
1289 | } |
1290 | ||
163c8a59 LC |
1291 | static QObject *pci_get_dev_class(const PCIDevice *dev) |
1292 | { | |
1293 | int class; | |
1294 | const pci_class_desc *desc; | |
1295 | ||
1296 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1297 | desc = pci_class_descriptions; | |
1298 | while (desc->desc && class != desc->class) | |
1299 | desc++; | |
1300 | ||
1301 | if (desc->desc) { | |
1302 | return qobject_from_jsonf("{ 'desc': %s, 'class': %d }", | |
1303 | desc->desc, class); | |
1304 | } else { | |
1305 | return qobject_from_jsonf("{ 'class': %d }", class); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | static QObject *pci_get_dev_id(const PCIDevice *dev) | |
1310 | { | |
1311 | return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }", | |
1312 | pci_get_word(dev->config + PCI_VENDOR_ID), | |
1313 | pci_get_word(dev->config + PCI_DEVICE_ID)); | |
1314 | } | |
1315 | ||
1316 | static QObject *pci_get_regions_list(const PCIDevice *dev) | |
1317 | { | |
1318 | int i; | |
1319 | QList *regions_list; | |
1320 | ||
1321 | regions_list = qlist_new(); | |
1322 | ||
1323 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1324 | QObject *obj; | |
1325 | const PCIIORegion *r = &dev->io_regions[i]; | |
1326 | ||
1327 | if (!r->size) { | |
1328 | continue; | |
1329 | } | |
1330 | ||
1331 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1332 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', " | |
1333 | "'address': %" PRId64 ", " | |
1334 | "'size': %" PRId64 " }", | |
1335 | i, r->addr, r->size); | |
1336 | } else { | |
1337 | int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
1338 | ||
1339 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', " | |
1340 | "'mem_type_64': %i, 'prefetch': %i, " | |
1341 | "'address': %" PRId64 ", " | |
1342 | "'size': %" PRId64 " }", | |
1343 | i, mem_type_64, | |
1344 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH, | |
1345 | r->addr, r->size); | |
1346 | } | |
1347 | ||
1348 | qlist_append_obj(regions_list, obj); | |
1349 | } | |
1350 | ||
1351 | return QOBJECT(regions_list); | |
1352 | } | |
1353 | ||
d5e4acf7 LC |
1354 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num); |
1355 | ||
1356 | static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num) | |
163c8a59 | 1357 | { |
b5937f29 | 1358 | uint8_t type; |
163c8a59 LC |
1359 | QObject *obj; |
1360 | ||
1361 | obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p," | |
1362 | " 'qdev_id': %s }", | |
1363 | bus_num, | |
1364 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
1365 | pci_get_dev_class(dev), pci_get_dev_id(dev), | |
1366 | pci_get_regions_list(dev), | |
1367 | dev->qdev.id ? dev->qdev.id : ""); | |
1368 | ||
1369 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
1370 | QDict *qdict = qobject_to_qdict(obj); | |
1371 | qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE])); | |
1372 | } | |
1373 | ||
b5937f29 IY |
1374 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1375 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
163c8a59 LC |
1376 | QDict *qdict; |
1377 | QObject *pci_bridge; | |
1378 | ||
1379 | pci_bridge = qobject_from_jsonf("{ 'bus': " | |
1380 | "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, " | |
1381 | "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1382 | "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1383 | "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }", | |
c021f8e6 | 1384 | dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS], |
163c8a59 LC |
1385 | dev->config[PCI_SUBORDINATE_BUS], |
1386 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1387 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1388 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1389 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1390 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1391 | PCI_BASE_ADDRESS_MEM_PREFETCH), | |
1392 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1393 | PCI_BASE_ADDRESS_MEM_PREFETCH)); | |
1394 | ||
c021f8e6 BS |
1395 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1396 | PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); | |
d5e4acf7 | 1397 | |
c021f8e6 BS |
1398 | if (child_bus) { |
1399 | qdict = qobject_to_qdict(pci_bridge); | |
1400 | qdict_put_obj(qdict, "devices", | |
1401 | pci_get_devices_list(child_bus, | |
1402 | dev->config[PCI_SECONDARY_BUS])); | |
1403 | } | |
1404 | } | |
163c8a59 LC |
1405 | qdict = qobject_to_qdict(obj); |
1406 | qdict_put_obj(qdict, "pci_bridge", pci_bridge); | |
1407 | } | |
1408 | ||
1409 | return obj; | |
1410 | } | |
1411 | ||
1412 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num) | |
384d8876 | 1413 | { |
502a5395 | 1414 | int devfn; |
163c8a59 LC |
1415 | PCIDevice *dev; |
1416 | QList *dev_list; | |
3b46e624 | 1417 | |
163c8a59 LC |
1418 | dev_list = qlist_new(); |
1419 | ||
1420 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1421 | dev = bus->devices[devfn]; | |
1422 | if (dev) { | |
d5e4acf7 | 1423 | qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num)); |
163c8a59 | 1424 | } |
1074df4f | 1425 | } |
163c8a59 LC |
1426 | |
1427 | return QOBJECT(dev_list); | |
1074df4f IY |
1428 | } |
1429 | ||
163c8a59 | 1430 | static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num) |
1074df4f | 1431 | { |
e822a52a | 1432 | bus = pci_find_bus(bus, bus_num); |
502a5395 | 1433 | if (bus) { |
163c8a59 LC |
1434 | return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }", |
1435 | bus_num, pci_get_devices_list(bus, bus_num)); | |
f2aa58c6 | 1436 | } |
163c8a59 LC |
1437 | |
1438 | return NULL; | |
f2aa58c6 FB |
1439 | } |
1440 | ||
163c8a59 | 1441 | void do_pci_info(Monitor *mon, QObject **ret_data) |
f2aa58c6 | 1442 | { |
163c8a59 | 1443 | QList *bus_list; |
e822a52a | 1444 | struct PCIHostBus *host; |
163c8a59 LC |
1445 | |
1446 | bus_list = qlist_new(); | |
1447 | ||
e822a52a | 1448 | QLIST_FOREACH(host, &host_buses, next) { |
163c8a59 LC |
1449 | QObject *obj = pci_get_bus_dict(host->bus, 0); |
1450 | if (obj) { | |
1451 | qlist_append_obj(bus_list, obj); | |
1452 | } | |
e822a52a | 1453 | } |
163c8a59 LC |
1454 | |
1455 | *ret_data = QOBJECT(bus_list); | |
77d4bc34 | 1456 | } |
a41b2ff2 | 1457 | |
cb457d76 AL |
1458 | static const char * const pci_nic_models[] = { |
1459 | "ne2k_pci", | |
1460 | "i82551", | |
1461 | "i82557b", | |
1462 | "i82559er", | |
1463 | "rtl8139", | |
1464 | "e1000", | |
1465 | "pcnet", | |
1466 | "virtio", | |
1467 | NULL | |
1468 | }; | |
1469 | ||
9d07d757 PB |
1470 | static const char * const pci_nic_names[] = { |
1471 | "ne2k_pci", | |
1472 | "i82551", | |
1473 | "i82557b", | |
1474 | "i82559er", | |
1475 | "rtl8139", | |
1476 | "e1000", | |
1477 | "pcnet", | |
53c25cea | 1478 | "virtio-net-pci", |
cb457d76 AL |
1479 | NULL |
1480 | }; | |
1481 | ||
a41b2ff2 | 1482 | /* Initialize a PCI NIC. */ |
33e66b86 | 1483 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1484 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1485 | const char *default_devaddr) | |
a41b2ff2 | 1486 | { |
5607c388 | 1487 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1488 | PCIBus *bus; |
1489 | int devfn; | |
5607c388 | 1490 | PCIDevice *pci_dev; |
9d07d757 | 1491 | DeviceState *dev; |
cb457d76 AL |
1492 | int i; |
1493 | ||
07caea31 MA |
1494 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1495 | if (i < 0) | |
1496 | return NULL; | |
1497 | ||
1498 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1499 | if (!bus) { | |
1ecda02b MA |
1500 | error_report("Invalid PCI device address %s for device %s", |
1501 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1502 | return NULL; |
1503 | } | |
1504 | ||
499cf102 | 1505 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1506 | dev = &pci_dev->qdev; |
1cc33683 | 1507 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1508 | if (qdev_init(dev) < 0) |
1509 | return NULL; | |
9ee05825 | 1510 | return pci_dev; |
a41b2ff2 PB |
1511 | } |
1512 | ||
07caea31 MA |
1513 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1514 | const char *default_devaddr) | |
1515 | { | |
1516 | PCIDevice *res; | |
1517 | ||
1518 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1519 | exit(0); | |
1520 | ||
1521 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1522 | if (!res) | |
1523 | exit(1); | |
1524 | return res; | |
1525 | } | |
1526 | ||
80b3ada7 PB |
1527 | typedef struct { |
1528 | PCIDevice dev; | |
03587182 GH |
1529 | PCIBus bus; |
1530 | uint32_t vid; | |
1531 | uint32_t did; | |
80b3ada7 PB |
1532 | } PCIBridge; |
1533 | ||
a0c7a97e IY |
1534 | |
1535 | static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) | |
1536 | { | |
1537 | pci_update_mappings(d); | |
1538 | } | |
1539 | ||
1540 | static void pci_bridge_update_mappings(PCIBus *b) | |
1541 | { | |
1542 | PCIBus *child; | |
1543 | ||
1544 | pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); | |
1545 | ||
1546 | QLIST_FOREACH(child, &b->child, sibling) { | |
1547 | pci_bridge_update_mappings(child); | |
1548 | } | |
1549 | } | |
1550 | ||
9596ebb7 | 1551 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
1552 | uint32_t address, uint32_t val, int len) |
1553 | { | |
80b3ada7 | 1554 | pci_default_write_config(d, address, val, len); |
a0c7a97e IY |
1555 | |
1556 | if (/* io base/limit */ | |
1557 | ranges_overlap(address, len, PCI_IO_BASE, 2) || | |
1558 | ||
1559 | /* memory base/limit, prefetchable base/limit and | |
1560 | io base/limit upper 16 */ | |
1561 | ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { | |
1562 | pci_bridge_update_mappings(d->bus); | |
1563 | } | |
80b3ada7 PB |
1564 | } |
1565 | ||
e822a52a | 1566 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 1567 | { |
470e6363 | 1568 | PCIBus *sec; |
3ae80618 | 1569 | |
470e6363 | 1570 | if (!bus) { |
e822a52a | 1571 | return NULL; |
470e6363 | 1572 | } |
3ae80618 | 1573 | |
e822a52a IY |
1574 | if (pci_bus_num(bus) == bus_num) { |
1575 | return bus; | |
1576 | } | |
1577 | ||
1578 | /* try child bus */ | |
470e6363 IY |
1579 | if (!bus->parent_dev /* host pci bridge */ || |
1580 | (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1581 | bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { | |
1582 | for (; bus; bus = sec) { | |
1583 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1584 | assert(sec->parent_dev); | |
1585 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1586 | return sec; | |
1587 | } | |
1588 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1589 | bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) { | |
1590 | break; | |
1591 | } | |
c021f8e6 | 1592 | } |
e822a52a IY |
1593 | } |
1594 | } | |
1595 | ||
1596 | return NULL; | |
3ae80618 AL |
1597 | } |
1598 | ||
e822a52a | 1599 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
3ae80618 | 1600 | { |
e822a52a | 1601 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
1602 | |
1603 | if (!bus) | |
1604 | return NULL; | |
1605 | ||
1606 | return bus->devices[PCI_DEVFN(slot, function)]; | |
1607 | } | |
1608 | ||
03587182 | 1609 | static int pci_bridge_initfn(PCIDevice *dev) |
80b3ada7 | 1610 | { |
03587182 | 1611 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
480b9f24 | 1612 | |
03587182 GH |
1613 | pci_config_set_vendor_id(s->dev.config, s->vid); |
1614 | pci_config_set_device_id(s->dev.config, s->did); | |
480b9f24 | 1615 | |
74c01823 IY |
1616 | pci_set_word(dev->config + PCI_STATUS, |
1617 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
1618 | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); | |
e327e323 IY |
1619 | dev->config[PCI_HEADER_TYPE] = |
1620 | (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | | |
1621 | PCI_HEADER_TYPE_BRIDGE; | |
74c01823 IY |
1622 | pci_set_word(dev->config + PCI_SEC_STATUS, |
1623 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
03587182 GH |
1624 | return 0; |
1625 | } | |
80b3ada7 | 1626 | |
e822a52a IY |
1627 | static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1628 | { | |
1629 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); | |
1630 | PCIBus *bus = &s->bus; | |
1631 | pci_unregister_secondary_bus(bus); | |
1632 | return 0; | |
1633 | } | |
1634 | ||
7c7b829e IY |
1635 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction, |
1636 | uint16_t vid, uint16_t did, | |
03587182 GH |
1637 | pci_map_irq_fn map_irq, const char *name) |
1638 | { | |
1639 | PCIDevice *dev; | |
1640 | PCIBridge *s; | |
1641 | ||
7c7b829e | 1642 | dev = pci_create_multifunction(bus, devfn, multifunction, "pci-bridge"); |
03587182 GH |
1643 | qdev_prop_set_uint32(&dev->qdev, "vendorid", vid); |
1644 | qdev_prop_set_uint32(&dev->qdev, "deviceid", did); | |
e23a1b33 | 1645 | qdev_init_nofail(&dev->qdev); |
03587182 GH |
1646 | |
1647 | s = DO_UPCAST(PCIBridge, dev, dev); | |
e822a52a | 1648 | pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
03587182 | 1649 | return &s->bus; |
80b3ada7 | 1650 | } |
6b1b92d3 | 1651 | |
d6318738 MT |
1652 | PCIDevice *pci_bridge_get_device(PCIBus *bus) |
1653 | { | |
1654 | return bus->parent_dev; | |
1655 | } | |
1656 | ||
81a322d4 | 1657 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1658 | { |
1659 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1660 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1661 | PCIBus *bus; |
ee995ffb | 1662 | int devfn, rc; |
6b1b92d3 | 1663 | |
a9f49946 IY |
1664 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1665 | if (info->is_express) { | |
1666 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1667 | } | |
1668 | ||
02e2da45 | 1669 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 1670 | devfn = pci_dev->devfn; |
16eaedf2 | 1671 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
fb231628 | 1672 | info->config_read, info->config_write, |
e327e323 | 1673 | info->is_bridge); |
09e3acc6 GH |
1674 | if (pci_dev == NULL) |
1675 | return -1; | |
ee995ffb | 1676 | rc = info->init(pci_dev); |
925fe64a AW |
1677 | if (rc != 0) { |
1678 | do_pci_unregister_device(pci_dev); | |
ee995ffb | 1679 | return rc; |
925fe64a | 1680 | } |
8c52c8f3 GH |
1681 | |
1682 | /* rom loading */ | |
1683 | if (pci_dev->romfile == NULL && info->romfile != NULL) | |
1684 | pci_dev->romfile = qemu_strdup(info->romfile); | |
1685 | pci_add_option_rom(pci_dev); | |
1686 | ||
ee995ffb | 1687 | if (qdev->hotplugged) |
87c30546 | 1688 | bus->hotplug(bus->hotplug_qdev, pci_dev, 1); |
ee995ffb GH |
1689 | return 0; |
1690 | } | |
1691 | ||
1692 | static int pci_unplug_device(DeviceState *qdev) | |
1693 | { | |
1694 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
1695 | ||
87c30546 | 1696 | dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0); |
ee995ffb | 1697 | return 0; |
6b1b92d3 PB |
1698 | } |
1699 | ||
0aab0d3a | 1700 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1701 | { |
02e2da45 | 1702 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1703 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1704 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1705 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1706 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1707 | } |
1708 | ||
0aab0d3a GH |
1709 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1710 | { | |
1711 | while (info->qdev.name) { | |
1712 | pci_qdev_register(info); | |
1713 | info++; | |
1714 | } | |
1715 | } | |
1716 | ||
49823868 IY |
1717 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1718 | const char *name) | |
6b1b92d3 PB |
1719 | { |
1720 | DeviceState *dev; | |
1721 | ||
02e2da45 | 1722 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1723 | qdev_prop_set_uint32(dev, "addr", devfn); |
49823868 | 1724 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
71077c1c GH |
1725 | return DO_UPCAST(PCIDevice, qdev, dev); |
1726 | } | |
6b1b92d3 | 1727 | |
49823868 IY |
1728 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1729 | bool multifunction, | |
1730 | const char *name) | |
71077c1c | 1731 | { |
49823868 | 1732 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1733 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1734 | return dev; |
6b1b92d3 | 1735 | } |
6f4cbd39 | 1736 | |
49823868 IY |
1737 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1738 | { | |
1739 | return pci_create_multifunction(bus, devfn, false, name); | |
1740 | } | |
1741 | ||
1742 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1743 | { | |
1744 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1745 | } | |
1746 | ||
6f4cbd39 MT |
1747 | static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1748 | { | |
a9f49946 | 1749 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1750 | int offset = PCI_CONFIG_HEADER_SIZE; |
1751 | int i; | |
a9f49946 | 1752 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1753 | if (pdev->used[i]) |
1754 | offset = i + 1; | |
1755 | else if (i - offset + 1 == size) | |
1756 | return offset; | |
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1761 | uint8_t *prev_p) | |
1762 | { | |
1763 | uint8_t next, prev; | |
1764 | ||
1765 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1766 | return 0; | |
1767 | ||
1768 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1769 | prev = next + PCI_CAP_LIST_NEXT) | |
1770 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1771 | break; | |
1772 | ||
1773 | if (prev_p) | |
1774 | *prev_p = prev; | |
1775 | return next; | |
1776 | } | |
1777 | ||
c2039bd0 AL |
1778 | static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1779 | { | |
1780 | cpu_register_physical_memory(addr, size, pdev->rom_offset); | |
1781 | } | |
1782 | ||
1783 | /* Add an option rom for the device */ | |
8c52c8f3 | 1784 | static int pci_add_option_rom(PCIDevice *pdev) |
c2039bd0 AL |
1785 | { |
1786 | int size; | |
1787 | char *path; | |
1788 | void *ptr; | |
1724f049 | 1789 | char name[32]; |
c2039bd0 | 1790 | |
8c52c8f3 GH |
1791 | if (!pdev->romfile) |
1792 | return 0; | |
1793 | if (strlen(pdev->romfile) == 0) | |
1794 | return 0; | |
1795 | ||
88169ddf GH |
1796 | if (!pdev->rom_bar) { |
1797 | /* | |
1798 | * Load rom via fw_cfg instead of creating a rom bar, | |
1799 | * for 0.11 compatibility. | |
1800 | */ | |
1801 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1802 | if (class == 0x0300) { | |
1803 | rom_add_vga(pdev->romfile); | |
1804 | } else { | |
1805 | rom_add_option(pdev->romfile); | |
1806 | } | |
1807 | return 0; | |
1808 | } | |
1809 | ||
8c52c8f3 | 1810 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1811 | if (path == NULL) { |
8c52c8f3 | 1812 | path = qemu_strdup(pdev->romfile); |
c2039bd0 AL |
1813 | } |
1814 | ||
1815 | size = get_image_size(path); | |
8c52c8f3 | 1816 | if (size < 0) { |
1ecda02b MA |
1817 | error_report("%s: failed to find romfile \"%s\"", |
1818 | __FUNCTION__, pdev->romfile); | |
8c52c8f3 GH |
1819 | return -1; |
1820 | } | |
c2039bd0 AL |
1821 | if (size & (size - 1)) { |
1822 | size = 1 << qemu_fls(size); | |
1823 | } | |
1824 | ||
1724f049 AW |
1825 | if (pdev->qdev.info->vmsd) |
1826 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name); | |
1827 | else | |
1828 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name); | |
1829 | pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size); | |
c2039bd0 AL |
1830 | |
1831 | ptr = qemu_get_ram_ptr(pdev->rom_offset); | |
1832 | load_image(path, ptr); | |
1833 | qemu_free(path); | |
1834 | ||
1835 | pci_register_bar(pdev, PCI_ROM_SLOT, size, | |
1836 | 0, pci_map_option_rom); | |
1837 | ||
1838 | return 0; | |
1839 | } | |
1840 | ||
230741dc AW |
1841 | static void pci_del_option_rom(PCIDevice *pdev) |
1842 | { | |
1843 | if (!pdev->rom_offset) | |
1844 | return; | |
1845 | ||
1846 | qemu_ram_free(pdev->rom_offset); | |
1847 | pdev->rom_offset = 0; | |
1848 | } | |
1849 | ||
6f4cbd39 | 1850 | /* Reserve space and add capability to the linked list in pci config space */ |
1db5a3aa MT |
1851 | int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id, |
1852 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1853 | { |
6f4cbd39 | 1854 | uint8_t *config = pdev->config + offset; |
6f4cbd39 MT |
1855 | config[PCI_CAP_LIST_ID] = cap_id; |
1856 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1857 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1858 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1859 | memset(pdev->used + offset, 0xFF, size); | |
1860 | /* Make capability read-only by default */ | |
1861 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1862 | /* Check capability by default */ |
1863 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1864 | return offset; |
1865 | } | |
1866 | ||
1db5a3aa MT |
1867 | /* Find and reserve space and add capability to the linked list |
1868 | * in pci config space */ | |
1869 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1870 | { | |
1871 | uint8_t offset = pci_find_space(pdev, size); | |
1872 | if (!offset) { | |
1873 | return -ENOSPC; | |
1874 | } | |
1875 | return pci_add_capability_at_offset(pdev, cap_id, offset, size); | |
1876 | } | |
1877 | ||
6f4cbd39 MT |
1878 | /* Unlink capability from the pci config space. */ |
1879 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1880 | { | |
1881 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1882 | if (!offset) | |
1883 | return; | |
1884 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
1885 | /* Make capability writeable again */ | |
1886 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
1887 | /* Clear cmask as device-specific registers can't be checked */ |
1888 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1889 | memset(pdev->used + offset, 0, size); |
1890 | ||
1891 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1892 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1893 | } | |
1894 | ||
1895 | /* Reserve space for capability at a known offset (to call after load). */ | |
1896 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1897 | { | |
1898 | memset(pdev->used + offset, 0xff, size); | |
1899 | } | |
1900 | ||
1901 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1902 | { | |
1903 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1904 | } | |
10c4c98a GH |
1905 | |
1906 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1907 | { | |
1908 | PCIDevice *d = (PCIDevice *)dev; | |
1909 | const pci_class_desc *desc; | |
1910 | char ctxt[64]; | |
1911 | PCIIORegion *r; | |
1912 | int i, class; | |
1913 | ||
b0ff8eb2 | 1914 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1915 | desc = pci_class_descriptions; |
1916 | while (desc->desc && class != desc->class) | |
1917 | desc++; | |
1918 | if (desc->desc) { | |
1919 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1920 | } else { | |
1921 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1922 | } | |
1923 | ||
1924 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1925 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1926 | indent, "", ctxt, | |
e822a52a IY |
1927 | d->config[PCI_SECONDARY_BUS], |
1928 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), | |
b0ff8eb2 IY |
1929 | pci_get_word(d->config + PCI_VENDOR_ID), |
1930 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1931 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1932 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1933 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1934 | r = &d->io_regions[i]; | |
1935 | if (!r->size) | |
1936 | continue; | |
89e8b13c IY |
1937 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1938 | " [0x%"FMT_PCIBUS"]\n", | |
1939 | indent, "", | |
0392a017 | 1940 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1941 | r->addr, r->addr + r->size - 1); |
1942 | } | |
1943 | } | |
03587182 | 1944 | |
4f43c1ff AW |
1945 | static char *pcibus_get_dev_path(DeviceState *dev) |
1946 | { | |
1947 | PCIDevice *d = (PCIDevice *)dev; | |
1948 | char path[16]; | |
1949 | ||
1950 | snprintf(path, sizeof(path), "%04x:%02x:%02x.%x", | |
1951 | pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS], | |
1952 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); | |
1953 | ||
1954 | return strdup(path); | |
1955 | } | |
1956 | ||
03587182 GH |
1957 | static PCIDeviceInfo bridge_info = { |
1958 | .qdev.name = "pci-bridge", | |
1959 | .qdev.size = sizeof(PCIBridge), | |
1960 | .init = pci_bridge_initfn, | |
e822a52a | 1961 | .exit = pci_bridge_exitfn, |
03587182 | 1962 | .config_write = pci_bridge_write_config, |
e327e323 | 1963 | .is_bridge = 1, |
03587182 GH |
1964 | .qdev.props = (Property[]) { |
1965 | DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), | |
1966 | DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), | |
1967 | DEFINE_PROP_END_OF_LIST(), | |
1968 | } | |
1969 | }; | |
1970 | ||
1971 | static void pci_register_devices(void) | |
1972 | { | |
1973 | pci_qdev_register(&bridge_info); | |
1974 | } | |
1975 | ||
1976 | device_init(pci_register_devices) |