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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
69b91039 FB |
29 | |
30 | //#define DEBUG_PCI | |
d8d2e079 IY |
31 | #ifdef DEBUG_PCI |
32 | # define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__) | |
33 | #else | |
34 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
35 | #endif | |
69b91039 | 36 | |
30468f78 | 37 | struct PCIBus { |
02e2da45 | 38 | BusState qbus; |
30468f78 FB |
39 | int bus_num; |
40 | int devfn_min; | |
502a5395 | 41 | pci_set_irq_fn set_irq; |
d2b59317 | 42 | pci_map_irq_fn map_irq; |
30468f78 | 43 | uint32_t config_reg; /* XXX: suppress */ |
384d8876 FB |
44 | /* low level pic */ |
45 | SetIRQFunc *low_set_irq; | |
d537cf6c | 46 | qemu_irq *irq_opaque; |
30468f78 | 47 | PCIDevice *devices[256]; |
80b3ada7 PB |
48 | PCIDevice *parent_dev; |
49 | PCIBus *next; | |
d2b59317 PB |
50 | /* The bus IRQ state is the logical OR of the connected devices. |
51 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 52 | int nirq; |
10c4c98a GH |
53 | int *irq_count; |
54 | }; | |
55 | ||
56 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
57 | ||
58 | static struct BusInfo pci_bus_info = { | |
59 | .name = "PCI", | |
60 | .size = sizeof(PCIBus), | |
61 | .print_dev = pcibus_dev_print, | |
ee6847d1 | 62 | .props = (Property[]) { |
54586bd1 GH |
63 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
64 | DEFINE_PROP_END_OF_LIST() | |
ee6847d1 | 65 | } |
30468f78 | 66 | }; |
69b91039 | 67 | |
1941d19c | 68 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 69 | static void pci_set_irq(void *opaque, int irq_num, int level); |
1941d19c | 70 | |
69b91039 | 71 | target_phys_addr_t pci_mem_base; |
d350d97d AL |
72 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
73 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
30468f78 FB |
74 | static PCIBus *first_bus; |
75 | ||
2d1e9f96 JQ |
76 | static const VMStateDescription vmstate_pcibus = { |
77 | .name = "PCIBUS", | |
78 | .version_id = 1, | |
79 | .minimum_version_id = 1, | |
80 | .minimum_version_id_old = 1, | |
81 | .fields = (VMStateField []) { | |
82 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
83 | VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq), | |
84 | VMSTATE_END_OF_LIST() | |
52fc1d83 | 85 | } |
2d1e9f96 | 86 | }; |
52fc1d83 | 87 | |
6eaa6847 GN |
88 | static void pci_bus_reset(void *opaque) |
89 | { | |
90 | PCIBus *bus = (PCIBus *)opaque; | |
91 | int i; | |
92 | ||
93 | for (i = 0; i < bus->nirq; i++) { | |
94 | bus->irq_count[i] = 0; | |
95 | } | |
96 | for (i = 0; i < 256; i++) { | |
97 | if (bus->devices[i]) | |
98 | memset(bus->devices[i]->irq_state, 0, | |
99 | sizeof(bus->devices[i]->irq_state)); | |
100 | } | |
101 | } | |
102 | ||
02e2da45 PB |
103 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
104 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
d537cf6c | 105 | qemu_irq *pic, int devfn_min, int nirq) |
30468f78 FB |
106 | { |
107 | PCIBus *bus; | |
52fc1d83 AZ |
108 | static int nbus = 0; |
109 | ||
10c4c98a | 110 | bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name)); |
502a5395 | 111 | bus->set_irq = set_irq; |
d2b59317 | 112 | bus->map_irq = map_irq; |
502a5395 PB |
113 | bus->irq_opaque = pic; |
114 | bus->devfn_min = devfn_min; | |
52fc1d83 | 115 | bus->nirq = nirq; |
616cbc78 | 116 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
425c608c | 117 | bus->next = first_bus; |
30468f78 | 118 | first_bus = bus; |
2d1e9f96 | 119 | vmstate_register(nbus++, &vmstate_pcibus, bus); |
a08d4367 | 120 | qemu_register_reset(pci_bus_reset, bus); |
30468f78 FB |
121 | return bus; |
122 | } | |
69b91039 | 123 | |
72f44c8c BS |
124 | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, |
125 | pci_map_irq_fn map_irq, | |
126 | const char *name) | |
80b3ada7 PB |
127 | { |
128 | PCIBus *bus; | |
16eaedf2 | 129 | |
72f44c8c | 130 | bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name)); |
80b3ada7 PB |
131 | bus->map_irq = map_irq; |
132 | bus->parent_dev = dev; | |
133 | bus->next = dev->bus->next; | |
134 | dev->bus->next = bus; | |
135 | return bus; | |
136 | } | |
137 | ||
502a5395 PB |
138 | int pci_bus_num(PCIBus *s) |
139 | { | |
140 | return s->bus_num; | |
141 | } | |
142 | ||
1941d19c | 143 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
30ca2aab | 144 | { |
52fc1d83 AZ |
145 | int i; |
146 | ||
f16c4abf | 147 | qemu_put_be32(f, s->version_id); /* PCI device version */ |
30ca2aab | 148 | qemu_put_buffer(f, s->config, 256); |
52fc1d83 AZ |
149 | for (i = 0; i < 4; i++) |
150 | qemu_put_be32(f, s->irq_state[i]); | |
30ca2aab FB |
151 | } |
152 | ||
1941d19c | 153 | int pci_device_load(PCIDevice *s, QEMUFile *f) |
30ca2aab | 154 | { |
bd4b65ee | 155 | uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
1941d19c | 156 | uint32_t version_id; |
52fc1d83 AZ |
157 | int i; |
158 | ||
1941d19c | 159 | version_id = qemu_get_be32(f); |
52fc1d83 | 160 | if (version_id > 2) |
30ca2aab | 161 | return -EINVAL; |
bd4b65ee MT |
162 | qemu_get_buffer(f, config, sizeof config); |
163 | for (i = 0; i < sizeof config; ++i) | |
164 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) | |
165 | return -EINVAL; | |
166 | memcpy(s->config, config, sizeof config); | |
167 | ||
1941d19c | 168 | pci_update_mappings(s); |
52fc1d83 AZ |
169 | |
170 | if (version_id >= 2) | |
171 | for (i = 0; i < 4; i ++) | |
172 | s->irq_state[i] = qemu_get_be32(f); | |
30ca2aab FB |
173 | return 0; |
174 | } | |
175 | ||
d350d97d AL |
176 | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
177 | { | |
178 | uint16_t *id; | |
179 | ||
180 | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); | |
181 | id[0] = cpu_to_le16(pci_default_sub_vendor_id); | |
182 | id[1] = cpu_to_le16(pci_default_sub_device_id); | |
183 | return 0; | |
184 | } | |
185 | ||
880345c4 AL |
186 | /* |
187 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
188 | */ | |
189 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
190 | { | |
191 | const char *p; | |
192 | char *e; | |
193 | unsigned long val; | |
194 | unsigned long dom = 0, bus = 0; | |
195 | unsigned slot = 0; | |
196 | ||
197 | p = addr; | |
198 | val = strtoul(p, &e, 16); | |
199 | if (e == p) | |
200 | return -1; | |
201 | if (*e == ':') { | |
202 | bus = val; | |
203 | p = e + 1; | |
204 | val = strtoul(p, &e, 16); | |
205 | if (e == p) | |
206 | return -1; | |
207 | if (*e == ':') { | |
208 | dom = bus; | |
209 | bus = val; | |
210 | p = e + 1; | |
211 | val = strtoul(p, &e, 16); | |
212 | if (e == p) | |
213 | return -1; | |
214 | } | |
215 | } | |
216 | ||
217 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
218 | return -1; | |
219 | ||
220 | slot = val; | |
221 | ||
222 | if (*e) | |
223 | return -1; | |
224 | ||
225 | /* Note: QEMU doesn't implement domains other than 0 */ | |
226 | if (dom != 0 || pci_find_bus(bus) == NULL) | |
227 | return -1; | |
228 | ||
229 | *domp = dom; | |
230 | *busp = bus; | |
231 | *slotp = slot; | |
232 | return 0; | |
233 | } | |
234 | ||
e9283f8b JK |
235 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
236 | unsigned *slotp) | |
880345c4 | 237 | { |
e9283f8b JK |
238 | /* strip legacy tag */ |
239 | if (!strncmp(addr, "pci_addr=", 9)) { | |
240 | addr += 9; | |
241 | } | |
242 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
243 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 244 | return -1; |
e9283f8b JK |
245 | } |
246 | return 0; | |
880345c4 AL |
247 | } |
248 | ||
5607c388 MA |
249 | static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
250 | { | |
251 | int dom, bus; | |
252 | unsigned slot; | |
253 | ||
254 | if (!devaddr) { | |
255 | *devfnp = -1; | |
256 | return pci_find_bus(0); | |
257 | } | |
258 | ||
259 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
260 | return NULL; | |
261 | } | |
262 | ||
263 | *devfnp = slot << 3; | |
264 | return pci_find_bus(bus); | |
265 | } | |
266 | ||
bd4b65ee MT |
267 | static void pci_init_cmask(PCIDevice *dev) |
268 | { | |
269 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
270 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
271 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
272 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
273 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
274 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
275 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
276 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
277 | } | |
278 | ||
b7ee1603 MT |
279 | static void pci_init_wmask(PCIDevice *dev) |
280 | { | |
281 | int i; | |
282 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; | |
283 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
284 | dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
285 | | PCI_COMMAND_MASTER; | |
286 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
287 | dev->wmask[i] = 0xff; | |
288 | } | |
289 | ||
69b91039 | 290 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
291 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
292 | const char *name, int devfn, | |
293 | PCIConfigReadFunc *config_read, | |
294 | PCIConfigWriteFunc *config_write) | |
69b91039 | 295 | { |
69b91039 | 296 | if (devfn < 0) { |
30468f78 FB |
297 | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
298 | if (!bus->devices[devfn]) | |
69b91039 FB |
299 | goto found; |
300 | } | |
301 | return NULL; | |
302 | found: ; | |
07b7d053 MA |
303 | } else if (bus->devices[devfn]) { |
304 | return NULL; | |
69b91039 | 305 | } |
30468f78 | 306 | pci_dev->bus = bus; |
69b91039 FB |
307 | pci_dev->devfn = devfn; |
308 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d2b59317 | 309 | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
d350d97d | 310 | pci_set_default_subsystem_id(pci_dev); |
bd4b65ee | 311 | pci_init_cmask(pci_dev); |
b7ee1603 | 312 | pci_init_wmask(pci_dev); |
0ac32c83 FB |
313 | |
314 | if (!config_read) | |
315 | config_read = pci_default_read_config; | |
316 | if (!config_write) | |
317 | config_write = pci_default_write_config; | |
69b91039 FB |
318 | pci_dev->config_read = config_read; |
319 | pci_dev->config_write = config_write; | |
30468f78 | 320 | bus->devices[devfn] = pci_dev; |
d537cf6c | 321 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); |
f16c4abf | 322 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
323 | return pci_dev; |
324 | } | |
325 | ||
6b1b92d3 PB |
326 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
327 | int instance_size, int devfn, | |
328 | PCIConfigReadFunc *config_read, | |
329 | PCIConfigWriteFunc *config_write) | |
330 | { | |
331 | PCIDevice *pci_dev; | |
332 | ||
333 | pci_dev = qemu_mallocz(instance_size); | |
334 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
335 | config_read, config_write); | |
336 | return pci_dev; | |
337 | } | |
5851e08c AL |
338 | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
339 | { | |
340 | return addr + pci_mem_base; | |
341 | } | |
342 | ||
343 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
344 | { | |
345 | PCIIORegion *r; | |
346 | int i; | |
347 | ||
348 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
349 | r = &pci_dev->io_regions[i]; | |
350 | if (!r->size || r->addr == -1) | |
351 | continue; | |
352 | if (r->type == PCI_ADDRESS_SPACE_IO) { | |
353 | isa_unassign_ioport(r->addr, r->size); | |
354 | } else { | |
355 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), | |
356 | r->size, | |
357 | IO_MEM_UNASSIGNED); | |
358 | } | |
359 | } | |
360 | } | |
361 | ||
362 | int pci_unregister_device(PCIDevice *pci_dev) | |
363 | { | |
364 | int ret = 0; | |
365 | ||
366 | if (pci_dev->unregister) | |
367 | ret = pci_dev->unregister(pci_dev); | |
368 | if (ret) | |
369 | return ret; | |
370 | ||
371 | pci_unregister_io_regions(pci_dev); | |
372 | ||
373 | qemu_free_irqs(pci_dev->irq); | |
5851e08c | 374 | pci_dev->bus->devices[pci_dev->devfn] = NULL; |
02e2da45 | 375 | qdev_free(&pci_dev->qdev); |
5851e08c AL |
376 | return 0; |
377 | } | |
378 | ||
28c2c264 | 379 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
5fafdf24 | 380 | uint32_t size, int type, |
69b91039 FB |
381 | PCIMapIORegionFunc *map_func) |
382 | { | |
383 | PCIIORegion *r; | |
d7ce493a | 384 | uint32_t addr; |
b7ee1603 | 385 | uint32_t wmask; |
69b91039 | 386 | |
8a8696a3 | 387 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 388 | return; |
a4c20c6a AL |
389 | |
390 | if (size & (size-1)) { | |
391 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
392 | "type=0x%x, size=0x%x\n", type, size); | |
393 | exit(1); | |
394 | } | |
395 | ||
69b91039 FB |
396 | r = &pci_dev->io_regions[region_num]; |
397 | r->addr = -1; | |
398 | r->size = size; | |
399 | r->type = type; | |
400 | r->map_func = map_func; | |
b7ee1603 MT |
401 | |
402 | wmask = ~(size - 1); | |
d7ce493a PB |
403 | if (region_num == PCI_ROM_SLOT) { |
404 | addr = 0x30; | |
b7ee1603 MT |
405 | /* ROM enable bit is writeable */ |
406 | wmask |= 1; | |
d7ce493a PB |
407 | } else { |
408 | addr = 0x10 + region_num * 4; | |
409 | } | |
410 | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); | |
b7ee1603 | 411 | *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
bd4b65ee | 412 | *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff; |
69b91039 FB |
413 | } |
414 | ||
0ac32c83 FB |
415 | static void pci_update_mappings(PCIDevice *d) |
416 | { | |
417 | PCIIORegion *r; | |
418 | int cmd, i; | |
8a8696a3 | 419 | uint32_t last_addr, new_addr, config_ofs; |
3b46e624 | 420 | |
0ac32c83 | 421 | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
8a8696a3 | 422 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 423 | r = &d->io_regions[i]; |
8a8696a3 FB |
424 | if (i == PCI_ROM_SLOT) { |
425 | config_ofs = 0x30; | |
426 | } else { | |
427 | config_ofs = 0x10 + i * 4; | |
428 | } | |
0ac32c83 FB |
429 | if (r->size != 0) { |
430 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
431 | if (cmd & PCI_COMMAND_IO) { | |
5fafdf24 | 432 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 | 433 | config_ofs)); |
0ac32c83 FB |
434 | new_addr = new_addr & ~(r->size - 1); |
435 | last_addr = new_addr + r->size - 1; | |
436 | /* NOTE: we have only 64K ioports on PC */ | |
437 | if (last_addr <= new_addr || new_addr == 0 || | |
438 | last_addr >= 0x10000) { | |
439 | new_addr = -1; | |
440 | } | |
441 | } else { | |
442 | new_addr = -1; | |
443 | } | |
444 | } else { | |
445 | if (cmd & PCI_COMMAND_MEMORY) { | |
5fafdf24 | 446 | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
8a8696a3 FB |
447 | config_ofs)); |
448 | /* the ROM slot has a specific enable bit */ | |
449 | if (i == PCI_ROM_SLOT && !(new_addr & 1)) | |
450 | goto no_mem_map; | |
0ac32c83 FB |
451 | new_addr = new_addr & ~(r->size - 1); |
452 | last_addr = new_addr + r->size - 1; | |
453 | /* NOTE: we do not support wrapping */ | |
454 | /* XXX: as we cannot support really dynamic | |
455 | mappings, we handle specific values as invalid | |
456 | mappings. */ | |
457 | if (last_addr <= new_addr || new_addr == 0 || | |
458 | last_addr == -1) { | |
459 | new_addr = -1; | |
460 | } | |
461 | } else { | |
8a8696a3 | 462 | no_mem_map: |
0ac32c83 FB |
463 | new_addr = -1; |
464 | } | |
465 | } | |
466 | /* now do the real mapping */ | |
467 | if (new_addr != r->addr) { | |
468 | if (r->addr != -1) { | |
469 | if (r->type & PCI_ADDRESS_SPACE_IO) { | |
470 | int class; | |
471 | /* NOTE: specific hack for IDE in PC case: | |
472 | only one byte must be mapped. */ | |
473 | class = d->config[0x0a] | (d->config[0x0b] << 8); | |
474 | if (class == 0x0101 && r->size == 4) { | |
475 | isa_unassign_ioport(r->addr + 2, 1); | |
476 | } else { | |
477 | isa_unassign_ioport(r->addr, r->size); | |
478 | } | |
479 | } else { | |
502a5395 | 480 | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
5fafdf24 | 481 | r->size, |
0ac32c83 | 482 | IO_MEM_UNASSIGNED); |
f65ed4c1 | 483 | qemu_unregister_coalesced_mmio(r->addr, r->size); |
0ac32c83 FB |
484 | } |
485 | } | |
486 | r->addr = new_addr; | |
487 | if (r->addr != -1) { | |
488 | r->map_func(d, i, r->addr, r->size, r->type); | |
489 | } | |
490 | } | |
491 | } | |
492 | } | |
493 | } | |
494 | ||
5fafdf24 | 495 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 496 | uint32_t address, int len) |
69b91039 | 497 | { |
0ac32c83 | 498 | uint32_t val; |
a2d4e44b | 499 | |
0ac32c83 | 500 | switch(len) { |
0ac32c83 FB |
501 | default: |
502 | case 4: | |
a2d4e44b TS |
503 | if (address <= 0xfc) { |
504 | val = le32_to_cpu(*(uint32_t *)(d->config + address)); | |
505 | break; | |
506 | } | |
507 | /* fall through */ | |
508 | case 2: | |
509 | if (address <= 0xfe) { | |
510 | val = le16_to_cpu(*(uint16_t *)(d->config + address)); | |
511 | break; | |
512 | } | |
513 | /* fall through */ | |
514 | case 1: | |
515 | val = d->config[address]; | |
0ac32c83 FB |
516 | break; |
517 | } | |
518 | return val; | |
519 | } | |
520 | ||
b7ee1603 | 521 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 522 | { |
b7ee1603 MT |
523 | uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
524 | int i; | |
0ac32c83 | 525 | |
0ac32c83 | 526 | /* not efficient, but simple */ |
b7ee1603 MT |
527 | memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
528 | for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { | |
529 | uint8_t wmask = d->wmask[addr]; | |
530 | d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); | |
0ac32c83 | 531 | } |
b7ee1603 MT |
532 | if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
533 | || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) | |
534 | & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) | |
0ac32c83 | 535 | pci_update_mappings(d); |
69b91039 FB |
536 | } |
537 | ||
502a5395 | 538 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
69b91039 | 539 | { |
30468f78 FB |
540 | PCIBus *s = opaque; |
541 | PCIDevice *pci_dev; | |
542 | int config_addr, bus_num; | |
3b46e624 | 543 | |
d8d2e079 IY |
544 | #if 0 |
545 | PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n", | |
546 | addr, val, len); | |
69b91039 | 547 | #endif |
502a5395 | 548 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
549 | while (s && s->bus_num != bus_num) |
550 | s = s->next; | |
551 | if (!s) | |
69b91039 | 552 | return; |
502a5395 | 553 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
554 | if (!pci_dev) |
555 | return; | |
502a5395 | 556 | config_addr = addr & 0xff; |
d8d2e079 IY |
557 | PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n", |
558 | pci_dev->name, config_addr, val, len); | |
0ac32c83 | 559 | pci_dev->config_write(pci_dev, config_addr, val, len); |
69b91039 FB |
560 | } |
561 | ||
502a5395 | 562 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
69b91039 | 563 | { |
30468f78 FB |
564 | PCIBus *s = opaque; |
565 | PCIDevice *pci_dev; | |
566 | int config_addr, bus_num; | |
69b91039 FB |
567 | uint32_t val; |
568 | ||
502a5395 | 569 | bus_num = (addr >> 16) & 0xff; |
80b3ada7 PB |
570 | while (s && s->bus_num != bus_num) |
571 | s= s->next; | |
572 | if (!s) | |
69b91039 | 573 | goto fail; |
502a5395 | 574 | pci_dev = s->devices[(addr >> 8) & 0xff]; |
69b91039 FB |
575 | if (!pci_dev) { |
576 | fail: | |
63ce9e0a FB |
577 | switch(len) { |
578 | case 1: | |
579 | val = 0xff; | |
580 | break; | |
581 | case 2: | |
582 | val = 0xffff; | |
583 | break; | |
584 | default: | |
585 | case 4: | |
586 | val = 0xffffffff; | |
587 | break; | |
588 | } | |
69b91039 FB |
589 | goto the_end; |
590 | } | |
502a5395 | 591 | config_addr = addr & 0xff; |
69b91039 | 592 | val = pci_dev->config_read(pci_dev, config_addr, len); |
d8d2e079 IY |
593 | PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n", |
594 | pci_dev->name, config_addr, val, len); | |
69b91039 | 595 | the_end: |
d8d2e079 IY |
596 | #if 0 |
597 | PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n", | |
598 | addr, val, len); | |
69b91039 FB |
599 | #endif |
600 | return val; | |
601 | } | |
602 | ||
502a5395 PB |
603 | /***********************************************************/ |
604 | /* generic PCI irq support */ | |
30468f78 | 605 | |
502a5395 | 606 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 607 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 608 | { |
d537cf6c | 609 | PCIDevice *pci_dev = (PCIDevice *)opaque; |
80b3ada7 PB |
610 | PCIBus *bus; |
611 | int change; | |
3b46e624 | 612 | |
80b3ada7 PB |
613 | change = level - pci_dev->irq_state[irq_num]; |
614 | if (!change) | |
615 | return; | |
d2b59317 | 616 | |
d2b59317 | 617 | pci_dev->irq_state[irq_num] = level; |
5e966ce6 PB |
618 | for (;;) { |
619 | bus = pci_dev->bus; | |
80b3ada7 | 620 | irq_num = bus->map_irq(pci_dev, irq_num); |
5e966ce6 PB |
621 | if (bus->set_irq) |
622 | break; | |
80b3ada7 | 623 | pci_dev = bus->parent_dev; |
80b3ada7 PB |
624 | } |
625 | bus->irq_count[irq_num] += change; | |
d2b59317 | 626 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
69b91039 FB |
627 | } |
628 | ||
502a5395 PB |
629 | /***********************************************************/ |
630 | /* monitor info on PCI */ | |
0ac32c83 | 631 | |
6650ee6d PB |
632 | typedef struct { |
633 | uint16_t class; | |
634 | const char *desc; | |
635 | } pci_class_desc; | |
636 | ||
09bc878a | 637 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 638 | { |
4ca9c76f | 639 | { 0x0100, "SCSI controller"}, |
6650ee6d | 640 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
641 | { 0x0102, "Floppy controller"}, |
642 | { 0x0103, "IPI controller"}, | |
643 | { 0x0104, "RAID controller"}, | |
644 | { 0x0106, "SATA controller"}, | |
645 | { 0x0107, "SAS controller"}, | |
646 | { 0x0180, "Storage controller"}, | |
6650ee6d | 647 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
648 | { 0x0201, "Token Ring controller"}, |
649 | { 0x0202, "FDDI controller"}, | |
650 | { 0x0203, "ATM controller"}, | |
651 | { 0x0280, "Network controller"}, | |
6650ee6d | 652 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
653 | { 0x0301, "XGA controller"}, |
654 | { 0x0302, "3D controller"}, | |
655 | { 0x0380, "Display controller"}, | |
656 | { 0x0400, "Video controller"}, | |
657 | { 0x0401, "Audio controller"}, | |
658 | { 0x0402, "Phone"}, | |
659 | { 0x0480, "Multimedia controller"}, | |
660 | { 0x0500, "RAM controller"}, | |
661 | { 0x0501, "Flash controller"}, | |
662 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
663 | { 0x0600, "Host bridge"}, |
664 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
665 | { 0x0602, "EISA bridge"}, |
666 | { 0x0603, "MC bridge"}, | |
6650ee6d | 667 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
668 | { 0x0605, "PCMCIA bridge"}, |
669 | { 0x0606, "NUBUS bridge"}, | |
670 | { 0x0607, "CARDBUS bridge"}, | |
671 | { 0x0608, "RACEWAY bridge"}, | |
672 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
673 | { 0x0c03, "USB controller"}, |
674 | { 0, NULL} | |
675 | }; | |
676 | ||
502a5395 | 677 | static void pci_info_device(PCIDevice *d) |
30468f78 | 678 | { |
376253ec | 679 | Monitor *mon = cur_mon; |
502a5395 PB |
680 | int i, class; |
681 | PCIIORegion *r; | |
09bc878a | 682 | const pci_class_desc *desc; |
30468f78 | 683 | |
376253ec AL |
684 | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", |
685 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); | |
502a5395 | 686 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
376253ec | 687 | monitor_printf(mon, " "); |
6650ee6d PB |
688 | desc = pci_class_descriptions; |
689 | while (desc->desc && class != desc->class) | |
690 | desc++; | |
691 | if (desc->desc) { | |
376253ec | 692 | monitor_printf(mon, "%s", desc->desc); |
6650ee6d | 693 | } else { |
376253ec | 694 | monitor_printf(mon, "Class %04x", class); |
72cc6cfe | 695 | } |
376253ec | 696 | monitor_printf(mon, ": PCI device %04x:%04x\n", |
502a5395 PB |
697 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
698 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); | |
30468f78 | 699 | |
502a5395 | 700 | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
376253ec AL |
701 | monitor_printf(mon, " IRQ %d.\n", |
702 | d->config[PCI_INTERRUPT_LINE]); | |
30468f78 | 703 | } |
80b3ada7 | 704 | if (class == 0x0604) { |
376253ec | 705 | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
80b3ada7 | 706 | } |
502a5395 PB |
707 | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
708 | r = &d->io_regions[i]; | |
709 | if (r->size != 0) { | |
376253ec | 710 | monitor_printf(mon, " BAR%d: ", i); |
502a5395 | 711 | if (r->type & PCI_ADDRESS_SPACE_IO) { |
376253ec AL |
712 | monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n", |
713 | r->addr, r->addr + r->size - 1); | |
502a5395 | 714 | } else { |
376253ec AL |
715 | monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n", |
716 | r->addr, r->addr + r->size - 1); | |
502a5395 PB |
717 | } |
718 | } | |
77d4bc34 | 719 | } |
8ad12514 | 720 | monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
80b3ada7 PB |
721 | if (class == 0x0604 && d->config[0x19] != 0) { |
722 | pci_for_each_device(d->config[0x19], pci_info_device); | |
723 | } | |
384d8876 FB |
724 | } |
725 | ||
80b3ada7 | 726 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
384d8876 | 727 | { |
502a5395 | 728 | PCIBus *bus = first_bus; |
384d8876 | 729 | PCIDevice *d; |
502a5395 | 730 | int devfn; |
3b46e624 | 731 | |
80b3ada7 PB |
732 | while (bus && bus->bus_num != bus_num) |
733 | bus = bus->next; | |
502a5395 PB |
734 | if (bus) { |
735 | for(devfn = 0; devfn < 256; devfn++) { | |
736 | d = bus->devices[devfn]; | |
737 | if (d) | |
738 | fn(d); | |
739 | } | |
f2aa58c6 | 740 | } |
f2aa58c6 FB |
741 | } |
742 | ||
376253ec | 743 | void pci_info(Monitor *mon) |
f2aa58c6 | 744 | { |
80b3ada7 | 745 | pci_for_each_device(0, pci_info_device); |
77d4bc34 | 746 | } |
a41b2ff2 | 747 | |
1f5f6638 | 748 | PCIDevice *pci_create(const char *name, const char *devaddr) |
5607c388 MA |
749 | { |
750 | PCIBus *bus; | |
751 | int devfn; | |
752 | DeviceState *dev; | |
753 | ||
754 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
755 | if (!bus) { | |
756 | fprintf(stderr, "Invalid PCI device address %s for device %s\n", | |
757 | devaddr, name); | |
758 | exit(1); | |
759 | } | |
760 | ||
761 | dev = qdev_create(&bus->qbus, name); | |
a6307b08 | 762 | qdev_prop_set_uint32(dev, "addr", devfn); |
5607c388 MA |
763 | return (PCIDevice *)dev; |
764 | } | |
765 | ||
cb457d76 AL |
766 | static const char * const pci_nic_models[] = { |
767 | "ne2k_pci", | |
768 | "i82551", | |
769 | "i82557b", | |
770 | "i82559er", | |
771 | "rtl8139", | |
772 | "e1000", | |
773 | "pcnet", | |
774 | "virtio", | |
775 | NULL | |
776 | }; | |
777 | ||
9d07d757 PB |
778 | static const char * const pci_nic_names[] = { |
779 | "ne2k_pci", | |
780 | "i82551", | |
781 | "i82557b", | |
782 | "i82559er", | |
783 | "rtl8139", | |
784 | "e1000", | |
785 | "pcnet", | |
53c25cea | 786 | "virtio-net-pci", |
cb457d76 AL |
787 | NULL |
788 | }; | |
789 | ||
a41b2ff2 | 790 | /* Initialize a PCI NIC. */ |
5607c388 MA |
791 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
792 | const char *default_devaddr) | |
a41b2ff2 | 793 | { |
5607c388 MA |
794 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
795 | PCIDevice *pci_dev; | |
9d07d757 | 796 | DeviceState *dev; |
cb457d76 AL |
797 | int i; |
798 | ||
799 | qemu_check_nic_model_list(nd, pci_nic_models, default_model); | |
800 | ||
9d07d757 | 801 | for (i = 0; pci_nic_models[i]; i++) { |
72da4208 | 802 | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
5607c388 MA |
803 | pci_dev = pci_create(pci_nic_names[i], devaddr); |
804 | dev = &pci_dev->qdev; | |
eb54b6dc GH |
805 | if (nd->id) |
806 | dev->id = qemu_strdup(nd->id); | |
ee6847d1 | 807 | dev->nd = nd; |
9d07d757 PB |
808 | qdev_init(dev); |
809 | nd->private = dev; | |
5607c388 | 810 | return pci_dev; |
72da4208 | 811 | } |
9d07d757 | 812 | } |
72da4208 AL |
813 | |
814 | return NULL; | |
a41b2ff2 PB |
815 | } |
816 | ||
80b3ada7 PB |
817 | typedef struct { |
818 | PCIDevice dev; | |
819 | PCIBus *bus; | |
820 | } PCIBridge; | |
821 | ||
9596ebb7 | 822 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
823 | uint32_t address, uint32_t val, int len) |
824 | { | |
825 | PCIBridge *s = (PCIBridge *)d; | |
826 | ||
80b3ada7 | 827 | pci_default_write_config(d, address, val, len); |
b7ee1603 | 828 | s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; |
80b3ada7 PB |
829 | } |
830 | ||
3ae80618 AL |
831 | PCIBus *pci_find_bus(int bus_num) |
832 | { | |
833 | PCIBus *bus = first_bus; | |
834 | ||
835 | while (bus && bus->bus_num != bus_num) | |
836 | bus = bus->next; | |
837 | ||
838 | return bus; | |
839 | } | |
840 | ||
841 | PCIDevice *pci_find_device(int bus_num, int slot, int function) | |
842 | { | |
843 | PCIBus *bus = pci_find_bus(bus_num); | |
844 | ||
845 | if (!bus) | |
846 | return NULL; | |
847 | ||
848 | return bus->devices[PCI_DEVFN(slot, function)]; | |
849 | } | |
850 | ||
480b9f24 | 851 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
80b3ada7 PB |
852 | pci_map_irq_fn map_irq, const char *name) |
853 | { | |
854 | PCIBridge *s; | |
5fafdf24 | 855 | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), |
80b3ada7 | 856 | devfn, NULL, pci_bridge_write_config); |
480b9f24 BS |
857 | |
858 | pci_config_set_vendor_id(s->dev.config, vid); | |
859 | pci_config_set_device_id(s->dev.config, did); | |
860 | ||
80b3ada7 PB |
861 | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
862 | s->dev.config[0x05] = 0x00; | |
863 | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
864 | s->dev.config[0x07] = 0x00; // status = fast devsel | |
865 | s->dev.config[0x08] = 0x00; // revision | |
866 | s->dev.config[0x09] = 0x00; // programming i/f | |
173a543b | 867 | pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
80b3ada7 | 868 | s->dev.config[0x0D] = 0x10; // latency_timer |
6407f373 IY |
869 | s->dev.config[PCI_HEADER_TYPE] = |
870 | PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type | |
80b3ada7 PB |
871 | s->dev.config[0x1E] = 0xa0; // secondary status |
872 | ||
72f44c8c | 873 | s->bus = pci_register_secondary_bus(&s->dev, map_irq, name); |
80b3ada7 PB |
874 | return s->bus; |
875 | } | |
6b1b92d3 | 876 | |
02e2da45 | 877 | static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
878 | { |
879 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 880 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 PB |
881 | PCIBus *bus; |
882 | int devfn; | |
883 | ||
02e2da45 | 884 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 885 | devfn = pci_dev->devfn; |
16eaedf2 | 886 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
0aab0d3a | 887 | info->config_read, info->config_write); |
6b1b92d3 | 888 | assert(pci_dev); |
02e2da45 | 889 | info->init(pci_dev); |
6b1b92d3 PB |
890 | } |
891 | ||
0aab0d3a | 892 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 893 | { |
02e2da45 | 894 | info->qdev.init = pci_qdev_init; |
10c4c98a | 895 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 896 | qdev_register(&info->qdev); |
6b1b92d3 PB |
897 | } |
898 | ||
0aab0d3a GH |
899 | void pci_qdev_register_many(PCIDeviceInfo *info) |
900 | { | |
901 | while (info->qdev.name) { | |
902 | pci_qdev_register(info); | |
903 | info++; | |
904 | } | |
905 | } | |
906 | ||
6b1b92d3 PB |
907 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
908 | { | |
909 | DeviceState *dev; | |
910 | ||
02e2da45 | 911 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 912 | qdev_prop_set_uint32(dev, "addr", devfn); |
6b1b92d3 PB |
913 | qdev_init(dev); |
914 | ||
915 | return (PCIDevice *)dev; | |
916 | } | |
6f4cbd39 MT |
917 | |
918 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
919 | { | |
920 | int offset = PCI_CONFIG_HEADER_SIZE; | |
921 | int i; | |
922 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) | |
923 | if (pdev->used[i]) | |
924 | offset = i + 1; | |
925 | else if (i - offset + 1 == size) | |
926 | return offset; | |
927 | return 0; | |
928 | } | |
929 | ||
930 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
931 | uint8_t *prev_p) | |
932 | { | |
933 | uint8_t next, prev; | |
934 | ||
935 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
936 | return 0; | |
937 | ||
938 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
939 | prev = next + PCI_CAP_LIST_NEXT) | |
940 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
941 | break; | |
942 | ||
943 | if (prev_p) | |
944 | *prev_p = prev; | |
945 | return next; | |
946 | } | |
947 | ||
948 | /* Reserve space and add capability to the linked list in pci config space */ | |
949 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
950 | { | |
951 | uint8_t offset = pci_find_space(pdev, size); | |
952 | uint8_t *config = pdev->config + offset; | |
953 | if (!offset) | |
954 | return -ENOSPC; | |
955 | config[PCI_CAP_LIST_ID] = cap_id; | |
956 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
957 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
958 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
959 | memset(pdev->used + offset, 0xFF, size); | |
960 | /* Make capability read-only by default */ | |
961 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
962 | /* Check capability by default */ |
963 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
964 | return offset; |
965 | } | |
966 | ||
967 | /* Unlink capability from the pci config space. */ | |
968 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
969 | { | |
970 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
971 | if (!offset) | |
972 | return; | |
973 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
974 | /* Make capability writeable again */ | |
975 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
976 | /* Clear cmask as device-specific registers can't be checked */ |
977 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
978 | memset(pdev->used + offset, 0, size); |
979 | ||
980 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
981 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
982 | } | |
983 | ||
984 | /* Reserve space for capability at a known offset (to call after load). */ | |
985 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
986 | { | |
987 | memset(pdev->used + offset, 0xff, size); | |
988 | } | |
989 | ||
990 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
991 | { | |
992 | return pci_find_capability_list(pdev, cap_id, NULL); | |
993 | } | |
10c4c98a GH |
994 | |
995 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
996 | { | |
997 | PCIDevice *d = (PCIDevice *)dev; | |
998 | const pci_class_desc *desc; | |
999 | char ctxt[64]; | |
1000 | PCIIORegion *r; | |
1001 | int i, class; | |
1002 | ||
1003 | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); | |
1004 | desc = pci_class_descriptions; | |
1005 | while (desc->desc && class != desc->class) | |
1006 | desc++; | |
1007 | if (desc->desc) { | |
1008 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1009 | } else { | |
1010 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1011 | } | |
1012 | ||
1013 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1014 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1015 | indent, "", ctxt, | |
1016 | d->bus->bus_num, d->devfn >> 3, d->devfn & 7, | |
1017 | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), | |
1018 | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))), | |
1019 | le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))), | |
1020 | le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID)))); | |
1021 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1022 | r = &d->io_regions[i]; | |
1023 | if (!r->size) | |
1024 | continue; | |
1025 | monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", | |
1026 | i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem", | |
1027 | r->addr, r->addr + r->size - 1); | |
1028 | } | |
1029 | } |