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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec | 4 | #include "qemu-common.h" |
163c8a59 | 5 | #include "qobject.h" |
376253ec | 6 | |
6b1b92d3 PB |
7 | #include "qdev.h" |
8 | ||
87ecb68b PB |
9 | /* PCI includes legacy ISA access. */ |
10 | #include "isa.h" | |
11 | ||
12 | /* PCI bus */ | |
13 | ||
3ae80618 AL |
14 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
15 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
16 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
17 | ||
a770dc7e AL |
18 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
19 | #include "pci_ids.h" | |
173a543b | 20 | |
a770dc7e | 21 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 22 | |
a770dc7e AL |
23 | /* IBM (0x1014) */ |
24 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 25 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 26 | |
a770dc7e | 27 | /* Hitachi (0x1054) */ |
deb54399 | 28 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 29 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 30 | |
a770dc7e | 31 | /* Apple (0x106b) */ |
4ebcf884 BS |
32 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
33 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
34 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 35 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 36 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 37 | |
a770dc7e AL |
38 | /* Realtek (0x10ec) */ |
39 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 40 | |
a770dc7e AL |
41 | /* Xilinx (0x10ee) */ |
42 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 43 | |
a770dc7e AL |
44 | /* Marvell (0x11ab) */ |
45 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 46 | |
a770dc7e | 47 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
48 | #define PCI_VENDOR_ID_QEMU 0x1234 |
49 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
50 | ||
a770dc7e | 51 | /* VMWare (0x15ad) */ |
deb54399 AL |
52 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
53 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
54 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
55 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
56 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
57 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
58 | ||
cef3017c | 59 | /* Intel (0x8086) */ |
a770dc7e | 60 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 61 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
74c62ba8 | 62 | |
deb54399 | 63 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
64 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
65 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
66 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
67 | ||
68 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
69 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
70 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 71 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
d350d97d | 72 | |
4f8589e1 | 73 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 74 | |
87ecb68b PB |
75 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
76 | uint32_t address, uint32_t data, int len); | |
77 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
78 | uint32_t address, int len); | |
79 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 80 | pcibus_t addr, pcibus_t size, int type); |
5851e08c | 81 | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 82 | |
87ecb68b | 83 | typedef struct PCIIORegion { |
6e355d90 IY |
84 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
85 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
86 | pcibus_t size; | |
a0c7a97e | 87 | pcibus_t filtered_size; |
87ecb68b PB |
88 | uint8_t type; |
89 | PCIMapIORegionFunc *map_func; | |
90 | } PCIIORegion; | |
91 | ||
92 | #define PCI_ROM_SLOT 6 | |
93 | #define PCI_NUM_REGIONS 7 | |
94 | ||
fb58a897 IY |
95 | #include "pci_regs.h" |
96 | ||
97 | /* PCI HEADER_TYPE */ | |
6407f373 | 98 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 AJ |
99 | |
100 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ | |
101 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ | |
102 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) | |
103 | ||
104 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) | |
105 | ||
475dc65f AJ |
106 | /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
107 | #define PCI_COMMAND_RESERVED 0xf800 | |
108 | ||
109 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) | |
110 | ||
b7ee1603 MT |
111 | /* Size of the standard PCI config header */ |
112 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
113 | /* Size of the standard PCI config space */ | |
114 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
115 | /* Size of the standart PCIe config space: 4KB */ |
116 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 117 | |
e369cad7 IY |
118 | #define PCI_NUM_PINS 4 /* A-D */ |
119 | ||
02eb84d0 MT |
120 | /* Bits in cap_present field. */ |
121 | enum { | |
122 | QEMU_PCI_CAP_MSIX = 0x1, | |
a9f49946 | 123 | QEMU_PCI_CAP_EXPRESS = 0x2, |
02eb84d0 MT |
124 | }; |
125 | ||
87ecb68b | 126 | struct PCIDevice { |
6b1b92d3 | 127 | DeviceState qdev; |
87ecb68b | 128 | /* PCI config space */ |
a9f49946 | 129 | uint8_t *config; |
b7ee1603 | 130 | |
bd4b65ee MT |
131 | /* Used to enable config checks on load. Note that writeable bits are |
132 | * never checked even if set in cmask. */ | |
a9f49946 | 133 | uint8_t *cmask; |
bd4b65ee | 134 | |
b7ee1603 | 135 | /* Used to implement R/W bytes */ |
a9f49946 | 136 | uint8_t *wmask; |
87ecb68b | 137 | |
6f4cbd39 | 138 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 139 | uint8_t *used; |
6f4cbd39 | 140 | |
87ecb68b PB |
141 | /* the following fields are read only */ |
142 | PCIBus *bus; | |
54586bd1 | 143 | uint32_t devfn; |
87ecb68b PB |
144 | char name[64]; |
145 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
146 | ||
147 | /* do not access the following fields */ | |
148 | PCIConfigReadFunc *config_read; | |
149 | PCIConfigWriteFunc *config_write; | |
87ecb68b PB |
150 | |
151 | /* IRQ objects for the INTA-INTD pins. */ | |
152 | qemu_irq *irq; | |
153 | ||
154 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
d036bb21 | 155 | uint8_t irq_state; |
02eb84d0 MT |
156 | |
157 | /* Capability bits */ | |
158 | uint32_t cap_present; | |
159 | ||
160 | /* Offset of MSI-X capability in config space */ | |
161 | uint8_t msix_cap; | |
162 | ||
163 | /* MSI-X entries */ | |
164 | int msix_entries_nr; | |
165 | ||
166 | /* Space to store MSIX table */ | |
167 | uint8_t *msix_table_page; | |
168 | /* MMIO index used to map MSIX table and pending bit entries. */ | |
169 | int msix_mmio_index; | |
170 | /* Reference-count for entries actually in use by driver. */ | |
171 | unsigned *msix_entry_used; | |
172 | /* Region including the MSI-X table */ | |
173 | uint32_t msix_bar_size; | |
f16c4abf JQ |
174 | /* Version id needed for VMState */ |
175 | int32_t version_id; | |
c2039bd0 AL |
176 | |
177 | /* Location of option rom */ | |
8c52c8f3 | 178 | char *romfile; |
c2039bd0 | 179 | ram_addr_t rom_offset; |
88169ddf | 180 | uint32_t rom_bar; |
87ecb68b PB |
181 | }; |
182 | ||
183 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
184 | int instance_size, int devfn, | |
185 | PCIConfigReadFunc *config_read, | |
186 | PCIConfigWriteFunc *config_write); | |
187 | ||
28c2c264 | 188 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 189 | pcibus_t size, int type, |
87ecb68b PB |
190 | PCIMapIORegionFunc *map_func); |
191 | ||
6f4cbd39 MT |
192 | int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); |
193 | ||
194 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
195 | ||
196 | void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size); | |
197 | ||
198 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); | |
199 | ||
200 | ||
87ecb68b PB |
201 | uint32_t pci_default_read_config(PCIDevice *d, |
202 | uint32_t address, int len); | |
203 | void pci_default_write_config(PCIDevice *d, | |
204 | uint32_t address, uint32_t val, int len); | |
205 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
206 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
207 | ||
5d4e84c8 | 208 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 209 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
ee995ffb | 210 | typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state); |
21eea4b3 GH |
211 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
212 | const char *name, int devfn_min); | |
213 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min); | |
214 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
215 | void *irq_opaque, int nirq); | |
ee995ffb | 216 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug); |
02e2da45 PB |
217 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
218 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
5d4e84c8 | 219 | void *irq_opaque, int devfn_min, int nirq); |
87ecb68b | 220 | |
2e01c8cf BS |
221 | void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base); |
222 | ||
5607c388 MA |
223 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
224 | const char *default_devaddr); | |
07caea31 MA |
225 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
226 | const char *default_devaddr); | |
87ecb68b | 227 | int pci_bus_num(PCIBus *s); |
e822a52a | 228 | void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
c469e1dd | 229 | PCIBus *pci_find_root_bus(int domain); |
e822a52a IY |
230 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num); |
231 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function); | |
49bd1458 | 232 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
87ecb68b | 233 | |
e9283f8b JK |
234 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
235 | unsigned *slotp); | |
880345c4 | 236 | |
163c8a59 LC |
237 | void do_pci_info_print(Monitor *mon, const QObject *data); |
238 | void do_pci_info(Monitor *mon, QObject **ret_data); | |
480b9f24 | 239 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
87ecb68b | 240 | pci_map_irq_fn map_irq, const char *name); |
d6318738 | 241 | PCIDevice *pci_bridge_get_device(PCIBus *bus); |
87ecb68b | 242 | |
64d50b8b MT |
243 | static inline void |
244 | pci_set_byte(uint8_t *config, uint8_t val) | |
245 | { | |
246 | *config = val; | |
247 | } | |
248 | ||
249 | static inline uint8_t | |
cb95c2e4 | 250 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
251 | { |
252 | return *config; | |
253 | } | |
254 | ||
14e12559 MT |
255 | static inline void |
256 | pci_set_word(uint8_t *config, uint16_t val) | |
257 | { | |
258 | cpu_to_le16wu((uint16_t *)config, val); | |
259 | } | |
260 | ||
261 | static inline uint16_t | |
cb95c2e4 | 262 | pci_get_word(const uint8_t *config) |
14e12559 | 263 | { |
cb95c2e4 | 264 | return le16_to_cpupu((const uint16_t *)config); |
14e12559 MT |
265 | } |
266 | ||
267 | static inline void | |
268 | pci_set_long(uint8_t *config, uint32_t val) | |
269 | { | |
270 | cpu_to_le32wu((uint32_t *)config, val); | |
271 | } | |
272 | ||
273 | static inline uint32_t | |
cb95c2e4 | 274 | pci_get_long(const uint8_t *config) |
14e12559 | 275 | { |
cb95c2e4 | 276 | return le32_to_cpupu((const uint32_t *)config); |
14e12559 MT |
277 | } |
278 | ||
fb5ce7d2 IY |
279 | static inline void |
280 | pci_set_quad(uint8_t *config, uint64_t val) | |
281 | { | |
282 | cpu_to_le64w((uint64_t *)config, val); | |
283 | } | |
284 | ||
285 | static inline uint64_t | |
cb95c2e4 | 286 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 287 | { |
cb95c2e4 | 288 | return le64_to_cpup((const uint64_t *)config); |
fb5ce7d2 IY |
289 | } |
290 | ||
deb54399 AL |
291 | static inline void |
292 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
293 | { | |
14e12559 | 294 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
295 | } |
296 | ||
297 | static inline void | |
298 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
299 | { | |
14e12559 | 300 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
301 | } |
302 | ||
cf602c7b IE |
303 | static inline void |
304 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
305 | { | |
306 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
307 | } | |
308 | ||
173a543b BS |
309 | static inline void |
310 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
311 | { | |
14e12559 | 312 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
313 | } |
314 | ||
cf602c7b IE |
315 | static inline void |
316 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
317 | { | |
318 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
319 | } | |
320 | ||
321 | static inline void | |
322 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
323 | { | |
324 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
325 | } | |
326 | ||
81a322d4 | 327 | typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
0aab0d3a GH |
328 | typedef struct { |
329 | DeviceInfo qdev; | |
330 | pci_qdev_initfn init; | |
e3936fa5 | 331 | PCIUnregisterFunc *exit; |
0aab0d3a GH |
332 | PCIConfigReadFunc *config_read; |
333 | PCIConfigWriteFunc *config_write; | |
a9f49946 | 334 | |
fb231628 | 335 | /* pci config header type */ |
3c217c14 | 336 | uint8_t header_type; |
fb231628 | 337 | |
a9f49946 | 338 | /* pcie stuff */ |
3c217c14 | 339 | int is_express; /* is this device pci express? */ |
8c52c8f3 GH |
340 | |
341 | /* rom bar */ | |
342 | const char *romfile; | |
0aab0d3a GH |
343 | } PCIDeviceInfo; |
344 | ||
345 | void pci_qdev_register(PCIDeviceInfo *info); | |
346 | void pci_qdev_register_many(PCIDeviceInfo *info); | |
6b1b92d3 | 347 | |
499cf102 | 348 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
349 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
350 | ||
a9f49946 IY |
351 | static inline int pci_is_express(PCIDevice *d) |
352 | { | |
353 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
354 | } | |
355 | ||
356 | static inline uint32_t pci_config_size(PCIDevice *d) | |
357 | { | |
358 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
359 | } | |
360 | ||
f49db805 IY |
361 | /* These are not pci specific. Should move into a separate header. |
362 | * Only pci.c uses them, so keep them here for now. | |
363 | */ | |
364 | ||
365 | /* Get last byte of a range from offset + length. | |
366 | * Undefined for ranges that wrap around 0. */ | |
367 | static inline uint64_t range_get_last(uint64_t offset, uint64_t len) | |
368 | { | |
369 | return offset + len - 1; | |
370 | } | |
371 | ||
372 | /* Check whether a given range covers a given byte. */ | |
373 | static inline int range_covers_byte(uint64_t offset, uint64_t len, | |
374 | uint64_t byte) | |
375 | { | |
376 | return offset <= byte && byte <= range_get_last(offset, len); | |
377 | } | |
378 | ||
379 | /* Check whether 2 given ranges overlap. | |
380 | * Undefined if ranges that wrap around 0. */ | |
381 | static inline int ranges_overlap(uint64_t first1, uint64_t len1, | |
382 | uint64_t first2, uint64_t len2) | |
383 | { | |
384 | uint64_t last1 = range_get_last(first1, len1); | |
385 | uint64_t last2 = range_get_last(first2, len2); | |
386 | ||
387 | return !(last2 < first1 || last1 < first2); | |
388 | } | |
389 | ||
87ecb68b | 390 | #endif |