[qemu.git] / hw / pci.h

#ifndef QEMU_PCI_H
#define QEMU_PCI_H

/* PCI includes legacy ISA access.  */
#include "isa.h"

/* PCI bus */

extern target_phys_addr_t pci_mem_base;

/* see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
#define PCI_SUBDEVICE_ID_QEMU            0x1100

#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002

typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
                                uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
                                   uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
                                uint32_t addr, uint32_t size, int type);

#define PCI_ADDRESS_SPACE_MEM		0x00
#define PCI_ADDRESS_SPACE_IO		0x01
#define PCI_ADDRESS_SPACE_MEM_PREFETCH	0x08

typedef struct PCIIORegion {
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
    uint32_t size;
    uint8_t type;
    PCIMapIORegionFunc *map_func;
} PCIIORegion;

#define PCI_ROM_SLOT 6
#define PCI_NUM_REGIONS 7

#define PCI_DEVICES_MAX 64

#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define PCI_REVISION            0x08
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
#define PCI_SUBVENDOR_ID	0x2c	/* 16 bits */
#define PCI_SUBDEVICE_ID	0x2e	/* 16 bits */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

struct PCIDevice {
    /* PCI config space */
    uint8_t config[256];

    /* the following fields are read only */
    PCIBus *bus;
    int devfn;
    char name[64];
    PCIIORegion io_regions[PCI_NUM_REGIONS];

    /* do not access the following fields */
    PCIConfigReadFunc *config_read;
    PCIConfigWriteFunc *config_write;
    /* ??? This is a PC-specific hack, and should be removed.  */
    int irq_index;

    /* IRQ objects for the INTA-INTD pins.  */
    qemu_irq *irq;

    /* Current IRQ levels.  Used internally by the generic PCI code.  */
    int irq_state[4];
};

PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                               int instance_size, int devfn,
                               PCIConfigReadFunc *config_read,
                               PCIConfigWriteFunc *config_write);

void pci_register_io_region(PCIDevice *pci_dev, int region_num,
                            uint32_t size, int type,
                            PCIMapIORegionFunc *map_func);

uint32_t pci_default_read_config(PCIDevice *d,
                                 uint32_t address, int len);
void pci_default_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);

typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                         qemu_irq *pic, int devfn_min, int nirq);

void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
int pci_bus_num(PCIBus *s);
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));

void pci_info(void);
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
                        pci_map_irq_fn map_irq, const char *name);

/* lsi53c895a.c */
#define LSI_MAX_DEVS 7
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *lsi_scsi_init(PCIBus *bus, int devfn);

/* vmware_vga.c */
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                     unsigned long vga_ram_offset, int vga_ram_size);

/* usb-uhci.c */
void usb_uhci_piix3_init(PCIBus *bus, int devfn);
void usb_uhci_piix4_init(PCIBus *bus, int devfn);

/* usb-ohci.c */
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);

/* eepro100.c */

void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);

/* ne2000.c */

void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* rtl8139.c */

void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);

/* e1000.c */
void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* pcnet.c */
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

/* prep_pci.c */
PCIBus *pci_prep_init(qemu_irq *pic);

/* apb_pci.c */
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
                     qemu_irq *pic);

/* sh_pci.c */
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                            qemu_irq *pic, int devfn_min, int nirq);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef QEMU_PCI_H
	2	#define QEMU_PCI_H
	3
	4	/* PCI includes legacy ISA access. */
	5	#include "isa.h"
	6
	7	/* PCI bus */
	8
	9	extern target_phys_addr_t pci_mem_base;
	10
d350d97d AL	11	/* see pci-ids.txt */
	12	#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
	13	#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
	14	#define PCI_SUBDEVICE_ID_QEMU 0x1100
	15
	16	#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
	17	#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
	18	#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
	19
87ecb68b PB	20	typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
	21	uint32_t address, uint32_t data, int len);
	22	typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
	23	uint32_t address, int len);
	24	typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
	25	uint32_t addr, uint32_t size, int type);
	26
	27	#define PCI_ADDRESS_SPACE_MEM 0x00
	28	#define PCI_ADDRESS_SPACE_IO 0x01
	29	#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
	30
	31	typedef struct PCIIORegion {
	32	uint32_t addr; /* current PCI mapping address. -1 means not mapped */
	33	uint32_t size;
	34	uint8_t type;
	35	PCIMapIORegionFunc *map_func;
	36	} PCIIORegion;
	37
	38	#define PCI_ROM_SLOT 6
	39	#define PCI_NUM_REGIONS 7
	40
	41	#define PCI_DEVICES_MAX 64
	42
	43	#define PCI_VENDOR_ID 0x00 /* 16 bits */
	44	#define PCI_DEVICE_ID 0x02 /* 16 bits */
	45	#define PCI_COMMAND 0x04 /* 16 bits */
	46	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	47	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
d350d97d	48	#define PCI_REVISION 0x08
87ecb68b	49	#define PCI_CLASS_DEVICE 0x0a /* Device class */
d350d97d AL	50	#define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
d350d97d AL	51	#define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
87ecb68b PB	52	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
	53	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
	54	#define PCI_MIN_GNT 0x3e /* 8 bits */
	55	#define PCI_MAX_LAT 0x3f /* 8 bits */
	56
	57	struct PCIDevice {
	58	/* PCI config space */
	59	uint8_t config[256];
	60
	61	/* the following fields are read only */
	62	PCIBus *bus;
	63	int devfn;
	64	char name[64];
	65	PCIIORegion io_regions[PCI_NUM_REGIONS];
	66
	67	/* do not access the following fields */
	68	PCIConfigReadFunc *config_read;
	69	PCIConfigWriteFunc *config_write;
	70	/* ??? This is a PC-specific hack, and should be removed. */
	71	int irq_index;
	72
	73	/* IRQ objects for the INTA-INTD pins. */
	74	qemu_irq *irq;
	75
	76	/* Current IRQ levels. Used internally by the generic PCI code. */
	77	int irq_state[4];
	78	};
	79
	80	PCIDevice pci_register_device(PCIBus bus, const char *name,
	81	int instance_size, int devfn,
	82	PCIConfigReadFunc *config_read,
	83	PCIConfigWriteFunc *config_write);
	84
	85	void pci_register_io_region(PCIDevice *pci_dev, int region_num,
	86	uint32_t size, int type,
	87	PCIMapIORegionFunc *map_func);
	88
	89	uint32_t pci_default_read_config(PCIDevice *d,
	90	uint32_t address, int len);
	91	void pci_default_write_config(PCIDevice *d,
	92	uint32_t address, uint32_t val, int len);
	93	void pci_device_save(PCIDevice s, QEMUFile f);
	94	int pci_device_load(PCIDevice s, QEMUFile f);
	95
	96	typedef void (pci_set_irq_fn)(qemu_irq pic, int irq_num, int level);
	97	typedef int (pci_map_irq_fn)(PCIDevice pci_dev, int irq_num);
	98	PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	99	qemu_irq *pic, int devfn_min, int nirq);
	100
	101	void pci_nic_init(PCIBus bus, NICInfo nd, int devfn);
	102	void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
	103	uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
	104	int pci_bus_num(PCIBus *s);
	105	void pci_for_each_device(int bus_num, void (fn)(PCIDevice d));
	106
	107	void pci_info(void);
	108	PCIBus pci_bridge_init(PCIBus bus, int devfn, uint32_t id,
	109	pci_map_irq_fn map_irq, const char *name);
	110
	111	/* lsi53c895a.c */
e4bcb14c	112	#define LSI_MAX_DEVS 7
87ecb68b PB	113	void lsi_scsi_attach(void opaque, BlockDriverState bd, int id);
	114	void lsi_scsi_init(PCIBus bus, int devfn);
	115
	116	/* vmware_vga.c */
	117	void pci_vmsvga_init(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
	118	unsigned long vga_ram_offset, int vga_ram_size);
	119
	120	/* usb-uhci.c */
	121	void usb_uhci_piix3_init(PCIBus *bus, int devfn);
	122	void usb_uhci_piix4_init(PCIBus *bus, int devfn);
	123
	124	/* usb-ohci.c */
	125	void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
	126
	127	/* eepro100.c */
	128
	129	void pci_i82551_init(PCIBus bus, NICInfo nd, int devfn);
	130	void pci_i82557b_init(PCIBus bus, NICInfo nd, int devfn);
	131	void pci_i82559er_init(PCIBus bus, NICInfo nd, int devfn);
	132
	133	/* ne2000.c */
	134
	135	void pci_ne2000_init(PCIBus bus, NICInfo nd, int devfn);
	136
	137	/* rtl8139.c */
	138
	139	void pci_rtl8139_init(PCIBus bus, NICInfo nd, int devfn);
	140
7c23b892 AZ	141	/* e1000.c */
	142	void pci_e1000_init(PCIBus bus, NICInfo nd, int devfn);
	143
87ecb68b PB	144	/* pcnet.c */
	145	void pci_pcnet_init(PCIBus bus, NICInfo nd, int devfn);
	146
	147	/* prep_pci.c */
	148	PCIBus pci_prep_init(qemu_irq pic);
	149
	150	/* apb_pci.c */
	151	PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
	152	qemu_irq *pic);
	153
b79e1752 AJ	154	/* sh_pci.c */
	155	PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	156	qemu_irq *pic, int devfn_min, int nirq);
	157
87ecb68b	158	#endif