[qemu.git] / hw / pci.h

#ifndef QEMU_PCI_H
#define QEMU_PCI_H

#include "qemu-common.h"

/* PCI includes legacy ISA access.  */
#include "isa.h"

/* PCI bus */

extern target_phys_addr_t pci_mem_base;

#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)         ((devfn) & 0x07)

/* Class, Vendor and Device IDs from Linux's pci_ids.h */
#include "pci_ids.h"

/* QEMU-specific Vendor and Device ID definitions */

/* IBM (0x1014) */
#define PCI_DEVICE_ID_IBM_440GX          0x027f
#define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff

/* Hitachi (0x1054) */
#define PCI_VENDOR_ID_HITACHI            0x1054
#define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e

/* Apple (0x106b) */
#define PCI_DEVICE_ID_APPLE_343S1201     0x0010
#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
#define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f

/* Realtek (0x10ec) */
#define PCI_DEVICE_ID_REALTEK_8029       0x8029

/* Xilinx (0x10ee) */
#define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300

/* Marvell (0x11ab) */
#define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620

/* QEMU/Bochs VGA (0x1234) */
#define PCI_VENDOR_ID_QEMU               0x1234
#define PCI_DEVICE_ID_QEMU_VGA           0x1111

/* VMWare (0x15ad) */
#define PCI_VENDOR_ID_VMWARE             0x15ad
#define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
#define PCI_DEVICE_ID_VMWARE_NET         0x0720
#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
#define PCI_DEVICE_ID_VMWARE_IDE         0x1729

/* Intel (0x8086) */
#define PCI_DEVICE_ID_INTEL_82551IT      0x1209

/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
#define PCI_SUBDEVICE_ID_QEMU            0x1100

#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
#define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003

typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
                                uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
                                   uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
                                uint32_t addr, uint32_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);

#define PCI_ADDRESS_SPACE_MEM		0x00
#define PCI_ADDRESS_SPACE_IO		0x01
#define PCI_ADDRESS_SPACE_MEM_PREFETCH	0x08

typedef struct PCIIORegion {
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
    uint32_t size;
    uint8_t type;
    PCIMapIORegionFunc *map_func;
} PCIIORegion;

#define PCI_ROM_SLOT 6
#define PCI_NUM_REGIONS 7

#define PCI_DEVICES_MAX 64

/* Declarations from linux/pci_regs.h */
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define PCI_STATUS              0x06    /* 16 bits */
#define PCI_REVISION_ID         0x08    /* 8 bits  */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
#define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

#define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
#define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
#define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */

/* Bits in the PCI Status Register (PCI 2.3 spec) */
#define PCI_STATUS_RESERVED1	0x007
#define PCI_STATUS_INT_STATUS	0x008
#define PCI_STATUS_CAPABILITIES	0x010
#define PCI_STATUS_66MHZ	0x020
#define PCI_STATUS_RESERVED2	0x040
#define PCI_STATUS_FAST_BACK	0x080
#define PCI_STATUS_DEVSEL	0x600

#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
                PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
                PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)

#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)

/* Bits in the PCI Command Register (PCI 2.3 spec) */
#define PCI_COMMAND_RESERVED	0xf800

#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)

struct PCIDevice {
    /* PCI config space */
    uint8_t config[256];

    /* the following fields are read only */
    PCIBus *bus;
    int devfn;
    char name[64];
    PCIIORegion io_regions[PCI_NUM_REGIONS];

    /* do not access the following fields */
    PCIConfigReadFunc *config_read;
    PCIConfigWriteFunc *config_write;
    PCIUnregisterFunc *unregister;
    /* ??? This is a PC-specific hack, and should be removed.  */
    int irq_index;

    /* IRQ objects for the INTA-INTD pins.  */
    qemu_irq *irq;

    /* Current IRQ levels.  Used internally by the generic PCI code.  */
    int irq_state[4];
};

PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                               int instance_size, int devfn,
                               PCIConfigReadFunc *config_read,
                               PCIConfigWriteFunc *config_write);
int pci_unregister_device(PCIDevice *pci_dev);

void pci_register_io_region(PCIDevice *pci_dev, int region_num,
                            uint32_t size, int type,
                            PCIMapIORegionFunc *map_func);

uint32_t pci_default_read_config(PCIDevice *d,
                                 uint32_t address, int len);
void pci_default_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);

typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                         qemu_irq *pic, int devfn_min, int nirq);

PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
                  const char *default_model);
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
int pci_bus_num(PCIBus *s);
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
PCIBus *pci_find_bus(int bus_num);
PCIDevice *pci_find_device(int bus_num, int slot, int function);

int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);

void pci_info(Monitor *mon);
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
                        pci_map_irq_fn map_irq, const char *name);

static inline void
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
}

static inline void
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
}

static inline void
pci_config_set_class(uint8_t *pci_config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
}

/* lsi53c895a.c */
#define LSI_MAX_DEVS 7
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *lsi_scsi_init(PCIBus *bus, int devfn);

/* vmware_vga.c */
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
                     unsigned long vga_ram_offset, int vga_ram_size);

/* usb-uhci.c */
void usb_uhci_piix3_init(PCIBus *bus, int devfn);
void usb_uhci_piix4_init(PCIBus *bus, int devfn);

/* usb-ohci.c */
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);

/* eepro100.c */

PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);

/* ne2000.c */

PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* rtl8139.c */

PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);

/* e1000.c */
PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* pcnet.c */
PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

/* prep_pci.c */
PCIBus *pci_prep_init(qemu_irq *pic);

/* apb_pci.c */
PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);

/* sh_pci.c */
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                            qemu_irq *pic, int devfn_min, int nirq);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef QEMU_PCI_H
	2	#define QEMU_PCI_H
	3
376253ec AL	4	#include "qemu-common.h"
376253ec AL	5
87ecb68b PB	6	/* PCI includes legacy ISA access. */
	7	#include "isa.h"
	8
	9	/* PCI bus */
	10
	11	extern target_phys_addr_t pci_mem_base;
	12
3ae80618 AL	13	#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) \| ((func) & 0x07))
	14	#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
	15	#define PCI_FUNC(devfn) ((devfn) & 0x07)
	16
a770dc7e AL	17	/* Class, Vendor and Device IDs from Linux's pci_ids.h */
a770dc7e AL	18	#include "pci_ids.h"
173a543b	19
a770dc7e	20	/* QEMU-specific Vendor and Device ID definitions */
6f338c34	21
a770dc7e AL	22	/* IBM (0x1014) */
a770dc7e AL	23	#define PCI_DEVICE_ID_IBM_440GX 0x027f
4ebcf884	24	#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
deb54399	25
a770dc7e	26	/* Hitachi (0x1054) */
deb54399	27	#define PCI_VENDOR_ID_HITACHI 0x1054
a770dc7e	28	#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
deb54399	29
a770dc7e	30	/* Apple (0x106b) */
4ebcf884 BS	31	#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
	32	#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
	33	#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
4ebcf884	34	#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
a770dc7e	35	#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
deb54399	36
a770dc7e AL	37	/* Realtek (0x10ec) */
a770dc7e AL	38	#define PCI_DEVICE_ID_REALTEK_8029 0x8029
deb54399	39
a770dc7e AL	40	/* Xilinx (0x10ee) */
a770dc7e AL	41	#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
deb54399	42
a770dc7e AL	43	/* Marvell (0x11ab) */
a770dc7e AL	44	#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
deb54399	45
a770dc7e	46	/* QEMU/Bochs VGA (0x1234) */
4ebcf884 BS	47	#define PCI_VENDOR_ID_QEMU 0x1234
	48	#define PCI_DEVICE_ID_QEMU_VGA 0x1111
	49
a770dc7e	50	/* VMWare (0x15ad) */
deb54399 AL	51	#define PCI_VENDOR_ID_VMWARE 0x15ad
	52	#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
	53	#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
	54	#define PCI_DEVICE_ID_VMWARE_NET 0x0720
	55	#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
	56	#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
	57
cef3017c	58	/* Intel (0x8086) */
a770dc7e	59	#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
74c62ba8	60
deb54399	61	/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
d350d97d AL	62	#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
	63	#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
	64	#define PCI_SUBDEVICE_ID_QEMU 0x1100
	65
	66	#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
	67	#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
	68	#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
14d50bef	69	#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
d350d97d	70
87ecb68b PB	71	typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
	72	uint32_t address, uint32_t data, int len);
	73	typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
	74	uint32_t address, int len);
	75	typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
	76	uint32_t addr, uint32_t size, int type);
5851e08c	77	typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
87ecb68b PB	78
	79	#define PCI_ADDRESS_SPACE_MEM 0x00
	80	#define PCI_ADDRESS_SPACE_IO 0x01
	81	#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
	82
	83	typedef struct PCIIORegion {
	84	uint32_t addr; /* current PCI mapping address. -1 means not mapped */
	85	uint32_t size;
	86	uint8_t type;
	87	PCIMapIORegionFunc *map_func;
	88	} PCIIORegion;
	89
	90	#define PCI_ROM_SLOT 6
	91	#define PCI_NUM_REGIONS 7
	92
	93	#define PCI_DEVICES_MAX 64
	94
cef3017c	95	/* Declarations from linux/pci_regs.h */
87ecb68b PB	96	#define PCI_VENDOR_ID 0x00 /* 16 bits */
	97	#define PCI_DEVICE_ID 0x02 /* 16 bits */
	98	#define PCI_COMMAND 0x04 /* 16 bits */
	99	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	100	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
cef3017c AL	101	#define PCI_STATUS 0x06 /* 16 bits */
cef3017c AL	102	#define PCI_REVISION_ID 0x08 /* 8 bits */
87ecb68b	103	#define PCI_CLASS_DEVICE 0x0a /* Device class */
cef3017c AL	104	#define PCI_HEADER_TYPE 0x0e /* 8 bits */
	105	#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
	106	#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
87ecb68b PB	107	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
	108	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
	109	#define PCI_MIN_GNT 0x3e /* 8 bits */
	110	#define PCI_MAX_LAT 0x3f /* 8 bits */
	111
cef3017c AL	112	#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
	113	#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
	114	#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
	115
8098ed41 AJ	116	/* Bits in the PCI Status Register (PCI 2.3 spec) */
	117	#define PCI_STATUS_RESERVED1 0x007
	118	#define PCI_STATUS_INT_STATUS 0x008
	119	#define PCI_STATUS_CAPABILITIES 0x010
	120	#define PCI_STATUS_66MHZ 0x020
	121	#define PCI_STATUS_RESERVED2 0x040
	122	#define PCI_STATUS_FAST_BACK 0x080
	123	#define PCI_STATUS_DEVSEL 0x600
	124
	125	#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 \| \
	126	PCI_STATUS_INT_STATUS \| PCI_STATUS_CAPABILITIES \| \
	127	PCI_STATUS_66MHZ \| PCI_STATUS_RESERVED2 \| PCI_STATUS_FAST_BACK)
	128
	129	#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
	130
475dc65f AJ	131	/* Bits in the PCI Command Register (PCI 2.3 spec) */
	132	#define PCI_COMMAND_RESERVED 0xf800
	133
	134	#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
	135
87ecb68b PB	136	struct PCIDevice {
	137	/* PCI config space */
	138	uint8_t config[256];
	139
	140	/* the following fields are read only */
	141	PCIBus *bus;
	142	int devfn;
	143	char name[64];
	144	PCIIORegion io_regions[PCI_NUM_REGIONS];
	145
	146	/* do not access the following fields */
	147	PCIConfigReadFunc *config_read;
	148	PCIConfigWriteFunc *config_write;
5851e08c	149	PCIUnregisterFunc *unregister;
87ecb68b PB	150	/* ??? This is a PC-specific hack, and should be removed. */
	151	int irq_index;
	152
	153	/* IRQ objects for the INTA-INTD pins. */
	154	qemu_irq *irq;
	155
	156	/* Current IRQ levels. Used internally by the generic PCI code. */
	157	int irq_state[4];
	158	};
	159
	160	PCIDevice pci_register_device(PCIBus bus, const char *name,
	161	int instance_size, int devfn,
	162	PCIConfigReadFunc *config_read,
	163	PCIConfigWriteFunc *config_write);
5851e08c	164	int pci_unregister_device(PCIDevice *pci_dev);
87ecb68b PB	165
	166	void pci_register_io_region(PCIDevice *pci_dev, int region_num,
	167	uint32_t size, int type,
	168	PCIMapIORegionFunc *map_func);
	169
	170	uint32_t pci_default_read_config(PCIDevice *d,
	171	uint32_t address, int len);
	172	void pci_default_write_config(PCIDevice *d,
	173	uint32_t address, uint32_t val, int len);
	174	void pci_device_save(PCIDevice s, QEMUFile f);
	175	int pci_device_load(PCIDevice s, QEMUFile f);
	176
	177	typedef void (pci_set_irq_fn)(qemu_irq pic, int irq_num, int level);
	178	typedef int (pci_map_irq_fn)(PCIDevice pci_dev, int irq_num);
	179	PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	180	qemu_irq *pic, int devfn_min, int nirq);
	181
72da4208	182	PCIDevice pci_nic_init(PCIBus bus, NICInfo *nd, int devfn,
cb457d76	183	const char *default_model);
87ecb68b PB	184	void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
	185	uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
	186	int pci_bus_num(PCIBus *s);
	187	void pci_for_each_device(int bus_num, void (fn)(PCIDevice d));
3ae80618 AL	188	PCIBus *pci_find_bus(int bus_num);
3ae80618 AL	189	PCIDevice *pci_find_device(int bus_num, int slot, int function);
87ecb68b	190
880345c4 AL	191	int pci_read_devaddr(const char addr, int domp, int busp, unsigned slotp);
	192	int pci_assign_devaddr(const char addr, int domp, int busp, unsigned slotp);
	193
376253ec	194	void pci_info(Monitor *mon);
480b9f24	195	PCIBus pci_bridge_init(PCIBus bus, int devfn, uint16_t vid, uint16_t did,
87ecb68b PB	196	pci_map_irq_fn map_irq, const char *name);
87ecb68b PB	197
deb54399 AL	198	static inline void
	199	pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
	200	{
	201	cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
	202	}
	203
	204	static inline void
	205	pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
	206	{
	207	cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
	208	}
	209
173a543b BS	210	static inline void
	211	pci_config_set_class(uint8_t *pci_config, uint16_t val)
	212	{
	213	cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
	214	}
	215
87ecb68b	216	/* lsi53c895a.c */
e4bcb14c	217	#define LSI_MAX_DEVS 7
87ecb68b PB	218	void lsi_scsi_attach(void opaque, BlockDriverState bd, int id);
	219	void lsi_scsi_init(PCIBus bus, int devfn);
	220
	221	/* vmware_vga.c */
3023f332	222	void pci_vmsvga_init(PCIBus bus, uint8_t vga_ram_base,
87ecb68b PB	223	unsigned long vga_ram_offset, int vga_ram_size);
	224
	225	/* usb-uhci.c */
	226	void usb_uhci_piix3_init(PCIBus *bus, int devfn);
	227	void usb_uhci_piix4_init(PCIBus *bus, int devfn);
	228
	229	/* usb-ohci.c */
	230	void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
	231
	232	/* eepro100.c */
	233
72da4208 AL	234	PCIDevice pci_i82551_init(PCIBus bus, NICInfo *nd, int devfn);
	235	PCIDevice pci_i82557b_init(PCIBus bus, NICInfo *nd, int devfn);
	236	PCIDevice pci_i82559er_init(PCIBus bus, NICInfo *nd, int devfn);
87ecb68b PB	237
	238	/* ne2000.c */
	239
72da4208	240	PCIDevice pci_ne2000_init(PCIBus bus, NICInfo *nd, int devfn);
87ecb68b PB	241
	242	/* rtl8139.c */
	243
72da4208	244	PCIDevice pci_rtl8139_init(PCIBus bus, NICInfo *nd, int devfn);
87ecb68b	245
7c23b892	246	/* e1000.c */
72da4208	247	PCIDevice pci_e1000_init(PCIBus bus, NICInfo *nd, int devfn);
7c23b892	248
87ecb68b	249	/* pcnet.c */
72da4208	250	PCIDevice pci_pcnet_init(PCIBus bus, NICInfo *nd, int devfn);
87ecb68b PB	251
	252	/* prep_pci.c */
	253	PCIBus pci_prep_init(qemu_irq pic);
	254
	255	/* apb_pci.c */
c190ea07 BS	256	PCIBus *pci_apb_init(target_phys_addr_t special_base,
	257	target_phys_addr_t mem_base,
	258	qemu_irq pic, PCIBus bus2, PCIBus *bus3);
87ecb68b	259
b79e1752 AJ	260	/* sh_pci.c */
	261	PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	262	qemu_irq *pic, int devfn_min, int nirq);
	263
87ecb68b	264	#endif