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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
6b1b92d3 PB |
6 | #include "qdev.h" |
7 | ||
87ecb68b PB |
8 | /* PCI includes legacy ISA access. */ |
9 | #include "isa.h" | |
10 | ||
11 | /* PCI bus */ | |
12 | ||
c227f099 | 13 | extern target_phys_addr_t pci_mem_base; |
87ecb68b | 14 | |
3ae80618 AL |
15 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
16 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
17 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
18 | ||
a770dc7e AL |
19 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
20 | #include "pci_ids.h" | |
173a543b | 21 | |
a770dc7e | 22 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 23 | |
a770dc7e AL |
24 | /* IBM (0x1014) */ |
25 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 26 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 27 | |
a770dc7e | 28 | /* Hitachi (0x1054) */ |
deb54399 | 29 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 30 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 31 | |
a770dc7e | 32 | /* Apple (0x106b) */ |
4ebcf884 BS |
33 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
34 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
35 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 36 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 37 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 38 | |
a770dc7e AL |
39 | /* Realtek (0x10ec) */ |
40 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 41 | |
a770dc7e AL |
42 | /* Xilinx (0x10ee) */ |
43 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 44 | |
a770dc7e AL |
45 | /* Marvell (0x11ab) */ |
46 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 47 | |
a770dc7e | 48 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
49 | #define PCI_VENDOR_ID_QEMU 0x1234 |
50 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
51 | ||
a770dc7e | 52 | /* VMWare (0x15ad) */ |
deb54399 AL |
53 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
54 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
55 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
56 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
57 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
58 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
59 | ||
cef3017c | 60 | /* Intel (0x8086) */ |
a770dc7e | 61 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 62 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
74c62ba8 | 63 | |
deb54399 | 64 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
65 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
66 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
67 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
68 | ||
69 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
70 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
71 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 72 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
d350d97d | 73 | |
4f8589e1 IY |
74 | typedef uint64_t pcibus_t; |
75 | #define FMT_PCIBUS PRIx64 | |
6e355d90 | 76 | |
87ecb68b PB |
77 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
78 | uint32_t address, uint32_t data, int len); | |
79 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
80 | uint32_t address, int len); | |
81 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 82 | pcibus_t addr, pcibus_t size, int type); |
5851e08c | 83 | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 84 | |
87ecb68b | 85 | typedef struct PCIIORegion { |
6e355d90 IY |
86 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
87 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
88 | pcibus_t size; | |
a0c7a97e | 89 | pcibus_t filtered_size; |
87ecb68b PB |
90 | uint8_t type; |
91 | PCIMapIORegionFunc *map_func; | |
92 | } PCIIORegion; | |
93 | ||
94 | #define PCI_ROM_SLOT 6 | |
95 | #define PCI_NUM_REGIONS 7 | |
96 | ||
cef3017c | 97 | /* Declarations from linux/pci_regs.h */ |
87ecb68b PB |
98 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
99 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
100 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
101 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
102 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
b7ee1603 | 103 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ |
cef3017c | 104 | #define PCI_STATUS 0x06 /* 16 bits */ |
67a2698d | 105 | #define PCI_STATUS_INTERRUPT 0x08 |
cef3017c | 106 | #define PCI_REVISION_ID 0x08 /* 8 bits */ |
bd4b65ee | 107 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
87ecb68b | 108 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
b7ee1603 MT |
109 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
110 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ | |
cef3017c | 111 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
6407f373 IY |
112 | #define PCI_HEADER_TYPE_NORMAL 0 |
113 | #define PCI_HEADER_TYPE_BRIDGE 1 | |
114 | #define PCI_HEADER_TYPE_CARDBUS 2 | |
115 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 | |
b7ee1603 | 116 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
0392a017 IY |
117 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
118 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 | |
14421258 | 119 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
0392a017 | 120 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
b7ee1603 MT |
121 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
122 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ | |
e822a52a | 123 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
fb231628 IY |
124 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
125 | #define PCI_IO_LIMIT 0x1d | |
a0c7a97e | 126 | #define PCI_IO_RANGE_TYPE_32 0x01 |
fb231628 | 127 | #define PCI_IO_RANGE_MASK (~0x0fUL) |
b7ee1603 | 128 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
fb231628 IY |
129 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
130 | #define PCI_MEMORY_LIMIT 0x22 | |
131 | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) | |
132 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ | |
133 | #define PCI_PREF_MEMORY_LIMIT 0x26 | |
134 | #define PCI_PREF_RANGE_MASK (~0x0fUL) | |
d46636b8 | 135 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
fb231628 | 136 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
a0c7a97e | 137 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
cef3017c AL |
138 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ |
139 | #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ | |
5330de09 MT |
140 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
141 | #define PCI_ROM_ADDRESS_ENABLE 0x01 | |
fb231628 IY |
142 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
143 | #define PCI_IO_LIMIT_UPPER16 0x32 | |
b7ee1603 | 144 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
b3b11697 | 145 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
87ecb68b PB |
146 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
147 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
148 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
fb231628 | 149 | #define PCI_BRIDGE_CONTROL 0x3e |
87ecb68b PB |
150 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
151 | ||
6f4cbd39 MT |
152 | /* Capability lists */ |
153 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ | |
154 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ | |
155 | ||
cef3017c AL |
156 | #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ |
157 | #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ | |
158 | #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ | |
159 | ||
8098ed41 AJ |
160 | /* Bits in the PCI Status Register (PCI 2.3 spec) */ |
161 | #define PCI_STATUS_RESERVED1 0x007 | |
162 | #define PCI_STATUS_INT_STATUS 0x008 | |
6f4cbd39 | 163 | #define PCI_STATUS_CAP_LIST 0x010 |
8098ed41 AJ |
164 | #define PCI_STATUS_66MHZ 0x020 |
165 | #define PCI_STATUS_RESERVED2 0x040 | |
166 | #define PCI_STATUS_FAST_BACK 0x080 | |
167 | #define PCI_STATUS_DEVSEL 0x600 | |
168 | ||
169 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ | |
170 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ | |
171 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) | |
172 | ||
173 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) | |
174 | ||
475dc65f AJ |
175 | /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
176 | #define PCI_COMMAND_RESERVED 0xf800 | |
177 | ||
178 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) | |
179 | ||
b7ee1603 MT |
180 | /* Size of the standard PCI config header */ |
181 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
182 | /* Size of the standard PCI config space */ | |
183 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
184 | /* Size of the standart PCIe config space: 4KB */ |
185 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 186 | |
e369cad7 IY |
187 | #define PCI_NUM_PINS 4 /* A-D */ |
188 | ||
02eb84d0 MT |
189 | /* Bits in cap_present field. */ |
190 | enum { | |
191 | QEMU_PCI_CAP_MSIX = 0x1, | |
a9f49946 | 192 | QEMU_PCI_CAP_EXPRESS = 0x2, |
02eb84d0 MT |
193 | }; |
194 | ||
87ecb68b | 195 | struct PCIDevice { |
6b1b92d3 | 196 | DeviceState qdev; |
87ecb68b | 197 | /* PCI config space */ |
a9f49946 | 198 | uint8_t *config; |
b7ee1603 | 199 | |
bd4b65ee MT |
200 | /* Used to enable config checks on load. Note that writeable bits are |
201 | * never checked even if set in cmask. */ | |
a9f49946 | 202 | uint8_t *cmask; |
bd4b65ee | 203 | |
b7ee1603 | 204 | /* Used to implement R/W bytes */ |
a9f49946 | 205 | uint8_t *wmask; |
87ecb68b | 206 | |
6f4cbd39 | 207 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 208 | uint8_t *used; |
6f4cbd39 | 209 | |
87ecb68b PB |
210 | /* the following fields are read only */ |
211 | PCIBus *bus; | |
54586bd1 | 212 | uint32_t devfn; |
87ecb68b PB |
213 | char name[64]; |
214 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
215 | ||
216 | /* do not access the following fields */ | |
217 | PCIConfigReadFunc *config_read; | |
218 | PCIConfigWriteFunc *config_write; | |
87ecb68b PB |
219 | |
220 | /* IRQ objects for the INTA-INTD pins. */ | |
221 | qemu_irq *irq; | |
222 | ||
223 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
eea4acfa | 224 | uint8_t irq_state; |
02eb84d0 MT |
225 | |
226 | /* Capability bits */ | |
227 | uint32_t cap_present; | |
228 | ||
229 | /* Offset of MSI-X capability in config space */ | |
230 | uint8_t msix_cap; | |
231 | ||
232 | /* MSI-X entries */ | |
233 | int msix_entries_nr; | |
234 | ||
235 | /* Space to store MSIX table */ | |
236 | uint8_t *msix_table_page; | |
237 | /* MMIO index used to map MSIX table and pending bit entries. */ | |
238 | int msix_mmio_index; | |
239 | /* Reference-count for entries actually in use by driver. */ | |
240 | unsigned *msix_entry_used; | |
241 | /* Region including the MSI-X table */ | |
242 | uint32_t msix_bar_size; | |
f16c4abf JQ |
243 | /* Version id needed for VMState */ |
244 | int32_t version_id; | |
72bb3c75 AL |
245 | |
246 | /* Location of option rom */ | |
898829d5 | 247 | char *romfile; |
72bb3c75 | 248 | ram_addr_t rom_offset; |
027866ce | 249 | uint32_t rom_bar; |
87ecb68b PB |
250 | }; |
251 | ||
252 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
253 | int instance_size, int devfn, | |
254 | PCIConfigReadFunc *config_read, | |
255 | PCIConfigWriteFunc *config_write); | |
256 | ||
28c2c264 | 257 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 258 | pcibus_t size, int type, |
87ecb68b PB |
259 | PCIMapIORegionFunc *map_func); |
260 | ||
6f4cbd39 MT |
261 | int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); |
262 | ||
263 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
264 | ||
265 | void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size); | |
266 | ||
267 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); | |
268 | ||
269 | ||
87ecb68b PB |
270 | uint32_t pci_default_read_config(PCIDevice *d, |
271 | uint32_t address, int len); | |
272 | void pci_default_write_config(PCIDevice *d, | |
273 | uint32_t address, uint32_t val, int len); | |
274 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
275 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
276 | ||
5d4e84c8 | 277 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 278 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
ee995ffb | 279 | typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state); |
21eea4b3 GH |
280 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
281 | const char *name, int devfn_min); | |
282 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min); | |
283 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
284 | void *irq_opaque, int nirq); | |
ee995ffb | 285 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug); |
02e2da45 PB |
286 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
287 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
5d4e84c8 | 288 | void *irq_opaque, int devfn_min, int nirq); |
87ecb68b | 289 | |
5607c388 MA |
290 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
291 | const char *default_devaddr); | |
07caea31 MA |
292 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
293 | const char *default_devaddr); | |
87ecb68b | 294 | int pci_bus_num(PCIBus *s); |
e822a52a | 295 | void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
c469e1dd | 296 | PCIBus *pci_find_root_bus(int domain); |
e822a52a IY |
297 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num); |
298 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function); | |
49bd1458 | 299 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
87ecb68b | 300 | |
e9283f8b JK |
301 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
302 | unsigned *slotp); | |
880345c4 | 303 | |
376253ec | 304 | void pci_info(Monitor *mon); |
480b9f24 | 305 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
87ecb68b | 306 | pci_map_irq_fn map_irq, const char *name); |
d6318738 | 307 | PCIDevice *pci_bridge_get_device(PCIBus *bus); |
87ecb68b | 308 | |
64d50b8b MT |
309 | static inline void |
310 | pci_set_byte(uint8_t *config, uint8_t val) | |
311 | { | |
312 | *config = val; | |
313 | } | |
314 | ||
315 | static inline uint8_t | |
316 | pci_get_byte(uint8_t *config) | |
317 | { | |
318 | return *config; | |
319 | } | |
320 | ||
14e12559 MT |
321 | static inline void |
322 | pci_set_word(uint8_t *config, uint16_t val) | |
323 | { | |
324 | cpu_to_le16wu((uint16_t *)config, val); | |
325 | } | |
326 | ||
327 | static inline uint16_t | |
328 | pci_get_word(uint8_t *config) | |
329 | { | |
330 | return le16_to_cpupu((uint16_t *)config); | |
331 | } | |
332 | ||
333 | static inline void | |
334 | pci_set_long(uint8_t *config, uint32_t val) | |
335 | { | |
336 | cpu_to_le32wu((uint32_t *)config, val); | |
337 | } | |
338 | ||
339 | static inline uint32_t | |
340 | pci_get_long(uint8_t *config) | |
341 | { | |
342 | return le32_to_cpupu((uint32_t *)config); | |
343 | } | |
344 | ||
fb5ce7d2 IY |
345 | static inline void |
346 | pci_set_quad(uint8_t *config, uint64_t val) | |
347 | { | |
348 | cpu_to_le64w((uint64_t *)config, val); | |
349 | } | |
350 | ||
351 | static inline uint64_t | |
352 | pci_get_quad(uint8_t *config) | |
353 | { | |
354 | return le64_to_cpup((uint64_t *)config); | |
355 | } | |
356 | ||
deb54399 AL |
357 | static inline void |
358 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
359 | { | |
14e12559 | 360 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
361 | } |
362 | ||
363 | static inline void | |
364 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
365 | { | |
14e12559 | 366 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
367 | } |
368 | ||
173a543b BS |
369 | static inline void |
370 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
371 | { | |
14e12559 | 372 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
373 | } |
374 | ||
81a322d4 | 375 | typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
0aab0d3a GH |
376 | typedef struct { |
377 | DeviceInfo qdev; | |
378 | pci_qdev_initfn init; | |
e3936fa5 | 379 | PCIUnregisterFunc *exit; |
0aab0d3a GH |
380 | PCIConfigReadFunc *config_read; |
381 | PCIConfigWriteFunc *config_write; | |
a9f49946 | 382 | |
fb231628 | 383 | /* pci config header type */ |
3c217c14 | 384 | uint8_t header_type; |
fb231628 | 385 | |
a9f49946 | 386 | /* pcie stuff */ |
3c217c14 | 387 | int is_express; /* is this device pci express? */ |
898829d5 GH |
388 | |
389 | /* rom bar */ | |
390 | const char *romfile; | |
0aab0d3a GH |
391 | } PCIDeviceInfo; |
392 | ||
393 | void pci_qdev_register(PCIDeviceInfo *info); | |
394 | void pci_qdev_register_many(PCIDeviceInfo *info); | |
6b1b92d3 | 395 | |
499cf102 | 396 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
397 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
398 | ||
a9f49946 IY |
399 | static inline int pci_is_express(PCIDevice *d) |
400 | { | |
401 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
402 | } | |
403 | ||
404 | static inline uint32_t pci_config_size(PCIDevice *d) | |
405 | { | |
406 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
407 | } | |
408 | ||
f49db805 IY |
409 | /* These are not pci specific. Should move into a separate header. |
410 | * Only pci.c uses them, so keep them here for now. | |
411 | */ | |
412 | ||
413 | /* Get last byte of a range from offset + length. | |
414 | * Undefined for ranges that wrap around 0. */ | |
415 | static inline uint64_t range_get_last(uint64_t offset, uint64_t len) | |
416 | { | |
417 | return offset + len - 1; | |
418 | } | |
419 | ||
420 | /* Check whether a given range covers a given byte. */ | |
421 | static inline int range_covers_byte(uint64_t offset, uint64_t len, | |
422 | uint64_t byte) | |
423 | { | |
424 | return offset <= byte && byte <= range_get_last(offset, len); | |
425 | } | |
426 | ||
427 | /* Check whether 2 given ranges overlap. | |
428 | * Undefined if ranges that wrap around 0. */ | |
429 | static inline int ranges_overlap(uint64_t first1, uint64_t len1, | |
430 | uint64_t first2, uint64_t len2) | |
431 | { | |
432 | uint64_t last1 = range_get_last(first1, len1); | |
433 | uint64_t last2 = range_get_last(first2, len2); | |
434 | ||
435 | return !(last2 < first1 || last1 < first2); | |
436 | } | |
437 | ||
87ecb68b | 438 | #endif |