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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
6b1b92d3 | 6 | #include "qdev.h" |
1e39101c | 7 | #include "memory.h" |
ec174575 | 8 | #include "dma.h" |
6b1b92d3 | 9 | |
87ecb68b PB |
10 | /* PCI includes legacy ISA access. */ |
11 | #include "isa.h" | |
12 | ||
0428527c IY |
13 | #include "pcie.h" |
14 | ||
87ecb68b PB |
15 | /* PCI bus */ |
16 | ||
3ae80618 AL |
17 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
19 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
90a20dbb | 20 | #define PCI_SLOT_MAX 32 |
6fa84913 | 21 | #define PCI_FUNC_MAX 8 |
3ae80618 | 22 | |
a770dc7e AL |
23 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
24 | #include "pci_ids.h" | |
173a543b | 25 | |
a770dc7e | 26 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 27 | |
a770dc7e AL |
28 | /* IBM (0x1014) */ |
29 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 30 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 31 | |
a770dc7e | 32 | /* Hitachi (0x1054) */ |
deb54399 | 33 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 34 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 35 | |
a770dc7e | 36 | /* Apple (0x106b) */ |
4ebcf884 BS |
37 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
39 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 40 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 41 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 42 | |
a770dc7e AL |
43 | /* Realtek (0x10ec) */ |
44 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 45 | |
a770dc7e AL |
46 | /* Xilinx (0x10ee) */ |
47 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 48 | |
a770dc7e AL |
49 | /* Marvell (0x11ab) */ |
50 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 51 | |
a770dc7e | 52 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
53 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
55 | ||
a770dc7e | 56 | /* VMWare (0x15ad) */ |
deb54399 AL |
57 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
59 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
60 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
61 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
62 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
63 | ||
cef3017c | 64 | /* Intel (0x8086) */ |
a770dc7e | 65 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 66 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
1a5a86fb | 67 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
74c62ba8 | 68 | |
deb54399 | 69 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
70 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
71 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
72 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
73 | ||
74 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
75 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
76 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 77 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
973abc7f | 78 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
16c915ba | 79 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
d350d97d | 80 | |
4f8589e1 | 81 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 82 | |
87ecb68b PB |
83 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
84 | uint32_t address, uint32_t data, int len); | |
85 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
86 | uint32_t address, int len); | |
87 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 88 | pcibus_t addr, pcibus_t size, int type); |
f90c2bcd | 89 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 90 | |
87ecb68b | 91 | typedef struct PCIIORegion { |
6e355d90 IY |
92 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
93 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
94 | pcibus_t size; | |
87ecb68b | 95 | uint8_t type; |
79ff8cb0 | 96 | MemoryRegion *memory; |
5968eca3 | 97 | MemoryRegion *address_space; |
87ecb68b PB |
98 | } PCIIORegion; |
99 | ||
100 | #define PCI_ROM_SLOT 6 | |
101 | #define PCI_NUM_REGIONS 7 | |
102 | ||
fb58a897 IY |
103 | #include "pci_regs.h" |
104 | ||
105 | /* PCI HEADER_TYPE */ | |
6407f373 | 106 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 | 107 | |
b7ee1603 MT |
108 | /* Size of the standard PCI config header */ |
109 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
110 | /* Size of the standard PCI config space */ | |
111 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
112 | /* Size of the standart PCIe config space: 4KB */ |
113 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 114 | |
e369cad7 IY |
115 | #define PCI_NUM_PINS 4 /* A-D */ |
116 | ||
02eb84d0 MT |
117 | /* Bits in cap_present field. */ |
118 | enum { | |
e4c7d2ae IY |
119 | QEMU_PCI_CAP_MSI = 0x1, |
120 | QEMU_PCI_CAP_MSIX = 0x2, | |
121 | QEMU_PCI_CAP_EXPRESS = 0x4, | |
49823868 IY |
122 | |
123 | /* multifunction capable device */ | |
e4c7d2ae | 124 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
49823868 | 125 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
b1aeb926 IY |
126 | |
127 | /* command register SERR bit enabled */ | |
128 | #define QEMU_PCI_CAP_SERR_BITNR 4 | |
129 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), | |
1dc324d2 MT |
130 | /* Standard hot plug controller. */ |
131 | #define QEMU_PCI_SHPC_BITNR 5 | |
132 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), | |
762833b3 MT |
133 | #define QEMU_PCI_SLOTID_BITNR 6 |
134 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), | |
02eb84d0 MT |
135 | }; |
136 | ||
40021f08 AL |
137 | #define TYPE_PCI_DEVICE "pci-device" |
138 | #define PCI_DEVICE(obj) \ | |
139 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) | |
140 | #define PCI_DEVICE_CLASS(klass) \ | |
141 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) | |
142 | #define PCI_DEVICE_GET_CLASS(obj) \ | |
143 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) | |
144 | ||
3afa9bb4 MT |
145 | typedef struct PCIINTxRoute { |
146 | enum { | |
147 | PCI_INTX_ENABLED, | |
148 | PCI_INTX_INVERTED, | |
149 | PCI_INTX_DISABLED, | |
150 | } mode; | |
151 | int irq; | |
152 | } PCIINTxRoute; | |
153 | ||
40021f08 AL |
154 | typedef struct PCIDeviceClass { |
155 | DeviceClass parent_class; | |
156 | ||
157 | int (*init)(PCIDevice *dev); | |
158 | PCIUnregisterFunc *exit; | |
159 | PCIConfigReadFunc *config_read; | |
160 | PCIConfigWriteFunc *config_write; | |
161 | ||
162 | uint16_t vendor_id; | |
163 | uint16_t device_id; | |
164 | uint8_t revision; | |
165 | uint16_t class_id; | |
166 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ | |
167 | uint16_t subsystem_id; /* only for header type = 0 */ | |
168 | ||
169 | /* | |
170 | * pci-to-pci bridge or normal device. | |
171 | * This doesn't mean pci host switch. | |
172 | * When card bus bridge is supported, this would be enhanced. | |
173 | */ | |
174 | int is_bridge; | |
175 | ||
176 | /* pcie stuff */ | |
177 | int is_express; /* is this device pci express? */ | |
178 | ||
179 | /* device isn't hot-pluggable */ | |
180 | int no_hotplug; | |
181 | ||
182 | /* rom bar */ | |
183 | const char *romfile; | |
184 | } PCIDeviceClass; | |
185 | ||
0ae16251 | 186 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
2cdfe53c JK |
187 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
188 | MSIMessage msg); | |
189 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); | |
190 | ||
87ecb68b | 191 | struct PCIDevice { |
6b1b92d3 | 192 | DeviceState qdev; |
5fa45de5 | 193 | |
87ecb68b | 194 | /* PCI config space */ |
a9f49946 | 195 | uint8_t *config; |
b7ee1603 | 196 | |
ebabb67a | 197 | /* Used to enable config checks on load. Note that writable bits are |
bd4b65ee | 198 | * never checked even if set in cmask. */ |
a9f49946 | 199 | uint8_t *cmask; |
bd4b65ee | 200 | |
b7ee1603 | 201 | /* Used to implement R/W bytes */ |
a9f49946 | 202 | uint8_t *wmask; |
87ecb68b | 203 | |
92ba5f51 IY |
204 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
205 | uint8_t *w1cmask; | |
206 | ||
6f4cbd39 | 207 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 208 | uint8_t *used; |
6f4cbd39 | 209 | |
87ecb68b PB |
210 | /* the following fields are read only */ |
211 | PCIBus *bus; | |
09f1bbcd | 212 | int32_t devfn; |
87ecb68b PB |
213 | char name[64]; |
214 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
817dcc53 | 215 | AddressSpace bus_master_as; |
1c380f94 | 216 | MemoryRegion bus_master_enable_region; |
5fa45de5 | 217 | DMAContext *dma; |
87ecb68b PB |
218 | |
219 | /* do not access the following fields */ | |
220 | PCIConfigReadFunc *config_read; | |
221 | PCIConfigWriteFunc *config_write; | |
87ecb68b PB |
222 | |
223 | /* IRQ objects for the INTA-INTD pins. */ | |
224 | qemu_irq *irq; | |
225 | ||
226 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
d036bb21 | 227 | uint8_t irq_state; |
02eb84d0 MT |
228 | |
229 | /* Capability bits */ | |
230 | uint32_t cap_present; | |
231 | ||
232 | /* Offset of MSI-X capability in config space */ | |
233 | uint8_t msix_cap; | |
234 | ||
235 | /* MSI-X entries */ | |
236 | int msix_entries_nr; | |
237 | ||
d35e428c AW |
238 | /* Space to store MSIX table & pending bit array */ |
239 | uint8_t *msix_table; | |
240 | uint8_t *msix_pba; | |
53f94925 AW |
241 | /* MemoryRegion container for msix exclusive BAR setup */ |
242 | MemoryRegion msix_exclusive_bar; | |
d35e428c AW |
243 | /* Memory Regions for MSIX table and pending bit entries. */ |
244 | MemoryRegion msix_table_mmio; | |
245 | MemoryRegion msix_pba_mmio; | |
02eb84d0 MT |
246 | /* Reference-count for entries actually in use by driver. */ |
247 | unsigned *msix_entry_used; | |
50322249 MT |
248 | /* MSIX function mask set or MSIX disabled */ |
249 | bool msix_function_masked; | |
f16c4abf JQ |
250 | /* Version id needed for VMState */ |
251 | int32_t version_id; | |
c2039bd0 | 252 | |
e4c7d2ae IY |
253 | /* Offset of MSI capability in config space */ |
254 | uint8_t msi_cap; | |
255 | ||
0428527c IY |
256 | /* PCI Express */ |
257 | PCIExpressDevice exp; | |
258 | ||
1dc324d2 MT |
259 | /* SHPC */ |
260 | SHPCDevice *shpc; | |
261 | ||
c2039bd0 | 262 | /* Location of option rom */ |
8c52c8f3 | 263 | char *romfile; |
14caaf7f AK |
264 | bool has_rom; |
265 | MemoryRegion rom; | |
88169ddf | 266 | uint32_t rom_bar; |
2cdfe53c | 267 | |
0ae16251 JK |
268 | /* INTx routing notifier */ |
269 | PCIINTxRoutingNotifier intx_routing_notifier; | |
270 | ||
2cdfe53c JK |
271 | /* MSI-X notifiers */ |
272 | MSIVectorUseNotifier msix_vector_use_notifier; | |
273 | MSIVectorReleaseNotifier msix_vector_release_notifier; | |
87ecb68b PB |
274 | }; |
275 | ||
e824b2cc AK |
276 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
277 | uint8_t attr, MemoryRegion *memory); | |
16a96f28 | 278 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
87ecb68b | 279 | |
ca77089d IY |
280 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
281 | uint8_t offset, uint8_t size); | |
6f4cbd39 MT |
282 | |
283 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
284 | ||
6f4cbd39 MT |
285 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
286 | ||
287 | ||
87ecb68b PB |
288 | uint32_t pci_default_read_config(PCIDevice *d, |
289 | uint32_t address, int len); | |
290 | void pci_default_write_config(PCIDevice *d, | |
291 | uint32_t address, uint32_t val, int len); | |
292 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
293 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
f5e6fed8 | 294 | MemoryRegion *pci_address_space(PCIDevice *dev); |
e11d6439 | 295 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
87ecb68b | 296 | |
5d4e84c8 | 297 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 298 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
3afa9bb4 | 299 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
e927d487 MT |
300 | |
301 | typedef enum { | |
302 | PCI_HOTPLUG_DISABLED, | |
303 | PCI_HOTPLUG_ENABLED, | |
304 | PCI_COLDPLUG_ENABLED, | |
305 | } PCIHotplugState; | |
306 | ||
307 | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, | |
308 | PCIHotplugState state); | |
21eea4b3 | 309 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
1e39101c | 310 | const char *name, |
aee97b84 AK |
311 | MemoryRegion *address_space_mem, |
312 | MemoryRegion *address_space_io, | |
1e39101c AK |
313 | uint8_t devfn_min); |
314 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, | |
aee97b84 AK |
315 | MemoryRegion *address_space_mem, |
316 | MemoryRegion *address_space_io, | |
317 | uint8_t devfn_min); | |
21eea4b3 GH |
318 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
319 | void *irq_opaque, int nirq); | |
9ddf8437 | 320 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
87c30546 | 321 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); |
91e56159 IY |
322 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
323 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); | |
02e2da45 PB |
324 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
325 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 326 | void *irq_opaque, |
aee97b84 AK |
327 | MemoryRegion *address_space_mem, |
328 | MemoryRegion *address_space_io, | |
1e39101c | 329 | uint8_t devfn_min, int nirq); |
3afa9bb4 MT |
330 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
331 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); | |
d6e65d54 | 332 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
0ae16251 JK |
333 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
334 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
335 | PCIINTxRoutingNotifier notifier); | |
0ead87c8 | 336 | void pci_device_reset(PCIDevice *dev); |
9bb33586 | 337 | void pci_bus_reset(PCIBus *bus); |
87ecb68b | 338 | |
5607c388 MA |
339 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
340 | const char *default_devaddr); | |
07caea31 MA |
341 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
342 | const char *default_devaddr); | |
129d42fb AJ |
343 | |
344 | PCIDevice *pci_vga_init(PCIBus *bus); | |
345 | ||
87ecb68b | 346 | int pci_bus_num(PCIBus *s); |
7aa8cbb9 AP |
347 | void pci_for_each_device(PCIBus *bus, int bus_num, |
348 | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), | |
349 | void *opaque); | |
c469e1dd | 350 | PCIBus *pci_find_root_bus(int domain); |
e075e788 | 351 | int pci_find_domain(const PCIBus *bus); |
5256d8bf | 352 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
f3006dd1 | 353 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
49bd1458 | 354 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
87ecb68b | 355 | |
e9283f8b JK |
356 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
357 | unsigned *slotp); | |
880345c4 | 358 | |
4c92325b IY |
359 | void pci_device_deassert_intx(PCIDevice *dev); |
360 | ||
5fa45de5 DG |
361 | typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); |
362 | ||
363 | void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); | |
364 | ||
64d50b8b MT |
365 | static inline void |
366 | pci_set_byte(uint8_t *config, uint8_t val) | |
367 | { | |
368 | *config = val; | |
369 | } | |
370 | ||
371 | static inline uint8_t | |
cb95c2e4 | 372 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
373 | { |
374 | return *config; | |
375 | } | |
376 | ||
14e12559 MT |
377 | static inline void |
378 | pci_set_word(uint8_t *config, uint16_t val) | |
379 | { | |
380 | cpu_to_le16wu((uint16_t *)config, val); | |
381 | } | |
382 | ||
383 | static inline uint16_t | |
cb95c2e4 | 384 | pci_get_word(const uint8_t *config) |
14e12559 | 385 | { |
cb95c2e4 | 386 | return le16_to_cpupu((const uint16_t *)config); |
14e12559 MT |
387 | } |
388 | ||
389 | static inline void | |
390 | pci_set_long(uint8_t *config, uint32_t val) | |
391 | { | |
392 | cpu_to_le32wu((uint32_t *)config, val); | |
393 | } | |
394 | ||
395 | static inline uint32_t | |
cb95c2e4 | 396 | pci_get_long(const uint8_t *config) |
14e12559 | 397 | { |
cb95c2e4 | 398 | return le32_to_cpupu((const uint32_t *)config); |
14e12559 MT |
399 | } |
400 | ||
fb5ce7d2 IY |
401 | static inline void |
402 | pci_set_quad(uint8_t *config, uint64_t val) | |
403 | { | |
404 | cpu_to_le64w((uint64_t *)config, val); | |
405 | } | |
406 | ||
407 | static inline uint64_t | |
cb95c2e4 | 408 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 409 | { |
cb95c2e4 | 410 | return le64_to_cpup((const uint64_t *)config); |
fb5ce7d2 IY |
411 | } |
412 | ||
deb54399 AL |
413 | static inline void |
414 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
415 | { | |
14e12559 | 416 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
417 | } |
418 | ||
419 | static inline void | |
420 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
421 | { | |
14e12559 | 422 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
423 | } |
424 | ||
cf602c7b IE |
425 | static inline void |
426 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
427 | { | |
428 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
429 | } | |
430 | ||
173a543b BS |
431 | static inline void |
432 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
433 | { | |
14e12559 | 434 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
435 | } |
436 | ||
cf602c7b IE |
437 | static inline void |
438 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
439 | { | |
440 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
441 | } | |
442 | ||
443 | static inline void | |
444 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
445 | { | |
446 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
447 | } | |
448 | ||
aabcf526 IY |
449 | /* |
450 | * helper functions to do bit mask operation on configuration space. | |
451 | * Just to set bit, use test-and-set and discard returned value. | |
452 | * Just to clear bit, use test-and-clear and discard returned value. | |
453 | * NOTE: They aren't atomic. | |
454 | */ | |
455 | static inline uint8_t | |
456 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) | |
457 | { | |
458 | uint8_t val = pci_get_byte(config); | |
459 | pci_set_byte(config, val & ~mask); | |
460 | return val & mask; | |
461 | } | |
462 | ||
463 | static inline uint8_t | |
464 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) | |
465 | { | |
466 | uint8_t val = pci_get_byte(config); | |
467 | pci_set_byte(config, val | mask); | |
468 | return val & mask; | |
469 | } | |
470 | ||
471 | static inline uint16_t | |
472 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) | |
473 | { | |
474 | uint16_t val = pci_get_word(config); | |
475 | pci_set_word(config, val & ~mask); | |
476 | return val & mask; | |
477 | } | |
478 | ||
479 | static inline uint16_t | |
480 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) | |
481 | { | |
482 | uint16_t val = pci_get_word(config); | |
483 | pci_set_word(config, val | mask); | |
484 | return val & mask; | |
485 | } | |
486 | ||
487 | static inline uint32_t | |
488 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) | |
489 | { | |
490 | uint32_t val = pci_get_long(config); | |
491 | pci_set_long(config, val & ~mask); | |
492 | return val & mask; | |
493 | } | |
494 | ||
495 | static inline uint32_t | |
496 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) | |
497 | { | |
498 | uint32_t val = pci_get_long(config); | |
499 | pci_set_long(config, val | mask); | |
500 | return val & mask; | |
501 | } | |
502 | ||
503 | static inline uint64_t | |
504 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) | |
505 | { | |
506 | uint64_t val = pci_get_quad(config); | |
507 | pci_set_quad(config, val & ~mask); | |
508 | return val & mask; | |
509 | } | |
510 | ||
511 | static inline uint64_t | |
512 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) | |
513 | { | |
514 | uint64_t val = pci_get_quad(config); | |
515 | pci_set_quad(config, val | mask); | |
516 | return val & mask; | |
517 | } | |
518 | ||
c9f50cea MT |
519 | /* Access a register specified by a mask */ |
520 | static inline void | |
521 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) | |
522 | { | |
523 | uint8_t val = pci_get_byte(config); | |
524 | uint8_t rval = reg << (ffs(mask) - 1); | |
525 | pci_set_byte(config, (~mask & val) | (mask & rval)); | |
526 | } | |
527 | ||
528 | static inline uint8_t | |
529 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) | |
530 | { | |
531 | uint8_t val = pci_get_byte(config); | |
532 | return (val & mask) >> (ffs(mask) - 1); | |
533 | } | |
534 | ||
535 | static inline void | |
536 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) | |
537 | { | |
538 | uint16_t val = pci_get_word(config); | |
539 | uint16_t rval = reg << (ffs(mask) - 1); | |
540 | pci_set_word(config, (~mask & val) | (mask & rval)); | |
541 | } | |
542 | ||
543 | static inline uint16_t | |
544 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) | |
545 | { | |
546 | uint16_t val = pci_get_word(config); | |
547 | return (val & mask) >> (ffs(mask) - 1); | |
548 | } | |
549 | ||
550 | static inline void | |
551 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) | |
552 | { | |
553 | uint32_t val = pci_get_long(config); | |
554 | uint32_t rval = reg << (ffs(mask) - 1); | |
555 | pci_set_long(config, (~mask & val) | (mask & rval)); | |
556 | } | |
557 | ||
558 | static inline uint32_t | |
559 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) | |
560 | { | |
561 | uint32_t val = pci_get_long(config); | |
562 | return (val & mask) >> (ffs(mask) - 1); | |
563 | } | |
564 | ||
565 | static inline void | |
566 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) | |
567 | { | |
568 | uint64_t val = pci_get_quad(config); | |
569 | uint64_t rval = reg << (ffs(mask) - 1); | |
570 | pci_set_quad(config, (~mask & val) | (mask & rval)); | |
571 | } | |
572 | ||
573 | static inline uint64_t | |
574 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) | |
575 | { | |
576 | uint64_t val = pci_get_quad(config); | |
577 | return (val & mask) >> (ffs(mask) - 1); | |
578 | } | |
579 | ||
49823868 IY |
580 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
581 | const char *name); | |
582 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, | |
583 | bool multifunction, | |
584 | const char *name); | |
499cf102 | 585 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
586 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
587 | ||
3c18685f | 588 | static inline int pci_is_express(const PCIDevice *d) |
a9f49946 IY |
589 | { |
590 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
591 | } | |
592 | ||
3c18685f | 593 | static inline uint32_t pci_config_size(const PCIDevice *d) |
a9f49946 IY |
594 | { |
595 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
596 | } | |
597 | ||
ec174575 | 598 | /* DMA access functions */ |
d86a77f8 DG |
599 | static inline DMAContext *pci_dma_context(PCIDevice *dev) |
600 | { | |
5fa45de5 | 601 | return dev->dma; |
d86a77f8 DG |
602 | } |
603 | ||
ec174575 DG |
604 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
605 | void *buf, dma_addr_t len, DMADirection dir) | |
606 | { | |
d86a77f8 | 607 | dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); |
ec174575 DG |
608 | return 0; |
609 | } | |
610 | ||
611 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, | |
612 | void *buf, dma_addr_t len) | |
613 | { | |
614 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); | |
615 | } | |
616 | ||
617 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, | |
618 | const void *buf, dma_addr_t len) | |
619 | { | |
620 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); | |
621 | } | |
622 | ||
623 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ | |
624 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ | |
625 | dma_addr_t addr) \ | |
626 | { \ | |
d86a77f8 | 627 | return ld##_l##_dma(pci_dma_context(dev), addr); \ |
ec174575 DG |
628 | } \ |
629 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ | |
d86a77f8 | 630 | dma_addr_t addr, uint##_bits##_t val) \ |
ec174575 | 631 | { \ |
d86a77f8 | 632 | st##_s##_dma(pci_dma_context(dev), addr, val); \ |
ec174575 DG |
633 | } |
634 | ||
635 | PCI_DMA_DEFINE_LDST(ub, b, 8); | |
636 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) | |
637 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); | |
638 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); | |
639 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) | |
640 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); | |
641 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); | |
642 | ||
643 | #undef PCI_DMA_DEFINE_LDST | |
644 | ||
645 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, | |
646 | dma_addr_t *plen, DMADirection dir) | |
647 | { | |
ec174575 DG |
648 | void *buf; |
649 | ||
d86a77f8 | 650 | buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); |
ec174575 DG |
651 | return buf; |
652 | } | |
653 | ||
654 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, | |
655 | DMADirection dir, dma_addr_t access_len) | |
656 | { | |
d86a77f8 | 657 | dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); |
ec174575 DG |
658 | } |
659 | ||
660 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, | |
661 | int alloc_hint) | |
662 | { | |
c65bcef3 | 663 | qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); |
ec174575 DG |
664 | } |
665 | ||
701a8f76 PB |
666 | extern const VMStateDescription vmstate_pci_device; |
667 | ||
668 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ | |
669 | .name = (stringify(_field)), \ | |
670 | .size = sizeof(PCIDevice), \ | |
671 | .vmsd = &vmstate_pci_device, \ | |
672 | .flags = VMS_STRUCT, \ | |
673 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ | |
674 | } | |
675 | ||
676 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ | |
677 | .name = (stringify(_field)), \ | |
678 | .size = sizeof(PCIDevice), \ | |
679 | .vmsd = &vmstate_pci_device, \ | |
680 | .flags = VMS_STRUCT|VMS_POINTER, \ | |
681 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ | |
682 | } | |
683 | ||
87ecb68b | 684 | #endif |