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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
4 | /* PCI includes legacy ISA access. */ | |
5 | #include "isa.h" | |
6 | ||
7 | /* PCI bus */ | |
8 | ||
9 | extern target_phys_addr_t pci_mem_base; | |
10 | ||
3ae80618 AL |
11 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
12 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
13 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
14 | ||
173a543b BS |
15 | /* Device classes and subclasses */ |
16 | ||
17 | #define PCI_CLASS_STORAGE_SCSI 0x0100 | |
18 | #define PCI_CLASS_STORAGE_IDE 0x0101 | |
19 | #define PCI_CLASS_STORAGE_OTHER 0x0180 | |
20 | ||
21 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 | |
22 | ||
23 | #define PCI_CLASS_DISPLAY_VGA 0x0300 | |
24 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 | |
25 | ||
26 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 | |
27 | ||
28 | #define PCI_CLASS_MEMORY_RAM 0x0500 | |
29 | ||
30 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 | |
31 | ||
32 | #define PCI_CLASS_SERIAL_USB 0x0c03 | |
33 | ||
34 | #define PCI_CLASS_BRIDGE_HOST 0x0600 | |
35 | #define PCI_CLASS_BRIDGE_ISA 0x0601 | |
36 | #define PCI_CLASS_BRIDGE_PCI 0x0604 | |
37 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 | |
38 | ||
39 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 | |
40 | ||
41 | #define PCI_CLASS_OTHERS 0xff | |
42 | ||
43 | /* Vendors and devices. */ | |
44 | ||
deb54399 AL |
45 | #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 |
46 | #define PCI_DEVICE_ID_LSI_53C895A 0x0012 | |
47 | ||
48 | #define PCI_VENDOR_ID_DEC 0x1011 | |
4ebcf884 | 49 | #define PCI_DEVICE_ID_DEC_21154 0x0026 |
deb54399 AL |
50 | |
51 | #define PCI_VENDOR_ID_CIRRUS 0x1013 | |
52 | ||
53 | #define PCI_VENDOR_ID_IBM 0x1014 | |
4ebcf884 | 54 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 AL |
55 | |
56 | #define PCI_VENDOR_ID_AMD 0x1022 | |
57 | #define PCI_DEVICE_ID_AMD_LANCE 0x2000 | |
58 | ||
59 | #define PCI_VENDOR_ID_HITACHI 0x1054 | |
60 | ||
61 | #define PCI_VENDOR_ID_MOTOROLA 0x1057 | |
62 | #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 | |
63 | #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 | |
64 | ||
65 | #define PCI_VENDOR_ID_APPLE 0x106b | |
4ebcf884 BS |
66 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
67 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
68 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
deb54399 | 69 | #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 |
4ebcf884 | 70 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
deb54399 AL |
71 | |
72 | #define PCI_VENDOR_ID_SUN 0x108e | |
73 | #define PCI_DEVICE_ID_SUN_EBUS 0x1000 | |
480b9f24 | 74 | #define PCI_DEVICE_ID_SUN_SIMBA 0x5000 |
deb54399 AL |
75 | #define PCI_DEVICE_ID_SUN_SABRE 0xa000 |
76 | ||
77 | #define PCI_VENDOR_ID_CMD 0x1095 | |
78 | #define PCI_DEVICE_ID_CMD_646 0x0646 | |
79 | ||
80 | #define PCI_VENDOR_ID_REALTEK 0x10ec | |
4ebcf884 | 81 | #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029 |
deb54399 AL |
82 | #define PCI_DEVICE_ID_REALTEK_8139 0x8139 |
83 | ||
84 | #define PCI_VENDOR_ID_XILINX 0x10ee | |
85 | ||
86 | #define PCI_VENDOR_ID_MARVELL 0x11ab | |
87 | ||
4ebcf884 BS |
88 | #define PCI_VENDOR_ID_QEMU 0x1234 |
89 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
90 | ||
deb54399 AL |
91 | #define PCI_VENDOR_ID_ENSONIQ 0x1274 |
92 | #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 | |
93 | ||
94 | #define PCI_VENDOR_ID_VMWARE 0x15ad | |
95 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
96 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
97 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
98 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
99 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
100 | ||
101 | #define PCI_VENDOR_ID_INTEL 0x8086 | |
102 | #define PCI_DEVICE_ID_INTEL_82441 0x1237 | |
103 | #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 | |
104 | #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 | |
105 | #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 | |
106 | #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 | |
107 | #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 | |
108 | #define PCI_DEVICE_ID_INTEL_82371AB 0x7111 | |
109 | #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 | |
110 | #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 | |
111 | ||
112 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ | |
d350d97d AL |
113 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
114 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
115 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
116 | ||
117 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
118 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
119 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 120 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
d350d97d | 121 | |
87ecb68b PB |
122 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
123 | uint32_t address, uint32_t data, int len); | |
124 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
125 | uint32_t address, int len); | |
126 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
127 | uint32_t addr, uint32_t size, int type); | |
128 | ||
129 | #define PCI_ADDRESS_SPACE_MEM 0x00 | |
130 | #define PCI_ADDRESS_SPACE_IO 0x01 | |
131 | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 | |
132 | ||
133 | typedef struct PCIIORegion { | |
134 | uint32_t addr; /* current PCI mapping address. -1 means not mapped */ | |
135 | uint32_t size; | |
136 | uint8_t type; | |
137 | PCIMapIORegionFunc *map_func; | |
138 | } PCIIORegion; | |
139 | ||
140 | #define PCI_ROM_SLOT 6 | |
141 | #define PCI_NUM_REGIONS 7 | |
142 | ||
143 | #define PCI_DEVICES_MAX 64 | |
144 | ||
145 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ | |
146 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
147 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
148 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
149 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
d350d97d | 150 | #define PCI_REVISION 0x08 |
87ecb68b | 151 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
d350d97d AL |
152 | #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */ |
153 | #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */ | |
87ecb68b PB |
154 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
155 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
156 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
157 | #define PCI_MAX_LAT 0x3f /* 8 bits */ | |
158 | ||
8098ed41 AJ |
159 | /* Bits in the PCI Status Register (PCI 2.3 spec) */ |
160 | #define PCI_STATUS_RESERVED1 0x007 | |
161 | #define PCI_STATUS_INT_STATUS 0x008 | |
162 | #define PCI_STATUS_CAPABILITIES 0x010 | |
163 | #define PCI_STATUS_66MHZ 0x020 | |
164 | #define PCI_STATUS_RESERVED2 0x040 | |
165 | #define PCI_STATUS_FAST_BACK 0x080 | |
166 | #define PCI_STATUS_DEVSEL 0x600 | |
167 | ||
168 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ | |
169 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ | |
170 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) | |
171 | ||
172 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) | |
173 | ||
475dc65f AJ |
174 | /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
175 | #define PCI_COMMAND_RESERVED 0xf800 | |
176 | ||
177 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) | |
178 | ||
87ecb68b PB |
179 | struct PCIDevice { |
180 | /* PCI config space */ | |
181 | uint8_t config[256]; | |
182 | ||
183 | /* the following fields are read only */ | |
184 | PCIBus *bus; | |
185 | int devfn; | |
186 | char name[64]; | |
187 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
188 | ||
189 | /* do not access the following fields */ | |
190 | PCIConfigReadFunc *config_read; | |
191 | PCIConfigWriteFunc *config_write; | |
192 | /* ??? This is a PC-specific hack, and should be removed. */ | |
193 | int irq_index; | |
194 | ||
195 | /* IRQ objects for the INTA-INTD pins. */ | |
196 | qemu_irq *irq; | |
197 | ||
198 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
199 | int irq_state[4]; | |
200 | }; | |
201 | ||
202 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
203 | int instance_size, int devfn, | |
204 | PCIConfigReadFunc *config_read, | |
205 | PCIConfigWriteFunc *config_write); | |
206 | ||
207 | void pci_register_io_region(PCIDevice *pci_dev, int region_num, | |
208 | uint32_t size, int type, | |
209 | PCIMapIORegionFunc *map_func); | |
210 | ||
211 | uint32_t pci_default_read_config(PCIDevice *d, | |
212 | uint32_t address, int len); | |
213 | void pci_default_write_config(PCIDevice *d, | |
214 | uint32_t address, uint32_t val, int len); | |
215 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
216 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
217 | ||
218 | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); | |
219 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); | |
220 | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
221 | qemu_irq *pic, int devfn_min, int nirq); | |
222 | ||
cb457d76 AL |
223 | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, |
224 | const char *default_model); | |
87ecb68b PB |
225 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
226 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); | |
227 | int pci_bus_num(PCIBus *s); | |
228 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); | |
3ae80618 AL |
229 | PCIBus *pci_find_bus(int bus_num); |
230 | PCIDevice *pci_find_device(int bus_num, int slot, int function); | |
87ecb68b PB |
231 | |
232 | void pci_info(void); | |
480b9f24 | 233 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
87ecb68b PB |
234 | pci_map_irq_fn map_irq, const char *name); |
235 | ||
deb54399 AL |
236 | static inline void |
237 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
238 | { | |
239 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val); | |
240 | } | |
241 | ||
242 | static inline void | |
243 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
244 | { | |
245 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val); | |
246 | } | |
247 | ||
173a543b BS |
248 | static inline void |
249 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
250 | { | |
251 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val); | |
252 | } | |
253 | ||
87ecb68b | 254 | /* lsi53c895a.c */ |
e4bcb14c | 255 | #define LSI_MAX_DEVS 7 |
87ecb68b PB |
256 | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
257 | void *lsi_scsi_init(PCIBus *bus, int devfn); | |
258 | ||
259 | /* vmware_vga.c */ | |
3023f332 | 260 | void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base, |
87ecb68b PB |
261 | unsigned long vga_ram_offset, int vga_ram_size); |
262 | ||
263 | /* usb-uhci.c */ | |
264 | void usb_uhci_piix3_init(PCIBus *bus, int devfn); | |
265 | void usb_uhci_piix4_init(PCIBus *bus, int devfn); | |
266 | ||
267 | /* usb-ohci.c */ | |
268 | void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn); | |
269 | ||
270 | /* eepro100.c */ | |
271 | ||
272 | void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); | |
273 | void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); | |
274 | void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); | |
275 | ||
276 | /* ne2000.c */ | |
277 | ||
278 | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); | |
279 | ||
280 | /* rtl8139.c */ | |
281 | ||
282 | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); | |
283 | ||
7c23b892 AZ |
284 | /* e1000.c */ |
285 | void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn); | |
286 | ||
87ecb68b PB |
287 | /* pcnet.c */ |
288 | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); | |
289 | ||
290 | /* prep_pci.c */ | |
291 | PCIBus *pci_prep_init(qemu_irq *pic); | |
292 | ||
293 | /* apb_pci.c */ | |
c190ea07 BS |
294 | PCIBus *pci_apb_init(target_phys_addr_t special_base, |
295 | target_phys_addr_t mem_base, | |
296 | qemu_irq *pic, PCIBus **bus2, PCIBus **bus3); | |
87ecb68b | 297 | |
b79e1752 AJ |
298 | /* sh_pci.c */ |
299 | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
300 | qemu_irq *pic, int devfn_min, int nirq); | |
301 | ||
87ecb68b | 302 | #endif |