[qemu.git] / hw / pci.h

#ifndef QEMU_PCI_H
#define QEMU_PCI_H

/* PCI includes legacy ISA access.  */
#include "isa.h"

/* PCI bus */

extern target_phys_addr_t pci_mem_base;

#define PCI_VENDOR_ID_LSI_LOGIC          0x1000
#define PCI_DEVICE_ID_LSI_53C895A        0x0012

#define PCI_VENDOR_ID_DEC                0x1011
#define PCI_DEVICE_ID_DEC_21154          0x0026

#define PCI_VENDOR_ID_CIRRUS             0x1013

#define PCI_VENDOR_ID_IBM                0x1014
#define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff

#define PCI_VENDOR_ID_AMD                0x1022
#define PCI_DEVICE_ID_AMD_LANCE          0x2000

#define PCI_VENDOR_ID_HITACHI            0x1054

#define PCI_VENDOR_ID_MOTOROLA           0x1057
#define PCI_DEVICE_ID_MOTOROLA_MPC106    0x0002
#define PCI_DEVICE_ID_MOTOROLA_RAVEN     0x4801

#define PCI_VENDOR_ID_APPLE              0x106b
#define PCI_DEVICE_ID_APPLE_343S1201     0x0010
#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP    0x0020
#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022

#define PCI_VENDOR_ID_SUN                0x108e
#define PCI_DEVICE_ID_SUN_EBUS           0x1000
#define PCI_DEVICE_ID_SUN_SIMBA          0x5000
#define PCI_DEVICE_ID_SUN_SABRE          0xa000

#define PCI_VENDOR_ID_CMD                0x1095
#define PCI_DEVICE_ID_CMD_646            0x0646

#define PCI_VENDOR_ID_REALTEK            0x10ec
#define PCI_DEVICE_ID_REALTEK_RTL8029    0x8029
#define PCI_DEVICE_ID_REALTEK_8139       0x8139

#define PCI_VENDOR_ID_XILINX             0x10ee

#define PCI_VENDOR_ID_MARVELL            0x11ab

#define PCI_VENDOR_ID_QEMU               0x1234
#define PCI_DEVICE_ID_QEMU_VGA           0x1111

#define PCI_VENDOR_ID_ENSONIQ            0x1274
#define PCI_DEVICE_ID_ENSONIQ_ES1370     0x5000

#define PCI_VENDOR_ID_VMWARE             0x15ad
#define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
#define PCI_DEVICE_ID_VMWARE_NET         0x0720
#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
#define PCI_DEVICE_ID_VMWARE_IDE         0x1729

#define PCI_VENDOR_ID_INTEL              0x8086
#define PCI_DEVICE_ID_INTEL_82441        0x1237
#define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
#define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
#define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
#define PCI_DEVICE_ID_INTEL_82371AB_0    0x7110
#define PCI_DEVICE_ID_INTEL_82371AB      0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
#define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113

/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
#define PCI_SUBDEVICE_ID_QEMU            0x1100

#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
#define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003

typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
                                uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
                                   uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
                                uint32_t addr, uint32_t size, int type);

#define PCI_ADDRESS_SPACE_MEM		0x00
#define PCI_ADDRESS_SPACE_IO		0x01
#define PCI_ADDRESS_SPACE_MEM_PREFETCH	0x08

typedef struct PCIIORegion {
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
    uint32_t size;
    uint8_t type;
    PCIMapIORegionFunc *map_func;
} PCIIORegion;

#define PCI_ROM_SLOT 6
#define PCI_NUM_REGIONS 7

#define PCI_DEVICES_MAX 64

#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define PCI_REVISION            0x08
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
#define PCI_SUBVENDOR_ID	0x2c	/* 16 bits */
#define PCI_SUBDEVICE_ID	0x2e	/* 16 bits */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

/* Bits in the PCI Status Register (PCI 2.3 spec) */
#define PCI_STATUS_RESERVED1	0x007
#define PCI_STATUS_INT_STATUS	0x008
#define PCI_STATUS_CAPABILITIES	0x010
#define PCI_STATUS_66MHZ	0x020
#define PCI_STATUS_RESERVED2	0x040
#define PCI_STATUS_FAST_BACK	0x080
#define PCI_STATUS_DEVSEL	0x600

#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
                PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
                PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)

#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)

/* Bits in the PCI Command Register (PCI 2.3 spec) */
#define PCI_COMMAND_RESERVED	0xf800

#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)

struct PCIDevice {
    /* PCI config space */
    uint8_t config[256];

    /* the following fields are read only */
    PCIBus *bus;
    int devfn;
    char name[64];
    PCIIORegion io_regions[PCI_NUM_REGIONS];

    /* do not access the following fields */
    PCIConfigReadFunc *config_read;
    PCIConfigWriteFunc *config_write;
    /* ??? This is a PC-specific hack, and should be removed.  */
    int irq_index;

    /* IRQ objects for the INTA-INTD pins.  */
    qemu_irq *irq;

    /* Current IRQ levels.  Used internally by the generic PCI code.  */
    int irq_state[4];
};

PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                               int instance_size, int devfn,
                               PCIConfigReadFunc *config_read,
                               PCIConfigWriteFunc *config_write);

void pci_register_io_region(PCIDevice *pci_dev, int region_num,
                            uint32_t size, int type,
                            PCIMapIORegionFunc *map_func);

uint32_t pci_default_read_config(PCIDevice *d,
                                 uint32_t address, int len);
void pci_default_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);

typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                         qemu_irq *pic, int devfn_min, int nirq);

void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
                  const char *default_model);
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
int pci_bus_num(PCIBus *s);
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));

void pci_info(void);
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
                        pci_map_irq_fn map_irq, const char *name);

static inline void
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
}

static inline void
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
{
    cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
}

/* lsi53c895a.c */
#define LSI_MAX_DEVS 7
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *lsi_scsi_init(PCIBus *bus, int devfn);

/* vmware_vga.c */
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
                     unsigned long vga_ram_offset, int vga_ram_size);

/* usb-uhci.c */
void usb_uhci_piix3_init(PCIBus *bus, int devfn);
void usb_uhci_piix4_init(PCIBus *bus, int devfn);

/* usb-ohci.c */
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);

/* eepro100.c */

void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);

/* ne2000.c */

void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* rtl8139.c */

void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);

/* e1000.c */
void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* pcnet.c */
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

/* prep_pci.c */
PCIBus *pci_prep_init(qemu_irq *pic);

/* apb_pci.c */
PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);

/* sh_pci.c */
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                            qemu_irq *pic, int devfn_min, int nirq);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef QEMU_PCI_H
	2	#define QEMU_PCI_H
	3
	4	/* PCI includes legacy ISA access. */
	5	#include "isa.h"
	6
	7	/* PCI bus */
	8
	9	extern target_phys_addr_t pci_mem_base;
	10
deb54399 AL	11	#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
	12	#define PCI_DEVICE_ID_LSI_53C895A 0x0012
	13
	14	#define PCI_VENDOR_ID_DEC 0x1011
4ebcf884	15	#define PCI_DEVICE_ID_DEC_21154 0x0026
deb54399 AL	16
	17	#define PCI_VENDOR_ID_CIRRUS 0x1013
	18
	19	#define PCI_VENDOR_ID_IBM 0x1014
4ebcf884	20	#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
deb54399 AL	21
	22	#define PCI_VENDOR_ID_AMD 0x1022
	23	#define PCI_DEVICE_ID_AMD_LANCE 0x2000
	24
	25	#define PCI_VENDOR_ID_HITACHI 0x1054
	26
	27	#define PCI_VENDOR_ID_MOTOROLA 0x1057
	28	#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
	29	#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
	30
	31	#define PCI_VENDOR_ID_APPLE 0x106b
4ebcf884 BS	32	#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
	33	#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
	34	#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
deb54399	35	#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
4ebcf884	36	#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
deb54399 AL	37
	38	#define PCI_VENDOR_ID_SUN 0x108e
	39	#define PCI_DEVICE_ID_SUN_EBUS 0x1000
480b9f24	40	#define PCI_DEVICE_ID_SUN_SIMBA 0x5000
deb54399 AL	41	#define PCI_DEVICE_ID_SUN_SABRE 0xa000
	42
	43	#define PCI_VENDOR_ID_CMD 0x1095
	44	#define PCI_DEVICE_ID_CMD_646 0x0646
	45
	46	#define PCI_VENDOR_ID_REALTEK 0x10ec
4ebcf884	47	#define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029
deb54399 AL	48	#define PCI_DEVICE_ID_REALTEK_8139 0x8139
	49
	50	#define PCI_VENDOR_ID_XILINX 0x10ee
	51
	52	#define PCI_VENDOR_ID_MARVELL 0x11ab
	53
4ebcf884 BS	54	#define PCI_VENDOR_ID_QEMU 0x1234
	55	#define PCI_DEVICE_ID_QEMU_VGA 0x1111
	56
deb54399 AL	57	#define PCI_VENDOR_ID_ENSONIQ 0x1274
	58	#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
	59
	60	#define PCI_VENDOR_ID_VMWARE 0x15ad
	61	#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
	62	#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
	63	#define PCI_DEVICE_ID_VMWARE_NET 0x0720
	64	#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
	65	#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
	66
	67	#define PCI_VENDOR_ID_INTEL 0x8086
	68	#define PCI_DEVICE_ID_INTEL_82441 0x1237
	69	#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
	70	#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
	71	#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
	72	#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
	73	#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
	74	#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
	75	#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
	76	#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
	77
	78	/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
d350d97d AL	79	#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
	80	#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
	81	#define PCI_SUBDEVICE_ID_QEMU 0x1100
	82
	83	#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
	84	#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
	85	#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
14d50bef	86	#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
d350d97d	87
87ecb68b PB	88	typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
	89	uint32_t address, uint32_t data, int len);
	90	typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
	91	uint32_t address, int len);
	92	typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
	93	uint32_t addr, uint32_t size, int type);
	94
	95	#define PCI_ADDRESS_SPACE_MEM 0x00
	96	#define PCI_ADDRESS_SPACE_IO 0x01
	97	#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
	98
	99	typedef struct PCIIORegion {
	100	uint32_t addr; /* current PCI mapping address. -1 means not mapped */
	101	uint32_t size;
	102	uint8_t type;
	103	PCIMapIORegionFunc *map_func;
	104	} PCIIORegion;
	105
	106	#define PCI_ROM_SLOT 6
	107	#define PCI_NUM_REGIONS 7
	108
	109	#define PCI_DEVICES_MAX 64
	110
	111	#define PCI_VENDOR_ID 0x00 /* 16 bits */
	112	#define PCI_DEVICE_ID 0x02 /* 16 bits */
	113	#define PCI_COMMAND 0x04 /* 16 bits */
	114	#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	115	#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
d350d97d	116	#define PCI_REVISION 0x08
87ecb68b	117	#define PCI_CLASS_DEVICE 0x0a /* Device class */
d350d97d AL	118	#define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
d350d97d AL	119	#define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
87ecb68b PB	120	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
	121	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
	122	#define PCI_MIN_GNT 0x3e /* 8 bits */
	123	#define PCI_MAX_LAT 0x3f /* 8 bits */
	124
8098ed41 AJ	125	/* Bits in the PCI Status Register (PCI 2.3 spec) */
	126	#define PCI_STATUS_RESERVED1 0x007
	127	#define PCI_STATUS_INT_STATUS 0x008
	128	#define PCI_STATUS_CAPABILITIES 0x010
	129	#define PCI_STATUS_66MHZ 0x020
	130	#define PCI_STATUS_RESERVED2 0x040
	131	#define PCI_STATUS_FAST_BACK 0x080
	132	#define PCI_STATUS_DEVSEL 0x600
	133
	134	#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 \| \
	135	PCI_STATUS_INT_STATUS \| PCI_STATUS_CAPABILITIES \| \
	136	PCI_STATUS_66MHZ \| PCI_STATUS_RESERVED2 \| PCI_STATUS_FAST_BACK)
	137
	138	#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
	139
475dc65f AJ	140	/* Bits in the PCI Command Register (PCI 2.3 spec) */
	141	#define PCI_COMMAND_RESERVED 0xf800
	142
	143	#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
	144
87ecb68b PB	145	struct PCIDevice {
	146	/* PCI config space */
	147	uint8_t config[256];
	148
	149	/* the following fields are read only */
	150	PCIBus *bus;
	151	int devfn;
	152	char name[64];
	153	PCIIORegion io_regions[PCI_NUM_REGIONS];
	154
	155	/* do not access the following fields */
	156	PCIConfigReadFunc *config_read;
	157	PCIConfigWriteFunc *config_write;
	158	/* ??? This is a PC-specific hack, and should be removed. */
	159	int irq_index;
	160
	161	/* IRQ objects for the INTA-INTD pins. */
	162	qemu_irq *irq;
	163
	164	/* Current IRQ levels. Used internally by the generic PCI code. */
	165	int irq_state[4];
	166	};
	167
	168	PCIDevice pci_register_device(PCIBus bus, const char *name,
	169	int instance_size, int devfn,
	170	PCIConfigReadFunc *config_read,
	171	PCIConfigWriteFunc *config_write);
	172
	173	void pci_register_io_region(PCIDevice *pci_dev, int region_num,
	174	uint32_t size, int type,
	175	PCIMapIORegionFunc *map_func);
	176
	177	uint32_t pci_default_read_config(PCIDevice *d,
	178	uint32_t address, int len);
	179	void pci_default_write_config(PCIDevice *d,
	180	uint32_t address, uint32_t val, int len);
	181	void pci_device_save(PCIDevice s, QEMUFile f);
	182	int pci_device_load(PCIDevice s, QEMUFile f);
	183
	184	typedef void (pci_set_irq_fn)(qemu_irq pic, int irq_num, int level);
	185	typedef int (pci_map_irq_fn)(PCIDevice pci_dev, int irq_num);
	186	PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	187	qemu_irq *pic, int devfn_min, int nirq);
	188
cb457d76 AL	189	void pci_nic_init(PCIBus bus, NICInfo nd, int devfn,
cb457d76 AL	190	const char *default_model);
87ecb68b PB	191	void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
	192	uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
	193	int pci_bus_num(PCIBus *s);
	194	void pci_for_each_device(int bus_num, void (fn)(PCIDevice d));
	195
	196	void pci_info(void);
480b9f24	197	PCIBus pci_bridge_init(PCIBus bus, int devfn, uint16_t vid, uint16_t did,
87ecb68b PB	198	pci_map_irq_fn map_irq, const char *name);
87ecb68b PB	199
deb54399 AL	200	static inline void
	201	pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
	202	{
	203	cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
	204	}
	205
	206	static inline void
	207	pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
	208	{
	209	cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
	210	}
	211
87ecb68b	212	/* lsi53c895a.c */
e4bcb14c	213	#define LSI_MAX_DEVS 7
87ecb68b PB	214	void lsi_scsi_attach(void opaque, BlockDriverState bd, int id);
	215	void lsi_scsi_init(PCIBus bus, int devfn);
	216
	217	/* vmware_vga.c */
3023f332	218	void pci_vmsvga_init(PCIBus bus, uint8_t vga_ram_base,
87ecb68b PB	219	unsigned long vga_ram_offset, int vga_ram_size);
	220
	221	/* usb-uhci.c */
	222	void usb_uhci_piix3_init(PCIBus *bus, int devfn);
	223	void usb_uhci_piix4_init(PCIBus *bus, int devfn);
	224
	225	/* usb-ohci.c */
	226	void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
	227
	228	/* eepro100.c */
	229
	230	void pci_i82551_init(PCIBus bus, NICInfo nd, int devfn);
	231	void pci_i82557b_init(PCIBus bus, NICInfo nd, int devfn);
	232	void pci_i82559er_init(PCIBus bus, NICInfo nd, int devfn);
	233
	234	/* ne2000.c */
	235
	236	void pci_ne2000_init(PCIBus bus, NICInfo nd, int devfn);
	237
	238	/* rtl8139.c */
	239
	240	void pci_rtl8139_init(PCIBus bus, NICInfo nd, int devfn);
	241
7c23b892 AZ	242	/* e1000.c */
	243	void pci_e1000_init(PCIBus bus, NICInfo nd, int devfn);
	244
87ecb68b PB	245	/* pcnet.c */
	246	void pci_pcnet_init(PCIBus bus, NICInfo nd, int devfn);
	247
	248	/* prep_pci.c */
	249	PCIBus pci_prep_init(qemu_irq pic);
	250
	251	/* apb_pci.c */
c190ea07 BS	252	PCIBus *pci_apb_init(target_phys_addr_t special_base,
	253	target_phys_addr_t mem_base,
	254	qemu_irq pic, PCIBus bus2, PCIBus *bus3);
87ecb68b	255
b79e1752 AJ	256	/* sh_pci.c */
	257	PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
	258	qemu_irq *pic, int devfn_min, int nirq);
	259
87ecb68b	260	#endif