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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
6b1b92d3 PB |
6 | #include "qdev.h" |
7 | ||
87ecb68b PB |
8 | /* PCI includes legacy ISA access. */ |
9 | #include "isa.h" | |
10 | ||
11 | /* PCI bus */ | |
12 | ||
13 | extern target_phys_addr_t pci_mem_base; | |
14 | ||
3ae80618 AL |
15 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
16 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
17 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
18 | ||
a770dc7e AL |
19 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
20 | #include "pci_ids.h" | |
173a543b | 21 | |
a770dc7e | 22 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 23 | |
a770dc7e AL |
24 | /* IBM (0x1014) */ |
25 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 26 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 27 | |
a770dc7e | 28 | /* Hitachi (0x1054) */ |
deb54399 | 29 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 30 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 31 | |
a770dc7e | 32 | /* Apple (0x106b) */ |
4ebcf884 BS |
33 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
34 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
35 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 36 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 37 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 38 | |
a770dc7e AL |
39 | /* Realtek (0x10ec) */ |
40 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 41 | |
a770dc7e AL |
42 | /* Xilinx (0x10ee) */ |
43 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 44 | |
a770dc7e AL |
45 | /* Marvell (0x11ab) */ |
46 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 47 | |
a770dc7e | 48 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
49 | #define PCI_VENDOR_ID_QEMU 0x1234 |
50 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
51 | ||
a770dc7e | 52 | /* VMWare (0x15ad) */ |
deb54399 AL |
53 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
54 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
55 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
56 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
57 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
58 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
59 | ||
cef3017c | 60 | /* Intel (0x8086) */ |
a770dc7e | 61 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
74c62ba8 | 62 | |
deb54399 | 63 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
64 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
65 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
66 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
67 | ||
68 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
69 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
70 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 71 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
d350d97d | 72 | |
87ecb68b PB |
73 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
74 | uint32_t address, uint32_t data, int len); | |
75 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
76 | uint32_t address, int len); | |
77 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
78 | uint32_t addr, uint32_t size, int type); | |
5851e08c | 79 | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b PB |
80 | |
81 | #define PCI_ADDRESS_SPACE_MEM 0x00 | |
82 | #define PCI_ADDRESS_SPACE_IO 0x01 | |
83 | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 | |
84 | ||
85 | typedef struct PCIIORegion { | |
86 | uint32_t addr; /* current PCI mapping address. -1 means not mapped */ | |
87 | uint32_t size; | |
88 | uint8_t type; | |
89 | PCIMapIORegionFunc *map_func; | |
90 | } PCIIORegion; | |
91 | ||
92 | #define PCI_ROM_SLOT 6 | |
93 | #define PCI_NUM_REGIONS 7 | |
94 | ||
cef3017c | 95 | /* Declarations from linux/pci_regs.h */ |
87ecb68b PB |
96 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
97 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
98 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
99 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
100 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
b7ee1603 | 101 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ |
cef3017c AL |
102 | #define PCI_STATUS 0x06 /* 16 bits */ |
103 | #define PCI_REVISION_ID 0x08 /* 8 bits */ | |
bd4b65ee | 104 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
87ecb68b | 105 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
b7ee1603 MT |
106 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
107 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ | |
cef3017c | 108 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
6407f373 IY |
109 | #define PCI_HEADER_TYPE_NORMAL 0 |
110 | #define PCI_HEADER_TYPE_BRIDGE 1 | |
111 | #define PCI_HEADER_TYPE_CARDBUS 2 | |
112 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 | |
b7ee1603 MT |
113 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
114 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ | |
115 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ | |
116 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ | |
cef3017c AL |
117 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ |
118 | #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ | |
b7ee1603 | 119 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
87ecb68b PB |
120 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
121 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
122 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
123 | #define PCI_MAX_LAT 0x3f /* 8 bits */ | |
124 | ||
6f4cbd39 MT |
125 | /* Capability lists */ |
126 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ | |
127 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ | |
128 | ||
cef3017c AL |
129 | #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ |
130 | #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ | |
131 | #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ | |
132 | ||
8098ed41 AJ |
133 | /* Bits in the PCI Status Register (PCI 2.3 spec) */ |
134 | #define PCI_STATUS_RESERVED1 0x007 | |
135 | #define PCI_STATUS_INT_STATUS 0x008 | |
6f4cbd39 | 136 | #define PCI_STATUS_CAP_LIST 0x010 |
8098ed41 AJ |
137 | #define PCI_STATUS_66MHZ 0x020 |
138 | #define PCI_STATUS_RESERVED2 0x040 | |
139 | #define PCI_STATUS_FAST_BACK 0x080 | |
140 | #define PCI_STATUS_DEVSEL 0x600 | |
141 | ||
142 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ | |
143 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ | |
144 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) | |
145 | ||
146 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) | |
147 | ||
475dc65f AJ |
148 | /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
149 | #define PCI_COMMAND_RESERVED 0xf800 | |
150 | ||
151 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) | |
152 | ||
b7ee1603 MT |
153 | /* Size of the standard PCI config header */ |
154 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
155 | /* Size of the standard PCI config space */ | |
156 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
157 | ||
02eb84d0 MT |
158 | /* Bits in cap_present field. */ |
159 | enum { | |
160 | QEMU_PCI_CAP_MSIX = 0x1, | |
161 | }; | |
162 | ||
87ecb68b | 163 | struct PCIDevice { |
6b1b92d3 | 164 | DeviceState qdev; |
87ecb68b | 165 | /* PCI config space */ |
b7ee1603 MT |
166 | uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
167 | ||
bd4b65ee MT |
168 | /* Used to enable config checks on load. Note that writeable bits are |
169 | * never checked even if set in cmask. */ | |
170 | uint8_t cmask[PCI_CONFIG_SPACE_SIZE]; | |
171 | ||
b7ee1603 MT |
172 | /* Used to implement R/W bytes */ |
173 | uint8_t wmask[PCI_CONFIG_SPACE_SIZE]; | |
87ecb68b | 174 | |
6f4cbd39 MT |
175 | /* Used to allocate config space for capabilities. */ |
176 | uint8_t used[PCI_CONFIG_SPACE_SIZE]; | |
177 | ||
87ecb68b PB |
178 | /* the following fields are read only */ |
179 | PCIBus *bus; | |
180 | int devfn; | |
181 | char name[64]; | |
182 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
183 | ||
184 | /* do not access the following fields */ | |
185 | PCIConfigReadFunc *config_read; | |
186 | PCIConfigWriteFunc *config_write; | |
5851e08c | 187 | PCIUnregisterFunc *unregister; |
87ecb68b PB |
188 | |
189 | /* IRQ objects for the INTA-INTD pins. */ | |
190 | qemu_irq *irq; | |
191 | ||
192 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
193 | int irq_state[4]; | |
02eb84d0 MT |
194 | |
195 | /* Capability bits */ | |
196 | uint32_t cap_present; | |
197 | ||
198 | /* Offset of MSI-X capability in config space */ | |
199 | uint8_t msix_cap; | |
200 | ||
201 | /* MSI-X entries */ | |
202 | int msix_entries_nr; | |
203 | ||
204 | /* Space to store MSIX table */ | |
205 | uint8_t *msix_table_page; | |
206 | /* MMIO index used to map MSIX table and pending bit entries. */ | |
207 | int msix_mmio_index; | |
208 | /* Reference-count for entries actually in use by driver. */ | |
209 | unsigned *msix_entry_used; | |
210 | /* Region including the MSI-X table */ | |
211 | uint32_t msix_bar_size; | |
87ecb68b PB |
212 | }; |
213 | ||
214 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
215 | int instance_size, int devfn, | |
216 | PCIConfigReadFunc *config_read, | |
217 | PCIConfigWriteFunc *config_write); | |
5851e08c | 218 | int pci_unregister_device(PCIDevice *pci_dev); |
87ecb68b | 219 | |
28c2c264 | 220 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
87ecb68b PB |
221 | uint32_t size, int type, |
222 | PCIMapIORegionFunc *map_func); | |
223 | ||
6f4cbd39 MT |
224 | int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); |
225 | ||
226 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
227 | ||
228 | void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size); | |
229 | ||
230 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); | |
231 | ||
232 | ||
87ecb68b PB |
233 | uint32_t pci_default_read_config(PCIDevice *d, |
234 | uint32_t address, int len); | |
235 | void pci_default_write_config(PCIDevice *d, | |
236 | uint32_t address, uint32_t val, int len); | |
237 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
238 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
239 | ||
240 | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); | |
241 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); | |
02e2da45 PB |
242 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
243 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
87ecb68b PB |
244 | qemu_irq *pic, int devfn_min, int nirq); |
245 | ||
5607c388 MA |
246 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
247 | const char *default_devaddr); | |
87ecb68b PB |
248 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
249 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); | |
250 | int pci_bus_num(PCIBus *s); | |
251 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); | |
3ae80618 AL |
252 | PCIBus *pci_find_bus(int bus_num); |
253 | PCIDevice *pci_find_device(int bus_num, int slot, int function); | |
87ecb68b | 254 | |
880345c4 | 255 | int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp); |
880345c4 | 256 | |
376253ec | 257 | void pci_info(Monitor *mon); |
480b9f24 | 258 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
87ecb68b PB |
259 | pci_map_irq_fn map_irq, const char *name); |
260 | ||
64d50b8b MT |
261 | static inline void |
262 | pci_set_byte(uint8_t *config, uint8_t val) | |
263 | { | |
264 | *config = val; | |
265 | } | |
266 | ||
267 | static inline uint8_t | |
268 | pci_get_byte(uint8_t *config) | |
269 | { | |
270 | return *config; | |
271 | } | |
272 | ||
14e12559 MT |
273 | static inline void |
274 | pci_set_word(uint8_t *config, uint16_t val) | |
275 | { | |
276 | cpu_to_le16wu((uint16_t *)config, val); | |
277 | } | |
278 | ||
279 | static inline uint16_t | |
280 | pci_get_word(uint8_t *config) | |
281 | { | |
282 | return le16_to_cpupu((uint16_t *)config); | |
283 | } | |
284 | ||
285 | static inline void | |
286 | pci_set_long(uint8_t *config, uint32_t val) | |
287 | { | |
288 | cpu_to_le32wu((uint32_t *)config, val); | |
289 | } | |
290 | ||
291 | static inline uint32_t | |
292 | pci_get_long(uint8_t *config) | |
293 | { | |
294 | return le32_to_cpupu((uint32_t *)config); | |
295 | } | |
296 | ||
deb54399 AL |
297 | static inline void |
298 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
299 | { | |
14e12559 | 300 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
301 | } |
302 | ||
303 | static inline void | |
304 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
305 | { | |
14e12559 | 306 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
307 | } |
308 | ||
173a543b BS |
309 | static inline void |
310 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
311 | { | |
14e12559 | 312 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
313 | } |
314 | ||
6b1b92d3 PB |
315 | typedef void (*pci_qdev_initfn)(PCIDevice *dev); |
316 | void pci_qdev_register(const char *name, int size, pci_qdev_initfn init); | |
317 | ||
1f5f6638 | 318 | PCIDevice *pci_create(const char *name, const char *devaddr); |
6b1b92d3 PB |
319 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
320 | ||
87ecb68b | 321 | /* lsi53c895a.c */ |
e4bcb14c | 322 | #define LSI_MAX_DEVS 7 |
9be5dafe | 323 | void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id); |
87ecb68b PB |
324 | |
325 | /* vmware_vga.c */ | |
fbe1b595 | 326 | void pci_vmsvga_init(PCIBus *bus); |
87ecb68b PB |
327 | |
328 | /* usb-uhci.c */ | |
329 | void usb_uhci_piix3_init(PCIBus *bus, int devfn); | |
330 | void usb_uhci_piix4_init(PCIBus *bus, int devfn); | |
331 | ||
332 | /* usb-ohci.c */ | |
333 | void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn); | |
334 | ||
87ecb68b PB |
335 | /* prep_pci.c */ |
336 | PCIBus *pci_prep_init(qemu_irq *pic); | |
337 | ||
338 | /* apb_pci.c */ | |
c190ea07 BS |
339 | PCIBus *pci_apb_init(target_phys_addr_t special_base, |
340 | target_phys_addr_t mem_base, | |
341 | qemu_irq *pic, PCIBus **bus2, PCIBus **bus3); | |
87ecb68b | 342 | |
b79e1752 AJ |
343 | /* sh_pci.c */ |
344 | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
345 | qemu_irq *pic, int devfn_min, int nirq); | |
346 | ||
87ecb68b | 347 | #endif |