[qemu.git] / hw / pci_internals.h

#ifndef QEMU_PCI_INTERNALS_H
#define QEMU_PCI_INTERNALS_H

/*
 * This header files is private to pci.c and pci_bridge.c
 * So following structures are opaque to others and shouldn't be
 * accessed.
 *
 * For pci-to-pci bridge needs to include this header file to embed
 * PCIBridge in its structure or to get sizeof(PCIBridge),
 * However, they shouldn't access those following members directly.
 * Use accessor function in pci.h, pci_bridge.h
 */

extern struct BusInfo pci_bus_info;

struct PCIBus {
    BusState qbus;
    uint8_t devfn_min;
    pci_set_irq_fn set_irq;
    pci_map_irq_fn map_irq;
    pci_hotplug_fn hotplug;
    DeviceState *hotplug_qdev;
    void *irq_opaque;
    PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
    PCIDevice *parent_dev;
    target_phys_addr_t mem_base;

    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */

    /* The bus IRQ state is the logical OR of the connected devices.
       Keep a count of the number of devices with raised IRQs.  */
    int nirq;
    int *irq_count;
};

struct PCIBridge {
    PCIDevice dev;

    /* private member */
    PCIBus sec_bus;
    pci_map_irq_fn map_irq;
    const char *bus_name;
};

#endif /* QEMU_PCI_INTERNALS_H */
Commit	Line	Data
cfb0a50a IY	1	#ifndef QEMU_PCI_INTERNALS_H
	2	#define QEMU_PCI_INTERNALS_H
	3
	4	/*
	5	* This header files is private to pci.c and pci_bridge.c
	6	* So following structures are opaque to others and shouldn't be
	7	* accessed.
68f79994 IY	8	*
	9	* For pci-to-pci bridge needs to include this header file to embed
	10	* PCIBridge in its structure or to get sizeof(PCIBridge),
	11	* However, they shouldn't access those following members directly.
	12	* Use accessor function in pci.h, pci_bridge.h
cfb0a50a IY	13	*/
	14
	15	extern struct BusInfo pci_bus_info;
	16
	17	struct PCIBus {
	18	BusState qbus;
6f3279b5	19	uint8_t devfn_min;
cfb0a50a IY	20	pci_set_irq_fn set_irq;
	21	pci_map_irq_fn map_irq;
	22	pci_hotplug_fn hotplug;
	23	DeviceState *hotplug_qdev;
	24	void *irq_opaque;
90a20dbb	25	PCIDevice devices[PCI_SLOT_MAX PCI_FUNC_MAX];
cfb0a50a IY	26	PCIDevice *parent_dev;
	27	target_phys_addr_t mem_base;
	28
	29	QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
	30	QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
	31
	32	/* The bus IRQ state is the logical OR of the connected devices.
	33	Keep a count of the number of devices with raised IRQs. */
	34	int nirq;
	35	int *irq_count;
	36	};
	37
68f79994	38	struct PCIBridge {
cfb0a50a	39	PCIDevice dev;
68f79994 IY	40
68f79994 IY	41	/* private member */
7e98e3af	42	PCIBus sec_bus;
68f79994 IY	43	pci_map_irq_fn map_irq;
	44	const char *bus_name;
	45	};
cfb0a50a IY	46
cfb0a50a IY	47	#endif /* QEMU_PCI_INTERNALS_H */