[qemu.git] / hw / pcie_regs.h

/*
 * constants for pcie configurations space from pci express spec.
 *
 * TODO:
 * Those constants and macros should go to Linux pci_regs.h
 * Once they're merged, they will go away.
 */
#ifndef QEMU_PCIE_REGS_H
#define QEMU_PCIE_REGS_H


/* express capability */

#define PCI_EXP_VER2_SIZEOF             0x3c /* express capability of ver. 2 */
#define PCI_EXT_CAP_VER_SHIFT           16
#define PCI_EXT_CAP_NEXT_SHIFT          20
#define PCI_EXT_CAP_NEXT_MASK           (0xffc << PCI_EXT_CAP_NEXT_SHIFT)

#define PCI_EXT_CAP(id, ver, next)                                      \
    ((id) |                                                             \
     ((ver) << PCI_EXT_CAP_VER_SHIFT) |                                 \
     ((next) << PCI_EXT_CAP_NEXT_SHIFT))

#define PCI_EXT_CAP_ALIGN               4
#define PCI_EXT_CAP_ALIGNUP(x)                                  \
    (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))

/* PCI_EXP_FLAGS */
#define PCI_EXP_FLAGS_VER2              2 /* for now, supports only ver. 2 */
#define PCI_EXP_FLAGS_IRQ_SHIFT         (ffs(PCI_EXP_FLAGS_IRQ) - 1)
#define PCI_EXP_FLAGS_TYPE_SHIFT        (ffs(PCI_EXP_FLAGS_TYPE) - 1)


/* PCI_EXP_LINK{CAP, STA} */
/* link speed */
#define PCI_EXP_LNK_LS_25               1

#define PCI_EXP_LNK_MLW_SHIFT           (ffs(PCI_EXP_LNKCAP_MLW) - 1)
#define PCI_EXP_LNK_MLW_1               (1 << PCI_EXP_LNK_MLW_SHIFT)

/* PCI_EXP_LINKCAP */
#define PCI_EXP_LNKCAP_ASPMS_SHIFT      (ffs(PCI_EXP_LNKCAP_ASPMS) - 1)
#define PCI_EXP_LNKCAP_ASPMS_0S         (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)

#define PCI_EXP_LNKCAP_PN_SHIFT         (ffs(PCI_EXP_LNKCAP_PN) - 1)

#define PCI_EXP_SLTCAP_PSN_SHIFT        (ffs(PCI_EXP_SLTCAP_PSN) - 1)

#define PCI_EXP_SLTCTL_IND_RESERVED     0x0
#define PCI_EXP_SLTCTL_IND_ON           0x1
#define PCI_EXP_SLTCTL_IND_BLINK        0x2
#define PCI_EXP_SLTCTL_IND_OFF          0x3
#define PCI_EXP_SLTCTL_AIC_SHIFT        (ffs(PCI_EXP_SLTCTL_AIC) - 1)
#define PCI_EXP_SLTCTL_AIC_OFF                          \
    (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT)

#define PCI_EXP_SLTCTL_PIC_SHIFT        (ffs(PCI_EXP_SLTCTL_PIC) - 1)
#define PCI_EXP_SLTCTL_PIC_OFF                          \
    (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT)

#define PCI_EXP_SLTCTL_SUPPORTED        \
            (PCI_EXP_SLTCTL_ABPE |      \
             PCI_EXP_SLTCTL_PDCE |      \
             PCI_EXP_SLTCTL_CCIE |      \
             PCI_EXP_SLTCTL_HPIE |      \
             PCI_EXP_SLTCTL_AIC |       \
             PCI_EXP_SLTCTL_PCC |       \
             PCI_EXP_SLTCTL_EIC)

#define PCI_EXP_DEVCAP2_EFF             0x100000
#define PCI_EXP_DEVCAP2_EETLPP          0x200000

#define PCI_EXP_DEVCTL2_EETLPPB         0x80

/* ARI */
#define PCI_ARI_VER                     1
#define PCI_ARI_SIZEOF                  8

/* AER */
#define PCI_ERR_VER                     2
#define PCI_ERR_SIZEOF                  0x48

#define PCI_ERR_UNC_SDN                 0x00000020      /* surprise down */
#define PCI_ERR_UNC_ACSV                0x00200000      /* ACS Violation */
#define PCI_ERR_UNC_INTN                0x00400000      /* Internal Error */
#define PCI_ERR_UNC_MCBTLP              0x00800000      /* MC Blcoked TLP */
#define PCI_ERR_UNC_ATOP_EBLOCKED       0x01000000      /* atomic op egress blocked */
#define PCI_ERR_UNC_TLP_PRF_BLOCKED     0x02000000      /* TLP Prefix Blocked */
#define PCI_ERR_COR_ADV_NONFATAL        0x00002000      /* Advisory Non-Fatal */
#define PCI_ERR_COR_INTERNAL            0x00004000      /* Corrected Internal */
#define PCI_ERR_COR_HL_OVERFLOW         0x00008000      /* Header Long Overflow */
#define PCI_ERR_CAP_FEP_MASK            0x0000001f
#define PCI_ERR_CAP_MHRC                0x00000200
#define PCI_ERR_CAP_MHRE                0x00000400
#define PCI_ERR_CAP_TLP                 0x00000800

#define PCI_ERR_HEADER_LOG_SIZE         16
#define PCI_ERR_TLP_PREFIX_LOG          0x38
#define PCI_ERR_TLP_PREFIX_LOG_SIZE     16

#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR         0x4000

/* aer root error command/status */
#define PCI_ERR_ROOT_CMD_EN_MASK        (PCI_ERR_ROOT_CMD_COR_EN |      \
                                         PCI_ERR_ROOT_CMD_NONFATAL_EN | \
                                         PCI_ERR_ROOT_CMD_FATAL_EN)

#define PCI_ERR_ROOT_IRQ_MAX            32
#define PCI_ERR_ROOT_IRQ                0xf8000000
#define PCI_ERR_ROOT_IRQ_SHIFT          (ffs(PCI_ERR_ROOT_IRQ) - 1)
#define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV |         \
                                         PCI_ERR_ROOT_MULTI_COR_RCV |   \
                                         PCI_ERR_ROOT_UNCOR_RCV |       \
                                         PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
                                         PCI_ERR_ROOT_FIRST_FATAL |     \
                                         PCI_ERR_ROOT_NONFATAL_RCV |    \
                                         PCI_ERR_ROOT_FATAL_RCV)

#define PCI_ERR_UNC_SUPPORTED           (PCI_ERR_UNC_DLP |              \
                                         PCI_ERR_UNC_SDN |              \
                                         PCI_ERR_UNC_POISON_TLP |       \
                                         PCI_ERR_UNC_FCP |              \
                                         PCI_ERR_UNC_COMP_TIME |        \
                                         PCI_ERR_UNC_COMP_ABORT |       \
                                         PCI_ERR_UNC_UNX_COMP |         \
                                         PCI_ERR_UNC_RX_OVER |          \
                                         PCI_ERR_UNC_MALF_TLP |         \
                                         PCI_ERR_UNC_ECRC |             \
                                         PCI_ERR_UNC_UNSUP |            \
                                         PCI_ERR_UNC_ACSV |             \
                                         PCI_ERR_UNC_INTN |             \
                                         PCI_ERR_UNC_MCBTLP |           \
                                         PCI_ERR_UNC_ATOP_EBLOCKED |    \
                                         PCI_ERR_UNC_TLP_PRF_BLOCKED)

#define PCI_ERR_UNC_SEVERITY_DEFAULT    (PCI_ERR_UNC_DLP |              \
                                         PCI_ERR_UNC_SDN |              \
                                         PCI_ERR_UNC_FCP |              \
                                         PCI_ERR_UNC_RX_OVER |          \
                                         PCI_ERR_UNC_MALF_TLP |         \
                                         PCI_ERR_UNC_INTN)

#define PCI_ERR_COR_SUPPORTED           (PCI_ERR_COR_RCVR |             \
                                         PCI_ERR_COR_BAD_TLP |          \
                                         PCI_ERR_COR_BAD_DLLP |         \
                                         PCI_ERR_COR_REP_ROLL |         \
                                         PCI_ERR_COR_REP_TIMER |        \
                                         PCI_ERR_COR_ADV_NONFATAL |     \
                                         PCI_ERR_COR_INTERNAL |         \
                                         PCI_ERR_COR_HL_OVERFLOW)

#define PCI_ERR_COR_MASK_DEFAULT        (PCI_ERR_COR_ADV_NONFATAL |     \
                                         PCI_ERR_COR_INTERNAL |         \
                                         PCI_ERR_COR_HL_OVERFLOW)

#endif /* QEMU_PCIE_REGS_H */
Commit	Line	Data
08f3dcf1 IY	1	/*
	2	* constants for pcie configurations space from pci express spec.
	3	*
	4	* TODO:
	5	* Those constants and macros should go to Linux pci_regs.h
	6	* Once they're merged, they will go away.
	7	*/
	8	#ifndef QEMU_PCIE_REGS_H
	9	#define QEMU_PCIE_REGS_H
	10
	11
	12	/* express capability */
	13
	14	#define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
	15	#define PCI_EXT_CAP_VER_SHIFT 16
	16	#define PCI_EXT_CAP_NEXT_SHIFT 20
	17	#define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
	18
	19	#define PCI_EXT_CAP(id, ver, next) \
	20	((id) \| \
	21	((ver) << PCI_EXT_CAP_VER_SHIFT) \| \
	22	((next) << PCI_EXT_CAP_NEXT_SHIFT))
	23
	24	#define PCI_EXT_CAP_ALIGN 4
	25	#define PCI_EXT_CAP_ALIGNUP(x) \
	26	(((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
	27
	28	/* PCI_EXP_FLAGS */
	29	#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */
	30	#define PCI_EXP_FLAGS_IRQ_SHIFT (ffs(PCI_EXP_FLAGS_IRQ) - 1)
	31	#define PCI_EXP_FLAGS_TYPE_SHIFT (ffs(PCI_EXP_FLAGS_TYPE) - 1)
	32
	33
	34	/* PCI_EXP_LINK{CAP, STA} */
	35	/* link speed */
	36	#define PCI_EXP_LNK_LS_25 1
	37
	38	#define PCI_EXP_LNK_MLW_SHIFT (ffs(PCI_EXP_LNKCAP_MLW) - 1)
	39	#define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT)
	40
	41	/* PCI_EXP_LINKCAP */
	42	#define PCI_EXP_LNKCAP_ASPMS_SHIFT (ffs(PCI_EXP_LNKCAP_ASPMS) - 1)
	43	#define PCI_EXP_LNKCAP_ASPMS_0S (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
	44
	45	#define PCI_EXP_LNKCAP_PN_SHIFT (ffs(PCI_EXP_LNKCAP_PN) - 1)
	46
	47	#define PCI_EXP_SLTCAP_PSN_SHIFT (ffs(PCI_EXP_SLTCAP_PSN) - 1)
	48
	49	#define PCI_EXP_SLTCTL_IND_RESERVED 0x0
	50	#define PCI_EXP_SLTCTL_IND_ON 0x1
	51	#define PCI_EXP_SLTCTL_IND_BLINK 0x2
	52	#define PCI_EXP_SLTCTL_IND_OFF 0x3
	53	#define PCI_EXP_SLTCTL_AIC_SHIFT (ffs(PCI_EXP_SLTCTL_AIC) - 1)
	54	#define PCI_EXP_SLTCTL_AIC_OFF \
	55	(PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT)
	56
	57	#define PCI_EXP_SLTCTL_PIC_SHIFT (ffs(PCI_EXP_SLTCTL_PIC) - 1)
	58	#define PCI_EXP_SLTCTL_PIC_OFF \
	59	(PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT)
	60
	61	#define PCI_EXP_SLTCTL_SUPPORTED \
	62	(PCI_EXP_SLTCTL_ABPE \| \
	63	PCI_EXP_SLTCTL_PDCE \| \
	64	PCI_EXP_SLTCTL_CCIE \| \
65	PCI_EXP_SLTCTL_HPIE \| \
66	PCI_EXP_SLTCTL_AIC \| \
67	PCI_EXP_SLTCTL_PCC \| \
68	PCI_EXP_SLTCTL_EIC)
69
70	#define PCI_EXP_DEVCAP2_EFF 0x100000
71	#define PCI_EXP_DEVCAP2_EETLPP 0x200000
72
73	#define PCI_EXP_DEVCTL2_EETLPPB 0x80
74
75	/* ARI */
76	#define PCI_ARI_VER 1
77	#define PCI_ARI_SIZEOF 8
78
79	/* AER */
80	#define PCI_ERR_VER 2
81	#define PCI_ERR_SIZEOF 0x48
82
83	#define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */
84	#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
85	#define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */
86	#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC Blcoked TLP */
87	#define PCI_ERR_UNC_ATOP_EBLOCKED 0x01000000 /* atomic op egress blocked */
88	#define PCI_ERR_UNC_TLP_PRF_BLOCKED 0x02000000 /* TLP Prefix Blocked */
89	#define PCI_ERR_COR_ADV_NONFATAL 0x00002000 /* Advisory Non-Fatal */
90	#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
91	#define PCI_ERR_COR_HL_OVERFLOW 0x00008000 /* Header Long Overflow */
92	#define PCI_ERR_CAP_FEP_MASK 0x0000001f
93	#define PCI_ERR_CAP_MHRC 0x00000200
94	#define PCI_ERR_CAP_MHRE 0x00000400
95	#define PCI_ERR_CAP_TLP 0x00000800
96
1a1ea6f0	97	#define PCI_ERR_HEADER_LOG_SIZE 16
08f3dcf1	98	#define PCI_ERR_TLP_PREFIX_LOG 0x38
1a1ea6f0	99	#define PCI_ERR_TLP_PREFIX_LOG_SIZE 16
08f3dcf1 IY	100
	101	#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR 0x4000
	102
	103	/* aer root error command/status */
	104	#define PCI_ERR_ROOT_CMD_EN_MASK (PCI_ERR_ROOT_CMD_COR_EN \| \
	105	PCI_ERR_ROOT_CMD_NONFATAL_EN \| \
	106	PCI_ERR_ROOT_CMD_FATAL_EN)
	107
	108	#define PCI_ERR_ROOT_IRQ_MAX 32
	109	#define PCI_ERR_ROOT_IRQ 0xf8000000
	110	#define PCI_ERR_ROOT_IRQ_SHIFT (ffs(PCI_ERR_ROOT_IRQ) - 1)
	111	#define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV \| \
	112	PCI_ERR_ROOT_MULTI_COR_RCV \| \
	113	PCI_ERR_ROOT_UNCOR_RCV \| \
	114	PCI_ERR_ROOT_MULTI_UNCOR_RCV \| \
	115	PCI_ERR_ROOT_FIRST_FATAL \| \
	116	PCI_ERR_ROOT_NONFATAL_RCV \| \
	117	PCI_ERR_ROOT_FATAL_RCV)
	118
	119	#define PCI_ERR_UNC_SUPPORTED (PCI_ERR_UNC_DLP \| \
	120	PCI_ERR_UNC_SDN \| \
	121	PCI_ERR_UNC_POISON_TLP \| \
	122	PCI_ERR_UNC_FCP \| \
	123	PCI_ERR_UNC_COMP_TIME \| \
	124	PCI_ERR_UNC_COMP_ABORT \| \
	125	PCI_ERR_UNC_UNX_COMP \| \
	126	PCI_ERR_UNC_RX_OVER \| \
	127	PCI_ERR_UNC_MALF_TLP \| \
	128	PCI_ERR_UNC_ECRC \| \
	129	PCI_ERR_UNC_UNSUP \| \
	130	PCI_ERR_UNC_ACSV \| \
	131	PCI_ERR_UNC_INTN \| \
	132	PCI_ERR_UNC_MCBTLP \| \
	133	PCI_ERR_UNC_ATOP_EBLOCKED \| \
	134	PCI_ERR_UNC_TLP_PRF_BLOCKED)
	135
	136	#define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP \| \
	137	PCI_ERR_UNC_SDN \| \
	138	PCI_ERR_UNC_FCP \| \
	139	PCI_ERR_UNC_RX_OVER \| \
	140	PCI_ERR_UNC_MALF_TLP \| \
	141	PCI_ERR_UNC_INTN)
	142
	143	#define PCI_ERR_COR_SUPPORTED (PCI_ERR_COR_RCVR \| \
	144	PCI_ERR_COR_BAD_TLP \| \
	145	PCI_ERR_COR_BAD_DLLP \| \
	146	PCI_ERR_COR_REP_ROLL \| \
	147	PCI_ERR_COR_REP_TIMER \| \
	148	PCI_ERR_COR_ADV_NONFATAL \| \
	149	PCI_ERR_COR_INTERNAL \| \
	150	PCI_ERR_COR_HL_OVERFLOW)
	151
	152	#define PCI_ERR_COR_MASK_DEFAULT (PCI_ERR_COR_ADV_NONFATAL \| \
	153	PCI_ERR_COR_INTERNAL \| \
	154	PCI_ERR_COR_HL_OVERFLOW)
	155
	156	#endif /* QEMU_PCIE_REGS_H */