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Commit | Line | Data |
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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
05ee37eb AZ |
19 | */ |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - CFI queries | |
29 | * | |
30 | * It does not support timings | |
31 | * It does not support flash interleaving | |
32 | * It does not implement software data protection as found in many real chips | |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | * | |
36 | * It does not implement much more ... | |
37 | */ | |
38 | ||
87ecb68b PB |
39 | #include "hw.h" |
40 | #include "flash.h" | |
41 | #include "block.h" | |
42 | #include "qemu-timer.h" | |
05ee37eb | 43 | |
001faf32 | 44 | #define PFLASH_BUG(fmt, ...) \ |
05ee37eb | 45 | do { \ |
001faf32 | 46 | printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
05ee37eb AZ |
47 | exit(1); \ |
48 | } while(0) | |
49 | ||
50 | /* #define PFLASH_DEBUG */ | |
51 | #ifdef PFLASH_DEBUG | |
001faf32 | 52 | #define DPRINTF(fmt, ...) \ |
05ee37eb | 53 | do { \ |
001faf32 | 54 | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
05ee37eb AZ |
55 | } while (0) |
56 | #else | |
001faf32 | 57 | #define DPRINTF(fmt, ...) do { } while (0) |
05ee37eb AZ |
58 | #endif |
59 | ||
c227f099 | 60 | struct pflash_t { |
05ee37eb | 61 | BlockDriverState *bs; |
c227f099 AL |
62 | target_phys_addr_t base; |
63 | target_phys_addr_t sector_len; | |
64 | target_phys_addr_t total_len; | |
05ee37eb AZ |
65 | int width; |
66 | int wcycle; /* if 0, the flash is read normally */ | |
67 | int bypass; | |
68 | int ro; | |
69 | uint8_t cmd; | |
70 | uint8_t status; | |
71 | uint16_t ident[4]; | |
72 | uint8_t cfi_len; | |
73 | uint8_t cfi_table[0x52]; | |
c227f099 | 74 | target_phys_addr_t counter; |
05ee37eb | 75 | QEMUTimer *timer; |
c227f099 | 76 | ram_addr_t off; |
05ee37eb AZ |
77 | int fl_mem; |
78 | void *storage; | |
79 | }; | |
80 | ||
81 | static void pflash_timer (void *opaque) | |
82 | { | |
c227f099 | 83 | pflash_t *pfl = opaque; |
05ee37eb AZ |
84 | |
85 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
86 | /* Reset flash */ | |
87 | pfl->status ^= 0x80; | |
88 | if (pfl->bypass) { | |
89 | pfl->wcycle = 2; | |
90 | } else { | |
91 | cpu_register_physical_memory(pfl->base, pfl->total_len, | |
92 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); | |
93 | pfl->wcycle = 0; | |
94 | } | |
95 | pfl->cmd = 0; | |
96 | } | |
97 | ||
c227f099 | 98 | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, |
42a89d77 | 99 | int width) |
05ee37eb | 100 | { |
c227f099 | 101 | target_phys_addr_t boff; |
05ee37eb AZ |
102 | uint32_t ret; |
103 | uint8_t *p; | |
104 | ||
105 | ret = -1; | |
05ee37eb AZ |
106 | boff = offset & 0xFF; /* why this here ?? */ |
107 | ||
108 | if (pfl->width == 2) | |
109 | boff = boff >> 1; | |
110 | else if (pfl->width == 4) | |
111 | boff = boff >> 2; | |
112 | ||
fad8c772 EI |
113 | #if 0 |
114 | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n", | |
06adb549 | 115 | __func__, offset, pfl->cmd, width); |
fad8c772 | 116 | #endif |
05ee37eb AZ |
117 | switch (pfl->cmd) { |
118 | case 0x00: | |
119 | /* Flash area read */ | |
120 | p = pfl->storage; | |
121 | switch (width) { | |
122 | case 1: | |
123 | ret = p[offset]; | |
fad8c772 | 124 | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
c8b153d7 | 125 | __func__, offset, ret); |
05ee37eb AZ |
126 | break; |
127 | case 2: | |
128 | #if defined(TARGET_WORDS_BIGENDIAN) | |
129 | ret = p[offset] << 8; | |
130 | ret |= p[offset + 1]; | |
131 | #else | |
132 | ret = p[offset]; | |
133 | ret |= p[offset + 1] << 8; | |
134 | #endif | |
fad8c772 | 135 | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
c8b153d7 | 136 | __func__, offset, ret); |
05ee37eb AZ |
137 | break; |
138 | case 4: | |
139 | #if defined(TARGET_WORDS_BIGENDIAN) | |
140 | ret = p[offset] << 24; | |
141 | ret |= p[offset + 1] << 16; | |
142 | ret |= p[offset + 2] << 8; | |
143 | ret |= p[offset + 3]; | |
144 | #else | |
145 | ret = p[offset]; | |
146 | ret |= p[offset + 1] << 8; | |
147 | ret |= p[offset + 1] << 8; | |
148 | ret |= p[offset + 2] << 16; | |
149 | ret |= p[offset + 3] << 24; | |
150 | #endif | |
fad8c772 | 151 | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
c8b153d7 | 152 | __func__, offset, ret); |
05ee37eb AZ |
153 | break; |
154 | default: | |
155 | DPRINTF("BUG in %s\n", __func__); | |
156 | } | |
157 | ||
158 | break; | |
159 | case 0x20: /* Block erase */ | |
160 | case 0x50: /* Clear status register */ | |
161 | case 0x60: /* Block /un)lock */ | |
162 | case 0x70: /* Status Register */ | |
163 | case 0xe8: /* Write block */ | |
164 | /* Status register read */ | |
165 | ret = pfl->status; | |
166 | DPRINTF("%s: status %x\n", __func__, ret); | |
167 | break; | |
168 | case 0x98: /* Query mode */ | |
169 | if (boff > pfl->cfi_len) | |
170 | ret = 0; | |
171 | else | |
172 | ret = pfl->cfi_table[boff]; | |
173 | break; | |
174 | default: | |
175 | /* This should never happen : reset state & treat it as a read */ | |
176 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
177 | pfl->wcycle = 0; | |
178 | pfl->cmd = 0; | |
179 | } | |
180 | return ret; | |
181 | } | |
182 | ||
183 | /* update flash content on disk */ | |
c227f099 | 184 | static void pflash_update(pflash_t *pfl, int offset, |
05ee37eb AZ |
185 | int size) |
186 | { | |
187 | int offset_end; | |
188 | if (pfl->bs) { | |
189 | offset_end = offset + size; | |
190 | /* round to sectors */ | |
191 | offset = offset >> 9; | |
192 | offset_end = (offset_end + 511) >> 9; | |
193 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), | |
194 | offset_end - offset); | |
195 | } | |
196 | } | |
197 | ||
c227f099 | 198 | static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset, |
d361be25 AZ |
199 | uint32_t value, int width) |
200 | { | |
201 | uint8_t *p = pfl->storage; | |
202 | ||
fad8c772 EI |
203 | DPRINTF("%s: block write offset " TARGET_FMT_plx |
204 | " value %x counter " TARGET_FMT_plx "\n", | |
d361be25 AZ |
205 | __func__, offset, value, pfl->counter); |
206 | switch (width) { | |
207 | case 1: | |
208 | p[offset] = value; | |
209 | pflash_update(pfl, offset, 1); | |
210 | break; | |
211 | case 2: | |
212 | #if defined(TARGET_WORDS_BIGENDIAN) | |
213 | p[offset] = value >> 8; | |
214 | p[offset + 1] = value; | |
215 | #else | |
216 | p[offset] = value; | |
217 | p[offset + 1] = value >> 8; | |
218 | #endif | |
219 | pflash_update(pfl, offset, 2); | |
220 | break; | |
221 | case 4: | |
222 | #if defined(TARGET_WORDS_BIGENDIAN) | |
223 | p[offset] = value >> 24; | |
224 | p[offset + 1] = value >> 16; | |
225 | p[offset + 2] = value >> 8; | |
226 | p[offset + 3] = value; | |
227 | #else | |
228 | p[offset] = value; | |
229 | p[offset + 1] = value >> 8; | |
230 | p[offset + 2] = value >> 16; | |
231 | p[offset + 3] = value >> 24; | |
232 | #endif | |
233 | pflash_update(pfl, offset, 4); | |
234 | break; | |
235 | } | |
236 | ||
237 | } | |
238 | ||
c227f099 | 239 | static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, |
42a89d77 | 240 | uint32_t value, int width) |
05ee37eb | 241 | { |
05ee37eb AZ |
242 | uint8_t *p; |
243 | uint8_t cmd; | |
244 | ||
05ee37eb | 245 | cmd = value; |
05ee37eb | 246 | |
fad8c772 | 247 | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
c8b153d7 | 248 | __func__, offset, value, width, pfl->wcycle); |
05ee37eb AZ |
249 | |
250 | /* Set the device in I/O access mode */ | |
251 | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); | |
05ee37eb AZ |
252 | |
253 | switch (pfl->wcycle) { | |
254 | case 0: | |
255 | /* read mode */ | |
256 | switch (cmd) { | |
257 | case 0x00: /* ??? */ | |
258 | goto reset_flash; | |
d361be25 AZ |
259 | case 0x10: /* Single Byte Program */ |
260 | case 0x40: /* Single Byte Program */ | |
fad8c772 | 261 | DPRINTF("%s: Single Byte Program\n", __func__); |
d361be25 | 262 | break; |
05ee37eb AZ |
263 | case 0x20: /* Block erase */ |
264 | p = pfl->storage; | |
265 | offset &= ~(pfl->sector_len - 1); | |
266 | ||
fad8c772 EI |
267 | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes " |
268 | TARGET_FMT_plx "\n", | |
c8b153d7 | 269 | __func__, offset, pfl->sector_len); |
05ee37eb AZ |
270 | |
271 | memset(p + offset, 0xff, pfl->sector_len); | |
272 | pflash_update(pfl, offset, pfl->sector_len); | |
273 | pfl->status |= 0x80; /* Ready! */ | |
274 | break; | |
275 | case 0x50: /* Clear status bits */ | |
276 | DPRINTF("%s: Clear status bits\n", __func__); | |
277 | pfl->status = 0x0; | |
278 | goto reset_flash; | |
279 | case 0x60: /* Block (un)lock */ | |
280 | DPRINTF("%s: Block unlock\n", __func__); | |
281 | break; | |
282 | case 0x70: /* Status Register */ | |
283 | DPRINTF("%s: Read status register\n", __func__); | |
284 | pfl->cmd = cmd; | |
285 | return; | |
286 | case 0x98: /* CFI query */ | |
287 | DPRINTF("%s: CFI query\n", __func__); | |
288 | break; | |
289 | case 0xe8: /* Write to buffer */ | |
290 | DPRINTF("%s: Write to buffer\n", __func__); | |
291 | pfl->status |= 0x80; /* Ready! */ | |
292 | break; | |
293 | case 0xff: /* Read array mode */ | |
294 | DPRINTF("%s: Read array mode\n", __func__); | |
295 | goto reset_flash; | |
296 | default: | |
297 | goto error_flash; | |
298 | } | |
299 | pfl->wcycle++; | |
300 | pfl->cmd = cmd; | |
301 | return; | |
302 | case 1: | |
303 | switch (pfl->cmd) { | |
d361be25 AZ |
304 | case 0x10: /* Single Byte Program */ |
305 | case 0x40: /* Single Byte Program */ | |
306 | DPRINTF("%s: Single Byte Program\n", __func__); | |
307 | pflash_data_write(pfl, offset, value, width); | |
308 | pfl->status |= 0x80; /* Ready! */ | |
309 | pfl->wcycle = 0; | |
310 | break; | |
05ee37eb AZ |
311 | case 0x20: /* Block erase */ |
312 | case 0x28: | |
313 | if (cmd == 0xd0) { /* confirm */ | |
3656744c | 314 | pfl->wcycle = 0; |
05ee37eb | 315 | pfl->status |= 0x80; |
9248f413 | 316 | } else if (cmd == 0xff) { /* read array mode */ |
05ee37eb AZ |
317 | goto reset_flash; |
318 | } else | |
319 | goto error_flash; | |
320 | ||
321 | break; | |
322 | case 0xe8: | |
71fb2348 AZ |
323 | DPRINTF("%s: block write of %x bytes\n", __func__, value); |
324 | pfl->counter = value; | |
05ee37eb AZ |
325 | pfl->wcycle++; |
326 | break; | |
327 | case 0x60: | |
328 | if (cmd == 0xd0) { | |
329 | pfl->wcycle = 0; | |
330 | pfl->status |= 0x80; | |
331 | } else if (cmd == 0x01) { | |
332 | pfl->wcycle = 0; | |
333 | pfl->status |= 0x80; | |
334 | } else if (cmd == 0xff) { | |
335 | goto reset_flash; | |
336 | } else { | |
337 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
338 | goto reset_flash; | |
339 | } | |
340 | break; | |
341 | case 0x98: | |
342 | if (cmd == 0xff) { | |
343 | goto reset_flash; | |
344 | } else { | |
345 | DPRINTF("%s: leaving query mode\n", __func__); | |
346 | } | |
347 | break; | |
348 | default: | |
349 | goto error_flash; | |
350 | } | |
351 | return; | |
352 | case 2: | |
353 | switch (pfl->cmd) { | |
354 | case 0xe8: /* Block write */ | |
d361be25 | 355 | pflash_data_write(pfl, offset, value, width); |
05ee37eb AZ |
356 | |
357 | pfl->status |= 0x80; | |
358 | ||
359 | if (!pfl->counter) { | |
360 | DPRINTF("%s: block write finished\n", __func__); | |
361 | pfl->wcycle++; | |
362 | } | |
363 | ||
364 | pfl->counter--; | |
365 | break; | |
7317b8ca AZ |
366 | default: |
367 | goto error_flash; | |
05ee37eb AZ |
368 | } |
369 | return; | |
370 | case 3: /* Confirm mode */ | |
371 | switch (pfl->cmd) { | |
372 | case 0xe8: /* Block write */ | |
373 | if (cmd == 0xd0) { | |
374 | pfl->wcycle = 0; | |
375 | pfl->status |= 0x80; | |
05ee37eb AZ |
376 | } else { |
377 | DPRINTF("%s: unknown command for \"write block\"\n", __func__); | |
378 | PFLASH_BUG("Write block confirm"); | |
7317b8ca | 379 | goto reset_flash; |
05ee37eb | 380 | } |
7317b8ca AZ |
381 | break; |
382 | default: | |
383 | goto error_flash; | |
05ee37eb AZ |
384 | } |
385 | return; | |
386 | default: | |
387 | /* Should never happen */ | |
388 | DPRINTF("%s: invalid write state\n", __func__); | |
389 | goto reset_flash; | |
390 | } | |
391 | return; | |
392 | ||
393 | error_flash: | |
394 | printf("%s: Unimplemented flash cmd sequence " | |
42a89d77 | 395 | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n", |
c8b153d7 | 396 | __func__, offset, pfl->wcycle, pfl->cmd, value); |
05ee37eb AZ |
397 | |
398 | reset_flash: | |
399 | cpu_register_physical_memory(pfl->base, pfl->total_len, | |
400 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); | |
401 | ||
402 | pfl->bypass = 0; | |
403 | pfl->wcycle = 0; | |
404 | pfl->cmd = 0; | |
405 | return; | |
406 | } | |
407 | ||
408 | ||
c227f099 | 409 | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
05ee37eb AZ |
410 | { |
411 | return pflash_read(opaque, addr, 1); | |
412 | } | |
413 | ||
c227f099 | 414 | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
05ee37eb | 415 | { |
c227f099 | 416 | pflash_t *pfl = opaque; |
05ee37eb AZ |
417 | |
418 | return pflash_read(pfl, addr, 2); | |
419 | } | |
420 | ||
c227f099 | 421 | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
05ee37eb | 422 | { |
c227f099 | 423 | pflash_t *pfl = opaque; |
05ee37eb AZ |
424 | |
425 | return pflash_read(pfl, addr, 4); | |
426 | } | |
427 | ||
c227f099 | 428 | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
05ee37eb AZ |
429 | uint32_t value) |
430 | { | |
431 | pflash_write(opaque, addr, value, 1); | |
432 | } | |
433 | ||
c227f099 | 434 | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
05ee37eb AZ |
435 | uint32_t value) |
436 | { | |
c227f099 | 437 | pflash_t *pfl = opaque; |
05ee37eb AZ |
438 | |
439 | pflash_write(pfl, addr, value, 2); | |
440 | } | |
441 | ||
c227f099 | 442 | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
05ee37eb AZ |
443 | uint32_t value) |
444 | { | |
c227f099 | 445 | pflash_t *pfl = opaque; |
05ee37eb AZ |
446 | |
447 | pflash_write(pfl, addr, value, 4); | |
448 | } | |
449 | ||
d60efc6b | 450 | static CPUWriteMemoryFunc * const pflash_write_ops[] = { |
05ee37eb AZ |
451 | &pflash_writeb, |
452 | &pflash_writew, | |
453 | &pflash_writel, | |
454 | }; | |
455 | ||
d60efc6b | 456 | static CPUReadMemoryFunc * const pflash_read_ops[] = { |
05ee37eb AZ |
457 | &pflash_readb, |
458 | &pflash_readw, | |
459 | &pflash_readl, | |
460 | }; | |
461 | ||
462 | /* Count trailing zeroes of a 32 bits quantity */ | |
463 | static int ctz32 (uint32_t n) | |
464 | { | |
465 | int ret; | |
466 | ||
467 | ret = 0; | |
468 | if (!(n & 0xFFFF)) { | |
469 | ret += 16; | |
470 | n = n >> 16; | |
471 | } | |
472 | if (!(n & 0xFF)) { | |
473 | ret += 8; | |
474 | n = n >> 8; | |
475 | } | |
476 | if (!(n & 0xF)) { | |
477 | ret += 4; | |
478 | n = n >> 4; | |
479 | } | |
480 | if (!(n & 0x3)) { | |
481 | ret += 2; | |
482 | n = n >> 2; | |
483 | } | |
484 | if (!(n & 0x1)) { | |
485 | ret++; | |
486 | n = n >> 1; | |
487 | } | |
488 | #if 0 /* This is not necessary as n is never 0 */ | |
489 | if (!n) | |
490 | ret++; | |
491 | #endif | |
492 | ||
493 | return ret; | |
494 | } | |
495 | ||
c227f099 | 496 | pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
c8b153d7 | 497 | BlockDriverState *bs, uint32_t sector_len, |
88eeee0a AZ |
498 | int nb_blocs, int width, |
499 | uint16_t id0, uint16_t id1, | |
500 | uint16_t id2, uint16_t id3) | |
05ee37eb | 501 | { |
c227f099 AL |
502 | pflash_t *pfl; |
503 | target_phys_addr_t total_len; | |
d0e7605e | 504 | int ret; |
05ee37eb AZ |
505 | |
506 | total_len = sector_len * nb_blocs; | |
507 | ||
508 | /* XXX: to be fixed */ | |
c8b153d7 | 509 | #if 0 |
05ee37eb AZ |
510 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
511 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
512 | return NULL; | |
c8b153d7 | 513 | #endif |
05ee37eb | 514 | |
c227f099 | 515 | pfl = qemu_mallocz(sizeof(pflash_t)); |
05ee37eb | 516 | |
5c130f65 PB |
517 | /* FIXME: Allocate ram ourselves. */ |
518 | pfl->storage = qemu_get_ram_ptr(off); | |
1eed09cb | 519 | pfl->fl_mem = cpu_register_io_memory( |
05ee37eb AZ |
520 | pflash_read_ops, pflash_write_ops, pfl); |
521 | pfl->off = off; | |
522 | cpu_register_physical_memory(base, total_len, | |
523 | off | pfl->fl_mem | IO_MEM_ROMD); | |
524 | ||
525 | pfl->bs = bs; | |
526 | if (pfl->bs) { | |
527 | /* read the initial flash content */ | |
d0e7605e VK |
528 | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
529 | if (ret < 0) { | |
530 | cpu_unregister_io_memory(pfl->fl_mem); | |
531 | qemu_free(pfl); | |
532 | return NULL; | |
533 | } | |
05ee37eb AZ |
534 | } |
535 | #if 0 /* XXX: there should be a bit to set up read-only, | |
536 | * the same way the hardware does (with WP pin). | |
537 | */ | |
538 | pfl->ro = 1; | |
539 | #else | |
540 | pfl->ro = 0; | |
541 | #endif | |
542 | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); | |
543 | pfl->base = base; | |
544 | pfl->sector_len = sector_len; | |
545 | pfl->total_len = total_len; | |
546 | pfl->width = width; | |
547 | pfl->wcycle = 0; | |
548 | pfl->cmd = 0; | |
549 | pfl->status = 0; | |
550 | pfl->ident[0] = id0; | |
551 | pfl->ident[1] = id1; | |
552 | pfl->ident[2] = id2; | |
553 | pfl->ident[3] = id3; | |
554 | /* Hardcoded CFI table */ | |
555 | pfl->cfi_len = 0x52; | |
556 | /* Standard "QRY" string */ | |
557 | pfl->cfi_table[0x10] = 'Q'; | |
558 | pfl->cfi_table[0x11] = 'R'; | |
559 | pfl->cfi_table[0x12] = 'Y'; | |
560 | /* Command set (Intel) */ | |
561 | pfl->cfi_table[0x13] = 0x01; | |
562 | pfl->cfi_table[0x14] = 0x00; | |
563 | /* Primary extended table address (none) */ | |
564 | pfl->cfi_table[0x15] = 0x31; | |
565 | pfl->cfi_table[0x16] = 0x00; | |
566 | /* Alternate command set (none) */ | |
567 | pfl->cfi_table[0x17] = 0x00; | |
568 | pfl->cfi_table[0x18] = 0x00; | |
569 | /* Alternate extended table (none) */ | |
570 | pfl->cfi_table[0x19] = 0x00; | |
571 | pfl->cfi_table[0x1A] = 0x00; | |
572 | /* Vcc min */ | |
573 | pfl->cfi_table[0x1B] = 0x45; | |
574 | /* Vcc max */ | |
575 | pfl->cfi_table[0x1C] = 0x55; | |
576 | /* Vpp min (no Vpp pin) */ | |
577 | pfl->cfi_table[0x1D] = 0x00; | |
578 | /* Vpp max (no Vpp pin) */ | |
579 | pfl->cfi_table[0x1E] = 0x00; | |
580 | /* Reserved */ | |
581 | pfl->cfi_table[0x1F] = 0x07; | |
582 | /* Timeout for min size buffer write */ | |
583 | pfl->cfi_table[0x20] = 0x07; | |
584 | /* Typical timeout for block erase */ | |
585 | pfl->cfi_table[0x21] = 0x0a; | |
586 | /* Typical timeout for full chip erase (4096 ms) */ | |
587 | pfl->cfi_table[0x22] = 0x00; | |
588 | /* Reserved */ | |
589 | pfl->cfi_table[0x23] = 0x04; | |
590 | /* Max timeout for buffer write */ | |
591 | pfl->cfi_table[0x24] = 0x04; | |
592 | /* Max timeout for block erase */ | |
593 | pfl->cfi_table[0x25] = 0x04; | |
594 | /* Max timeout for chip erase */ | |
595 | pfl->cfi_table[0x26] = 0x00; | |
596 | /* Device size */ | |
597 | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; | |
598 | /* Flash device interface (8 & 16 bits) */ | |
599 | pfl->cfi_table[0x28] = 0x02; | |
600 | pfl->cfi_table[0x29] = 0x00; | |
601 | /* Max number of bytes in multi-bytes write */ | |
4737fa26 EI |
602 | if (width == 1) { |
603 | pfl->cfi_table[0x2A] = 0x08; | |
604 | } else { | |
605 | pfl->cfi_table[0x2A] = 0x0B; | |
606 | } | |
05ee37eb AZ |
607 | pfl->cfi_table[0x2B] = 0x00; |
608 | /* Number of erase block regions (uniform) */ | |
609 | pfl->cfi_table[0x2C] = 0x01; | |
610 | /* Erase block region 1 */ | |
611 | pfl->cfi_table[0x2D] = nb_blocs - 1; | |
612 | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; | |
613 | pfl->cfi_table[0x2F] = sector_len >> 8; | |
614 | pfl->cfi_table[0x30] = sector_len >> 16; | |
615 | ||
616 | /* Extended */ | |
617 | pfl->cfi_table[0x31] = 'P'; | |
618 | pfl->cfi_table[0x32] = 'R'; | |
619 | pfl->cfi_table[0x33] = 'I'; | |
620 | ||
621 | pfl->cfi_table[0x34] = '1'; | |
622 | pfl->cfi_table[0x35] = '1'; | |
623 | ||
624 | pfl->cfi_table[0x36] = 0x00; | |
625 | pfl->cfi_table[0x37] = 0x00; | |
626 | pfl->cfi_table[0x38] = 0x00; | |
627 | pfl->cfi_table[0x39] = 0x00; | |
628 | ||
629 | pfl->cfi_table[0x3a] = 0x00; | |
630 | ||
631 | pfl->cfi_table[0x3b] = 0x00; | |
632 | pfl->cfi_table[0x3c] = 0x00; | |
633 | ||
634 | return pfl; | |
635 | } |