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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | /* | |
23 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
24 | * Supported commands/modes are: | |
25 | * - flash read | |
26 | * - flash write | |
27 | * - flash ID read | |
28 | * - sector erase | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support timings | |
32 | * It does not support flash interleaving | |
33 | * It does not implement software data protection as found in many real chips | |
34 | * It does not implement erase suspend/resume commands | |
35 | * It does not implement multiple sectors erase | |
36 | * | |
37 | * It does not implement much more ... | |
38 | */ | |
39 | ||
87ecb68b PB |
40 | #include "hw.h" |
41 | #include "flash.h" | |
42 | #include "block.h" | |
43 | #include "qemu-timer.h" | |
05ee37eb AZ |
44 | |
45 | #define PFLASH_BUG(fmt, args...) \ | |
46 | do { \ | |
47 | printf("PFLASH: Possible BUG - " fmt, ##args); \ | |
48 | exit(1); \ | |
49 | } while(0) | |
50 | ||
51 | /* #define PFLASH_DEBUG */ | |
52 | #ifdef PFLASH_DEBUG | |
53 | #define DPRINTF(fmt, args...) \ | |
54 | do { \ | |
55 | printf("PFLASH: " fmt , ##args); \ | |
56 | } while (0) | |
57 | #else | |
58 | #define DPRINTF(fmt, args...) do { } while (0) | |
59 | #endif | |
60 | ||
61 | struct pflash_t { | |
62 | BlockDriverState *bs; | |
63 | target_ulong base; | |
64 | target_ulong sector_len; | |
65 | target_ulong total_len; | |
66 | int width; | |
67 | int wcycle; /* if 0, the flash is read normally */ | |
68 | int bypass; | |
69 | int ro; | |
70 | uint8_t cmd; | |
71 | uint8_t status; | |
72 | uint16_t ident[4]; | |
73 | uint8_t cfi_len; | |
74 | uint8_t cfi_table[0x52]; | |
75 | target_ulong counter; | |
76 | QEMUTimer *timer; | |
77 | ram_addr_t off; | |
78 | int fl_mem; | |
79 | void *storage; | |
80 | }; | |
81 | ||
82 | static void pflash_timer (void *opaque) | |
83 | { | |
84 | pflash_t *pfl = opaque; | |
85 | ||
86 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
87 | /* Reset flash */ | |
88 | pfl->status ^= 0x80; | |
89 | if (pfl->bypass) { | |
90 | pfl->wcycle = 2; | |
91 | } else { | |
92 | cpu_register_physical_memory(pfl->base, pfl->total_len, | |
93 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); | |
94 | pfl->wcycle = 0; | |
95 | } | |
96 | pfl->cmd = 0; | |
97 | } | |
98 | ||
99 | static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) | |
100 | { | |
101 | target_ulong boff; | |
102 | uint32_t ret; | |
103 | uint8_t *p; | |
104 | ||
105 | ret = -1; | |
106 | offset -= pfl->base; | |
107 | boff = offset & 0xFF; /* why this here ?? */ | |
108 | ||
109 | if (pfl->width == 2) | |
110 | boff = boff >> 1; | |
111 | else if (pfl->width == 4) | |
112 | boff = boff >> 2; | |
113 | ||
114 | DPRINTF("%s: reading offset %08x under cmd %02x\n", | |
115 | __func__, boff, pfl->cmd); | |
116 | ||
117 | switch (pfl->cmd) { | |
118 | case 0x00: | |
119 | /* Flash area read */ | |
120 | p = pfl->storage; | |
121 | switch (width) { | |
122 | case 1: | |
123 | ret = p[offset]; | |
124 | DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); | |
125 | break; | |
126 | case 2: | |
127 | #if defined(TARGET_WORDS_BIGENDIAN) | |
128 | ret = p[offset] << 8; | |
129 | ret |= p[offset + 1]; | |
130 | #else | |
131 | ret = p[offset]; | |
132 | ret |= p[offset + 1] << 8; | |
133 | #endif | |
134 | DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); | |
135 | break; | |
136 | case 4: | |
137 | #if defined(TARGET_WORDS_BIGENDIAN) | |
138 | ret = p[offset] << 24; | |
139 | ret |= p[offset + 1] << 16; | |
140 | ret |= p[offset + 2] << 8; | |
141 | ret |= p[offset + 3]; | |
142 | #else | |
143 | ret = p[offset]; | |
144 | ret |= p[offset + 1] << 8; | |
145 | ret |= p[offset + 1] << 8; | |
146 | ret |= p[offset + 2] << 16; | |
147 | ret |= p[offset + 3] << 24; | |
148 | #endif | |
149 | DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); | |
150 | break; | |
151 | default: | |
152 | DPRINTF("BUG in %s\n", __func__); | |
153 | } | |
154 | ||
155 | break; | |
156 | case 0x20: /* Block erase */ | |
157 | case 0x50: /* Clear status register */ | |
158 | case 0x60: /* Block /un)lock */ | |
159 | case 0x70: /* Status Register */ | |
160 | case 0xe8: /* Write block */ | |
161 | /* Status register read */ | |
162 | ret = pfl->status; | |
163 | DPRINTF("%s: status %x\n", __func__, ret); | |
164 | break; | |
165 | case 0x98: /* Query mode */ | |
166 | if (boff > pfl->cfi_len) | |
167 | ret = 0; | |
168 | else | |
169 | ret = pfl->cfi_table[boff]; | |
170 | break; | |
171 | default: | |
172 | /* This should never happen : reset state & treat it as a read */ | |
173 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
174 | pfl->wcycle = 0; | |
175 | pfl->cmd = 0; | |
176 | } | |
177 | return ret; | |
178 | } | |
179 | ||
180 | /* update flash content on disk */ | |
181 | static void pflash_update(pflash_t *pfl, int offset, | |
182 | int size) | |
183 | { | |
184 | int offset_end; | |
185 | if (pfl->bs) { | |
186 | offset_end = offset + size; | |
187 | /* round to sectors */ | |
188 | offset = offset >> 9; | |
189 | offset_end = (offset_end + 511) >> 9; | |
190 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), | |
191 | offset_end - offset); | |
192 | } | |
193 | } | |
194 | ||
195 | static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, | |
196 | int width) | |
197 | { | |
198 | target_ulong boff; | |
199 | uint8_t *p; | |
200 | uint8_t cmd; | |
201 | ||
202 | /* WARNING: when the memory area is in ROMD mode, the offset is a | |
203 | ram offset, not a physical address */ | |
204 | cmd = value; | |
205 | ||
206 | if (pfl->wcycle == 0) | |
207 | offset -= (target_ulong)(long)pfl->storage; | |
208 | else | |
209 | offset -= pfl->base; | |
210 | ||
211 | DPRINTF("%s: offset %08x %08x %d wcycle 0x%x\n", | |
212 | __func__, offset, value, width, pfl->wcycle); | |
213 | ||
214 | /* Set the device in I/O access mode */ | |
215 | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); | |
216 | boff = offset & (pfl->sector_len - 1); | |
217 | ||
218 | if (pfl->width == 2) | |
219 | boff = boff >> 1; | |
220 | else if (pfl->width == 4) | |
221 | boff = boff >> 2; | |
222 | ||
223 | switch (pfl->wcycle) { | |
224 | case 0: | |
225 | /* read mode */ | |
226 | switch (cmd) { | |
227 | case 0x00: /* ??? */ | |
228 | goto reset_flash; | |
229 | case 0x20: /* Block erase */ | |
230 | p = pfl->storage; | |
231 | offset &= ~(pfl->sector_len - 1); | |
232 | ||
233 | DPRINTF("%s: block erase at 0x%x bytes 0x%x\n", __func__, | |
234 | offset, pfl->sector_len); | |
235 | ||
236 | memset(p + offset, 0xff, pfl->sector_len); | |
237 | pflash_update(pfl, offset, pfl->sector_len); | |
238 | pfl->status |= 0x80; /* Ready! */ | |
239 | break; | |
240 | case 0x50: /* Clear status bits */ | |
241 | DPRINTF("%s: Clear status bits\n", __func__); | |
242 | pfl->status = 0x0; | |
243 | goto reset_flash; | |
244 | case 0x60: /* Block (un)lock */ | |
245 | DPRINTF("%s: Block unlock\n", __func__); | |
246 | break; | |
247 | case 0x70: /* Status Register */ | |
248 | DPRINTF("%s: Read status register\n", __func__); | |
249 | pfl->cmd = cmd; | |
250 | return; | |
251 | case 0x98: /* CFI query */ | |
252 | DPRINTF("%s: CFI query\n", __func__); | |
253 | break; | |
254 | case 0xe8: /* Write to buffer */ | |
255 | DPRINTF("%s: Write to buffer\n", __func__); | |
256 | pfl->status |= 0x80; /* Ready! */ | |
257 | break; | |
258 | case 0xff: /* Read array mode */ | |
259 | DPRINTF("%s: Read array mode\n", __func__); | |
260 | goto reset_flash; | |
261 | default: | |
262 | goto error_flash; | |
263 | } | |
264 | pfl->wcycle++; | |
265 | pfl->cmd = cmd; | |
266 | return; | |
267 | case 1: | |
268 | switch (pfl->cmd) { | |
269 | case 0x20: /* Block erase */ | |
270 | case 0x28: | |
271 | if (cmd == 0xd0) { /* confirm */ | |
272 | pfl->wcycle = 1; | |
273 | pfl->status |= 0x80; | |
274 | } if (cmd == 0xff) { /* read array mode */ | |
275 | goto reset_flash; | |
276 | } else | |
277 | goto error_flash; | |
278 | ||
279 | break; | |
280 | case 0xe8: | |
281 | DPRINTF("%s: block write of 0x%x bytes\n", __func__, cmd); | |
282 | pfl->counter = cmd; | |
283 | pfl->wcycle++; | |
284 | break; | |
285 | case 0x60: | |
286 | if (cmd == 0xd0) { | |
287 | pfl->wcycle = 0; | |
288 | pfl->status |= 0x80; | |
289 | } else if (cmd == 0x01) { | |
290 | pfl->wcycle = 0; | |
291 | pfl->status |= 0x80; | |
292 | } else if (cmd == 0xff) { | |
293 | goto reset_flash; | |
294 | } else { | |
295 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
296 | goto reset_flash; | |
297 | } | |
298 | break; | |
299 | case 0x98: | |
300 | if (cmd == 0xff) { | |
301 | goto reset_flash; | |
302 | } else { | |
303 | DPRINTF("%s: leaving query mode\n", __func__); | |
304 | } | |
305 | break; | |
306 | default: | |
307 | goto error_flash; | |
308 | } | |
309 | return; | |
310 | case 2: | |
311 | switch (pfl->cmd) { | |
312 | case 0xe8: /* Block write */ | |
313 | p = pfl->storage; | |
314 | DPRINTF("%s: block write offset 0x%x value 0x%x counter 0x%x\n", | |
315 | __func__, offset, value, pfl->counter); | |
316 | switch (width) { | |
317 | case 1: | |
318 | p[offset] = value; | |
319 | pflash_update(pfl, offset, 1); | |
320 | break; | |
321 | case 2: | |
322 | #if defined(TARGET_WORDS_BIGENDIAN) | |
323 | p[offset] = value >> 8; | |
324 | p[offset + 1] = value; | |
325 | #else | |
326 | p[offset] = value; | |
327 | p[offset + 1] = value >> 8; | |
328 | #endif | |
329 | pflash_update(pfl, offset, 2); | |
330 | break; | |
331 | case 4: | |
332 | #if defined(TARGET_WORDS_BIGENDIAN) | |
333 | p[offset] = value >> 24; | |
334 | p[offset + 1] = value >> 16; | |
335 | p[offset + 2] = value >> 8; | |
336 | p[offset + 3] = value; | |
337 | #else | |
338 | p[offset] = value; | |
339 | p[offset + 1] = value >> 8; | |
340 | p[offset + 2] = value >> 16; | |
341 | p[offset + 3] = value >> 24; | |
342 | #endif | |
343 | pflash_update(pfl, offset, 4); | |
344 | break; | |
345 | } | |
346 | ||
347 | pfl->status |= 0x80; | |
348 | ||
349 | if (!pfl->counter) { | |
350 | DPRINTF("%s: block write finished\n", __func__); | |
351 | pfl->wcycle++; | |
352 | } | |
353 | ||
354 | pfl->counter--; | |
355 | break; | |
7317b8ca AZ |
356 | default: |
357 | goto error_flash; | |
05ee37eb AZ |
358 | } |
359 | return; | |
360 | case 3: /* Confirm mode */ | |
361 | switch (pfl->cmd) { | |
362 | case 0xe8: /* Block write */ | |
363 | if (cmd == 0xd0) { | |
364 | pfl->wcycle = 0; | |
365 | pfl->status |= 0x80; | |
05ee37eb AZ |
366 | } else { |
367 | DPRINTF("%s: unknown command for \"write block\"\n", __func__); | |
368 | PFLASH_BUG("Write block confirm"); | |
7317b8ca | 369 | goto reset_flash; |
05ee37eb | 370 | } |
7317b8ca AZ |
371 | break; |
372 | default: | |
373 | goto error_flash; | |
05ee37eb AZ |
374 | } |
375 | return; | |
376 | default: | |
377 | /* Should never happen */ | |
378 | DPRINTF("%s: invalid write state\n", __func__); | |
379 | goto reset_flash; | |
380 | } | |
381 | return; | |
382 | ||
383 | error_flash: | |
384 | printf("%s: Unimplemented flash cmd sequence " | |
385 | "(offset 0x%x, wcycle 0x%x cmd 0x%x value 0x%x\n", | |
386 | __func__, offset, pfl->wcycle, pfl->cmd, value); | |
387 | ||
388 | reset_flash: | |
389 | cpu_register_physical_memory(pfl->base, pfl->total_len, | |
390 | pfl->off | IO_MEM_ROMD | pfl->fl_mem); | |
391 | ||
392 | pfl->bypass = 0; | |
393 | pfl->wcycle = 0; | |
394 | pfl->cmd = 0; | |
395 | return; | |
396 | } | |
397 | ||
398 | ||
399 | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) | |
400 | { | |
401 | return pflash_read(opaque, addr, 1); | |
402 | } | |
403 | ||
404 | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) | |
405 | { | |
406 | pflash_t *pfl = opaque; | |
407 | ||
408 | return pflash_read(pfl, addr, 2); | |
409 | } | |
410 | ||
411 | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) | |
412 | { | |
413 | pflash_t *pfl = opaque; | |
414 | ||
415 | return pflash_read(pfl, addr, 4); | |
416 | } | |
417 | ||
418 | static void pflash_writeb (void *opaque, target_phys_addr_t addr, | |
419 | uint32_t value) | |
420 | { | |
421 | pflash_write(opaque, addr, value, 1); | |
422 | } | |
423 | ||
424 | static void pflash_writew (void *opaque, target_phys_addr_t addr, | |
425 | uint32_t value) | |
426 | { | |
427 | pflash_t *pfl = opaque; | |
428 | ||
429 | pflash_write(pfl, addr, value, 2); | |
430 | } | |
431 | ||
432 | static void pflash_writel (void *opaque, target_phys_addr_t addr, | |
433 | uint32_t value) | |
434 | { | |
435 | pflash_t *pfl = opaque; | |
436 | ||
437 | pflash_write(pfl, addr, value, 4); | |
438 | } | |
439 | ||
440 | static CPUWriteMemoryFunc *pflash_write_ops[] = { | |
441 | &pflash_writeb, | |
442 | &pflash_writew, | |
443 | &pflash_writel, | |
444 | }; | |
445 | ||
446 | static CPUReadMemoryFunc *pflash_read_ops[] = { | |
447 | &pflash_readb, | |
448 | &pflash_readw, | |
449 | &pflash_readl, | |
450 | }; | |
451 | ||
452 | /* Count trailing zeroes of a 32 bits quantity */ | |
453 | static int ctz32 (uint32_t n) | |
454 | { | |
455 | int ret; | |
456 | ||
457 | ret = 0; | |
458 | if (!(n & 0xFFFF)) { | |
459 | ret += 16; | |
460 | n = n >> 16; | |
461 | } | |
462 | if (!(n & 0xFF)) { | |
463 | ret += 8; | |
464 | n = n >> 8; | |
465 | } | |
466 | if (!(n & 0xF)) { | |
467 | ret += 4; | |
468 | n = n >> 4; | |
469 | } | |
470 | if (!(n & 0x3)) { | |
471 | ret += 2; | |
472 | n = n >> 2; | |
473 | } | |
474 | if (!(n & 0x1)) { | |
475 | ret++; | |
476 | n = n >> 1; | |
477 | } | |
478 | #if 0 /* This is not necessary as n is never 0 */ | |
479 | if (!n) | |
480 | ret++; | |
481 | #endif | |
482 | ||
483 | return ret; | |
484 | } | |
485 | ||
486 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, | |
487 | BlockDriverState *bs, | |
488 | target_ulong sector_len, int nb_blocs, int width, | |
489 | uint16_t id0, uint16_t id1, | |
490 | uint16_t id2, uint16_t id3) | |
491 | { | |
492 | pflash_t *pfl; | |
493 | target_long total_len; | |
494 | ||
495 | total_len = sector_len * nb_blocs; | |
496 | ||
497 | /* XXX: to be fixed */ | |
498 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && | |
499 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
500 | return NULL; | |
501 | ||
502 | pfl = qemu_mallocz(sizeof(pflash_t)); | |
503 | ||
504 | if (pfl == NULL) | |
505 | return NULL; | |
506 | pfl->storage = phys_ram_base + off; | |
507 | pfl->fl_mem = cpu_register_io_memory(0, | |
508 | pflash_read_ops, pflash_write_ops, pfl); | |
509 | pfl->off = off; | |
510 | cpu_register_physical_memory(base, total_len, | |
511 | off | pfl->fl_mem | IO_MEM_ROMD); | |
512 | ||
513 | pfl->bs = bs; | |
514 | if (pfl->bs) { | |
515 | /* read the initial flash content */ | |
516 | bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); | |
517 | } | |
518 | #if 0 /* XXX: there should be a bit to set up read-only, | |
519 | * the same way the hardware does (with WP pin). | |
520 | */ | |
521 | pfl->ro = 1; | |
522 | #else | |
523 | pfl->ro = 0; | |
524 | #endif | |
525 | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); | |
526 | pfl->base = base; | |
527 | pfl->sector_len = sector_len; | |
528 | pfl->total_len = total_len; | |
529 | pfl->width = width; | |
530 | pfl->wcycle = 0; | |
531 | pfl->cmd = 0; | |
532 | pfl->status = 0; | |
533 | pfl->ident[0] = id0; | |
534 | pfl->ident[1] = id1; | |
535 | pfl->ident[2] = id2; | |
536 | pfl->ident[3] = id3; | |
537 | /* Hardcoded CFI table */ | |
538 | pfl->cfi_len = 0x52; | |
539 | /* Standard "QRY" string */ | |
540 | pfl->cfi_table[0x10] = 'Q'; | |
541 | pfl->cfi_table[0x11] = 'R'; | |
542 | pfl->cfi_table[0x12] = 'Y'; | |
543 | /* Command set (Intel) */ | |
544 | pfl->cfi_table[0x13] = 0x01; | |
545 | pfl->cfi_table[0x14] = 0x00; | |
546 | /* Primary extended table address (none) */ | |
547 | pfl->cfi_table[0x15] = 0x31; | |
548 | pfl->cfi_table[0x16] = 0x00; | |
549 | /* Alternate command set (none) */ | |
550 | pfl->cfi_table[0x17] = 0x00; | |
551 | pfl->cfi_table[0x18] = 0x00; | |
552 | /* Alternate extended table (none) */ | |
553 | pfl->cfi_table[0x19] = 0x00; | |
554 | pfl->cfi_table[0x1A] = 0x00; | |
555 | /* Vcc min */ | |
556 | pfl->cfi_table[0x1B] = 0x45; | |
557 | /* Vcc max */ | |
558 | pfl->cfi_table[0x1C] = 0x55; | |
559 | /* Vpp min (no Vpp pin) */ | |
560 | pfl->cfi_table[0x1D] = 0x00; | |
561 | /* Vpp max (no Vpp pin) */ | |
562 | pfl->cfi_table[0x1E] = 0x00; | |
563 | /* Reserved */ | |
564 | pfl->cfi_table[0x1F] = 0x07; | |
565 | /* Timeout for min size buffer write */ | |
566 | pfl->cfi_table[0x20] = 0x07; | |
567 | /* Typical timeout for block erase */ | |
568 | pfl->cfi_table[0x21] = 0x0a; | |
569 | /* Typical timeout for full chip erase (4096 ms) */ | |
570 | pfl->cfi_table[0x22] = 0x00; | |
571 | /* Reserved */ | |
572 | pfl->cfi_table[0x23] = 0x04; | |
573 | /* Max timeout for buffer write */ | |
574 | pfl->cfi_table[0x24] = 0x04; | |
575 | /* Max timeout for block erase */ | |
576 | pfl->cfi_table[0x25] = 0x04; | |
577 | /* Max timeout for chip erase */ | |
578 | pfl->cfi_table[0x26] = 0x00; | |
579 | /* Device size */ | |
580 | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; | |
581 | /* Flash device interface (8 & 16 bits) */ | |
582 | pfl->cfi_table[0x28] = 0x02; | |
583 | pfl->cfi_table[0x29] = 0x00; | |
584 | /* Max number of bytes in multi-bytes write */ | |
585 | pfl->cfi_table[0x2A] = 0x04; | |
586 | pfl->cfi_table[0x2B] = 0x00; | |
587 | /* Number of erase block regions (uniform) */ | |
588 | pfl->cfi_table[0x2C] = 0x01; | |
589 | /* Erase block region 1 */ | |
590 | pfl->cfi_table[0x2D] = nb_blocs - 1; | |
591 | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; | |
592 | pfl->cfi_table[0x2F] = sector_len >> 8; | |
593 | pfl->cfi_table[0x30] = sector_len >> 16; | |
594 | ||
595 | /* Extended */ | |
596 | pfl->cfi_table[0x31] = 'P'; | |
597 | pfl->cfi_table[0x32] = 'R'; | |
598 | pfl->cfi_table[0x33] = 'I'; | |
599 | ||
600 | pfl->cfi_table[0x34] = '1'; | |
601 | pfl->cfi_table[0x35] = '1'; | |
602 | ||
603 | pfl->cfi_table[0x36] = 0x00; | |
604 | pfl->cfi_table[0x37] = 0x00; | |
605 | pfl->cfi_table[0x38] = 0x00; | |
606 | pfl->cfi_table[0x39] = 0x00; | |
607 | ||
608 | pfl->cfi_table[0x3a] = 0x00; | |
609 | ||
610 | pfl->cfi_table[0x3b] = 0x00; | |
611 | pfl->cfi_table[0x3c] = 0x00; | |
612 | ||
613 | return pfl; | |
614 | } |