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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "pc.h" | |
27 | #include "pci.h" | |
4f5e19e6 | 28 | #include "pci_host.h" |
f75247f1 | 29 | #include "isa.h" |
8a14daa5 | 30 | #include "sysbus.h" |
87ecb68b | 31 | |
502a5395 PB |
32 | typedef PCIHostState I440FXState; |
33 | ||
fd37d881 JQ |
34 | typedef struct PIIX3State { |
35 | PCIDevice dev; | |
8372615d | 36 | int pci_irq_levels[4]; |
bd7dce87 | 37 | qemu_irq *pic; |
7cd9eee0 | 38 | } PIIX3State; |
bd7dce87 | 39 | |
0a3bacf3 JQ |
40 | struct PCII440FXState { |
41 | PCIDevice dev; | |
c227f099 | 42 | target_phys_addr_t isa_page_descs[384 / 4]; |
6c009fa4 | 43 | uint8_t smm_enabled; |
7cd9eee0 | 44 | PIIX3State *piix3; |
0a3bacf3 JQ |
45 | }; |
46 | ||
5d4e84c8 | 47 | static void piix3_set_irq(void *opaque, int irq_num, int level); |
d2b59317 PB |
48 | |
49 | /* return the global irq number corresponding to a given device irq | |
50 | pin. We could also use the bus number to have a more precise | |
51 | mapping. */ | |
52 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) | |
53 | { | |
54 | int slot_addend; | |
55 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
56 | return (irq_num + slot_addend) & 3; | |
57 | } | |
502a5395 | 58 | |
0a3bacf3 | 59 | static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
84631fd7 FB |
60 | { |
61 | uint32_t addr; | |
62 | ||
63 | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r); | |
64 | switch(r) { | |
65 | case 3: | |
66 | /* RAM */ | |
5fafdf24 | 67 | cpu_register_physical_memory(start, end - start, |
84631fd7 FB |
68 | start); |
69 | break; | |
70 | case 1: | |
71 | /* ROM (XXX: not quite correct) */ | |
5fafdf24 | 72 | cpu_register_physical_memory(start, end - start, |
84631fd7 FB |
73 | start | IO_MEM_ROM); |
74 | break; | |
75 | case 2: | |
76 | case 0: | |
77 | /* XXX: should distinguish read/write cases */ | |
78 | for(addr = start; addr < end; addr += 4096) { | |
5fafdf24 | 79 | cpu_register_physical_memory(addr, 4096, |
6c009fa4 | 80 | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
84631fd7 FB |
81 | } |
82 | break; | |
83 | } | |
84 | } | |
ee0ea1d0 | 85 | |
0a3bacf3 | 86 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 FB |
87 | { |
88 | int i, r; | |
84631fd7 FB |
89 | uint32_t smram, addr; |
90 | ||
0a3bacf3 | 91 | update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3); |
84631fd7 | 92 | for(i = 0; i < 12; i++) { |
0a3bacf3 | 93 | r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; |
84631fd7 | 94 | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
ee0ea1d0 | 95 | } |
0a3bacf3 | 96 | smram = d->dev.config[0x72]; |
6c009fa4 | 97 | if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
84631fd7 FB |
98 | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
99 | } else { | |
100 | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { | |
5fafdf24 | 101 | cpu_register_physical_memory(addr, 4096, |
6c009fa4 | 102 | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
ee0ea1d0 FB |
103 | } |
104 | } | |
105 | } | |
106 | ||
0a3bacf3 | 107 | void i440fx_set_smm(PCII440FXState *d, int val) |
ee0ea1d0 FB |
108 | { |
109 | val = (val != 0); | |
6c009fa4 JQ |
110 | if (d->smm_enabled != val) { |
111 | d->smm_enabled = val; | |
ee0ea1d0 FB |
112 | i440fx_update_memory_mappings(d); |
113 | } | |
114 | } | |
115 | ||
116 | ||
117 | /* XXX: suppress when better memory API. We make the assumption that | |
118 | no device (in particular the VGA) changes the memory mappings in | |
119 | the 0xa0000-0x100000 range */ | |
0a3bacf3 | 120 | void i440fx_init_memory_mappings(PCII440FXState *d) |
ee0ea1d0 FB |
121 | { |
122 | int i; | |
123 | for(i = 0; i < 96; i++) { | |
6c009fa4 | 124 | d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
ee0ea1d0 FB |
125 | } |
126 | } | |
127 | ||
0a3bacf3 | 128 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
129 | uint32_t address, uint32_t val, int len) |
130 | { | |
0a3bacf3 JQ |
131 | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
132 | ||
ee0ea1d0 | 133 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 134 | pci_default_write_config(dev, address, val, len); |
84631fd7 | 135 | if ((address >= 0x59 && address <= 0x5f) || address == 0x72) |
ee0ea1d0 FB |
136 | i440fx_update_memory_mappings(d); |
137 | } | |
138 | ||
0c7d19e5 | 139 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 140 | { |
0a3bacf3 | 141 | PCII440FXState *d = opaque; |
52fc1d83 | 142 | int ret, i; |
ee0ea1d0 | 143 | |
0a3bacf3 | 144 | ret = pci_device_load(&d->dev, f); |
ee0ea1d0 FB |
145 | if (ret < 0) |
146 | return ret; | |
147 | i440fx_update_memory_mappings(d); | |
6c009fa4 | 148 | qemu_get_8s(f, &d->smm_enabled); |
52fc1d83 | 149 | |
da64182c | 150 | if (version_id == 2) |
52fc1d83 | 151 | for (i = 0; i < 4; i++) |
7cd9eee0 | 152 | d->piix3->pci_irq_levels[i] = qemu_get_be32(f); |
52fc1d83 | 153 | |
ee0ea1d0 FB |
154 | return 0; |
155 | } | |
156 | ||
e59fb374 | 157 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
158 | { |
159 | PCII440FXState *d = opaque; | |
160 | ||
161 | i440fx_update_memory_mappings(d); | |
162 | return 0; | |
163 | } | |
164 | ||
165 | static const VMStateDescription vmstate_i440fx = { | |
166 | .name = "I440FX", | |
167 | .version_id = 3, | |
168 | .minimum_version_id = 3, | |
169 | .minimum_version_id_old = 1, | |
170 | .load_state_old = i440fx_load_old, | |
752ff2fa | 171 | .post_load = i440fx_post_load, |
0c7d19e5 JQ |
172 | .fields = (VMStateField []) { |
173 | VMSTATE_PCI_DEVICE(dev, PCII440FXState), | |
174 | VMSTATE_UINT8(smm_enabled, PCII440FXState), | |
175 | VMSTATE_END_OF_LIST() | |
176 | } | |
177 | }; | |
178 | ||
81a322d4 | 179 | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
502a5395 | 180 | { |
8a14daa5 | 181 | I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
502a5395 | 182 | |
f08b32fe | 183 | pci_host_conf_register_ioport(0xcf8, s); |
502a5395 | 184 | |
4f5e19e6 | 185 | pci_host_data_register_ioport(0xcfc, s); |
81a322d4 | 186 | return 0; |
8a14daa5 | 187 | } |
502a5395 | 188 | |
0a3bacf3 | 189 | static int i440fx_initfn(PCIDevice *dev) |
8a14daa5 | 190 | { |
0a3bacf3 | 191 | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
ee0ea1d0 | 192 | |
0a3bacf3 JQ |
193 | pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); |
194 | pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441); | |
195 | d->dev.config[0x08] = 0x02; // revision | |
196 | pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST); | |
197 | d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type | |
198 | ||
199 | d->dev.config[0x72] = 0x02; /* SMRAM */ | |
ee0ea1d0 | 200 | |
81a322d4 | 201 | return 0; |
8a14daa5 GH |
202 | } |
203 | ||
85a750ca | 204 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic) |
8a14daa5 GH |
205 | { |
206 | DeviceState *dev; | |
207 | PCIBus *b; | |
208 | PCIDevice *d; | |
209 | I440FXState *s; | |
7cd9eee0 | 210 | PIIX3State *piix3; |
8a14daa5 GH |
211 | |
212 | dev = qdev_create(NULL, "i440FX-pcihost"); | |
213 | s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); | |
7cd9eee0 | 214 | b = pci_bus_new(&s->busdev.qdev, NULL, 0); |
8a14daa5 | 215 | s->bus = b; |
e23a1b33 | 216 | qdev_init_nofail(dev); |
8a14daa5 GH |
217 | |
218 | d = pci_create_simple(b, 0, "i440FX"); | |
0a3bacf3 | 219 | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
8a14daa5 | 220 | |
7cd9eee0 | 221 | piix3 = DO_UPCAST(PIIX3State, dev, |
fd83e9b9 | 222 | pci_create_simple(b, -1, "PIIX3")); |
7cd9eee0 GH |
223 | piix3->pic = pic; |
224 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4); | |
225 | (*pi440fx_state)->piix3 = piix3; | |
226 | ||
227 | *piix3_devfn = piix3->dev.devfn; | |
85a750ca | 228 | |
502a5395 PB |
229 | return b; |
230 | } | |
231 | ||
232 | /* PIIX3 PCI to ISA bridge */ | |
233 | ||
5d4e84c8 | 234 | static void piix3_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 235 | { |
d2b59317 | 236 | int i, pic_irq, pic_level; |
7cd9eee0 | 237 | PIIX3State *piix3 = opaque; |
502a5395 | 238 | |
7cd9eee0 | 239 | piix3->pci_irq_levels[irq_num] = level; |
502a5395 PB |
240 | |
241 | /* now we change the pic irq level according to the piix irq mappings */ | |
242 | /* XXX: optimize */ | |
7cd9eee0 | 243 | pic_irq = piix3->dev.config[0x60 + irq_num]; |
502a5395 | 244 | if (pic_irq < 16) { |
d2b59317 | 245 | /* The pic level is the logical OR of all the PCI irqs mapped |
502a5395 PB |
246 | to it */ |
247 | pic_level = 0; | |
d2b59317 | 248 | for (i = 0; i < 4; i++) { |
7cd9eee0 GH |
249 | if (pic_irq == piix3->dev.config[0x60 + i]) |
250 | pic_level |= piix3->pci_irq_levels[i]; | |
d2b59317 | 251 | } |
7cd9eee0 | 252 | qemu_set_irq(piix3->pic[pic_irq], pic_level); |
502a5395 PB |
253 | } |
254 | } | |
255 | ||
15a1956a | 256 | static void piix3_reset(void *opaque) |
502a5395 | 257 | { |
fd37d881 JQ |
258 | PIIX3State *d = opaque; |
259 | uint8_t *pci_conf = d->dev.config; | |
502a5395 PB |
260 | |
261 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
262 | pci_conf[0x05] = 0x00; | |
263 | pci_conf[0x06] = 0x00; | |
264 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
265 | pci_conf[0x4c] = 0x4d; | |
266 | pci_conf[0x4e] = 0x03; | |
267 | pci_conf[0x4f] = 0x00; | |
268 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
269 | pci_conf[0x61] = 0x80; |
270 | pci_conf[0x62] = 0x80; | |
271 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
272 | pci_conf[0x69] = 0x02; |
273 | pci_conf[0x70] = 0x80; | |
274 | pci_conf[0x76] = 0x0c; | |
275 | pci_conf[0x77] = 0x0c; | |
276 | pci_conf[0x78] = 0x02; | |
277 | pci_conf[0x79] = 0x00; | |
278 | pci_conf[0x80] = 0x00; | |
279 | pci_conf[0x82] = 0x00; | |
280 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
281 | pci_conf[0xa2] = 0x00; |
282 | pci_conf[0xa3] = 0x00; | |
283 | pci_conf[0xa4] = 0x00; | |
284 | pci_conf[0xa5] = 0x00; | |
285 | pci_conf[0xa6] = 0x00; | |
286 | pci_conf[0xa7] = 0x00; | |
287 | pci_conf[0xa8] = 0x0f; | |
288 | pci_conf[0xaa] = 0x00; | |
289 | pci_conf[0xab] = 0x00; | |
290 | pci_conf[0xac] = 0x00; | |
291 | pci_conf[0xae] = 0x00; | |
15a1956a | 292 | |
8372615d | 293 | memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels)); |
502a5395 PB |
294 | } |
295 | ||
d1f171bd JQ |
296 | static const VMStateDescription vmstate_piix3 = { |
297 | .name = "PIIX3", | |
298 | .version_id = 3, | |
299 | .minimum_version_id = 2, | |
300 | .minimum_version_id_old = 2, | |
301 | .fields = (VMStateField []) { | |
302 | VMSTATE_PCI_DEVICE(dev, PIIX3State), | |
303 | VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3), | |
304 | VMSTATE_END_OF_LIST() | |
da64182c | 305 | } |
d1f171bd | 306 | }; |
1941d19c | 307 | |
fd37d881 | 308 | static int piix3_initfn(PCIDevice *dev) |
502a5395 | 309 | { |
fd37d881 | 310 | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
502a5395 PB |
311 | uint8_t *pci_conf; |
312 | ||
fd37d881 | 313 | isa_bus_new(&d->dev.qdev); |
502a5395 | 314 | |
fd37d881 | 315 | pci_conf = d->dev.config; |
deb54399 AL |
316 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
317 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) | |
173a543b | 318 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
6407f373 IY |
319 | pci_conf[PCI_HEADER_TYPE] = |
320 | PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic | |
502a5395 | 321 | |
a08d4367 | 322 | qemu_register_reset(piix3_reset, d); |
81a322d4 | 323 | return 0; |
502a5395 | 324 | } |
5c2b87e3 | 325 | |
8a14daa5 GH |
326 | static PCIDeviceInfo i440fx_info[] = { |
327 | { | |
328 | .qdev.name = "i440FX", | |
329 | .qdev.desc = "Host bridge", | |
0a3bacf3 | 330 | .qdev.size = sizeof(PCII440FXState), |
be73cfe2 | 331 | .qdev.vmsd = &vmstate_i440fx, |
8a14daa5 GH |
332 | .qdev.no_user = 1, |
333 | .init = i440fx_initfn, | |
334 | .config_write = i440fx_write_config, | |
335 | },{ | |
336 | .qdev.name = "PIIX3", | |
337 | .qdev.desc = "ISA bridge", | |
fd37d881 | 338 | .qdev.size = sizeof(PIIX3State), |
be73cfe2 | 339 | .qdev.vmsd = &vmstate_piix3, |
8a14daa5 GH |
340 | .qdev.no_user = 1, |
341 | .init = piix3_initfn, | |
8a14daa5 GH |
342 | },{ |
343 | /* end of list */ | |
344 | } | |
345 | }; | |
346 | ||
347 | static SysBusDeviceInfo i440fx_pcihost_info = { | |
348 | .init = i440fx_pcihost_initfn, | |
349 | .qdev.name = "i440FX-pcihost", | |
350 | .qdev.size = sizeof(I440FXState), | |
351 | .qdev.no_user = 1, | |
352 | }; | |
353 | ||
354 | static void i440fx_register(void) | |
355 | { | |
356 | sysbus_register_withprop(&i440fx_pcihost_info); | |
357 | pci_qdev_register_many(i440fx_info); | |
358 | } | |
359 | device_init(i440fx_register); |