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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "pc.h" | |
27 | #include "pci.h" | |
4f5e19e6 | 28 | #include "pci_host.h" |
f75247f1 | 29 | #include "isa.h" |
8a14daa5 | 30 | #include "sysbus.h" |
bf1b0071 | 31 | #include "range.h" |
41445300 | 32 | #include "xen.h" |
87ecb68b | 33 | |
56594fe3 IY |
34 | /* |
35 | * I440FX chipset data sheet. | |
36 | * http://download.intel.com/design/chipsets/datashts/29054901.pdf | |
37 | */ | |
38 | ||
67c332fd AF |
39 | typedef struct I440FXState { |
40 | PCIHostState parent_obj; | |
41 | } I440FXState; | |
502a5395 | 42 | |
ab431c28 | 43 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 44 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 45 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 46 | #define PIIX_PIRQC 0x60 |
e735b55a | 47 | |
fd37d881 JQ |
48 | typedef struct PIIX3State { |
49 | PCIDevice dev; | |
ab431c28 IY |
50 | |
51 | /* | |
52 | * bitmap to track pic levels. | |
53 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
54 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
55 | * | |
56 | * PIRQ is mapped to PIC pins, we track it by | |
57 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
58 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
59 | */ | |
60 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
61 | #error "unable to encode pic state in 64bit in pic_levels." | |
62 | #endif | |
63 | uint64_t pic_levels; | |
64 | ||
bd7dce87 | 65 | qemu_irq *pic; |
e735b55a IY |
66 | |
67 | /* This member isn't used. Just for save/load compatibility */ | |
68 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
7cd9eee0 | 69 | } PIIX3State; |
bd7dce87 | 70 | |
ae0a5466 | 71 | typedef struct PAMMemoryRegion { |
2725aec7 AK |
72 | MemoryRegion alias[4]; /* index = PAM value */ |
73 | unsigned current; | |
ae0a5466 AK |
74 | } PAMMemoryRegion; |
75 | ||
0a3bacf3 JQ |
76 | struct PCII440FXState { |
77 | PCIDevice dev; | |
ae0a5466 AK |
78 | MemoryRegion *system_memory; |
79 | MemoryRegion *pci_address_space; | |
80 | MemoryRegion *ram_memory; | |
81 | MemoryRegion pci_hole; | |
82 | MemoryRegion pci_hole_64bit; | |
83 | PAMMemoryRegion pam_regions[13]; | |
84 | MemoryRegion smram_region; | |
6c009fa4 | 85 | uint8_t smm_enabled; |
0a3bacf3 JQ |
86 | }; |
87 | ||
f2c688bb IY |
88 | |
89 | #define I440FX_PAM 0x59 | |
90 | #define I440FX_PAM_SIZE 7 | |
91 | #define I440FX_SMRAM 0x72 | |
92 | ||
ab431c28 | 93 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 94 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
95 | static void piix3_write_config_xen(PCIDevice *dev, |
96 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
97 | |
98 | /* return the global irq number corresponding to a given device irq | |
99 | pin. We could also use the bus number to have a more precise | |
100 | mapping. */ | |
ab431c28 | 101 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
102 | { |
103 | int slot_addend; | |
104 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 105 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 106 | } |
502a5395 | 107 | |
2725aec7 AK |
108 | static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem, |
109 | uint32_t start, uint32_t size) | |
84631fd7 | 110 | { |
2725aec7 AK |
111 | int i; |
112 | ||
113 | /* RAM */ | |
114 | memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size); | |
115 | /* ROM (XXX: not quite correct) */ | |
116 | memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size); | |
117 | memory_region_set_readonly(&mem->alias[1], true); | |
118 | ||
119 | /* XXX: should distinguish read/write cases */ | |
120 | memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space, | |
121 | start, size); | |
122 | memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space, | |
123 | start, size); | |
124 | ||
125 | for (i = 0; i < 4; ++i) { | |
126 | memory_region_set_enabled(&mem->alias[i], false); | |
127 | memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1); | |
ae0a5466 | 128 | } |
2725aec7 AK |
129 | mem->current = 0; |
130 | } | |
84631fd7 | 131 | |
2725aec7 AK |
132 | static void update_pam(PAMMemoryRegion *pam, unsigned r) |
133 | { | |
134 | memory_region_set_enabled(&pam->alias[pam->current], false); | |
135 | pam->current = r; | |
136 | memory_region_set_enabled(&pam->alias[pam->current], true); | |
84631fd7 | 137 | } |
ee0ea1d0 | 138 | |
0a3bacf3 | 139 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 FB |
140 | { |
141 | int i, r; | |
ae0a5466 | 142 | uint32_t smram; |
b41e1ed4 | 143 | bool smram_enabled; |
84631fd7 | 144 | |
72124c01 | 145 | memory_region_transaction_begin(); |
2725aec7 | 146 | update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3); |
84631fd7 | 147 | for(i = 0; i < 12; i++) { |
f2c688bb | 148 | r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; |
2725aec7 | 149 | update_pam(&d->pam_regions[i+1], r); |
ee0ea1d0 | 150 | } |
f2c688bb | 151 | smram = d->dev.config[I440FX_SMRAM]; |
b41e1ed4 AK |
152 | smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40); |
153 | memory_region_set_enabled(&d->smram_region, !smram_enabled); | |
72124c01 | 154 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
155 | } |
156 | ||
f885f1ea | 157 | static void i440fx_set_smm(int val, void *arg) |
ee0ea1d0 | 158 | { |
f885f1ea IY |
159 | PCII440FXState *d = arg; |
160 | ||
ee0ea1d0 | 161 | val = (val != 0); |
6c009fa4 JQ |
162 | if (d->smm_enabled != val) { |
163 | d->smm_enabled = val; | |
ee0ea1d0 FB |
164 | i440fx_update_memory_mappings(d); |
165 | } | |
166 | } | |
167 | ||
168 | ||
0a3bacf3 | 169 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
170 | uint32_t address, uint32_t val, int len) |
171 | { | |
0a3bacf3 JQ |
172 | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
173 | ||
ee0ea1d0 | 174 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 175 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
176 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
177 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 178 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 179 | } |
ee0ea1d0 FB |
180 | } |
181 | ||
0c7d19e5 | 182 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 183 | { |
0a3bacf3 | 184 | PCII440FXState *d = opaque; |
52fc1d83 | 185 | int ret, i; |
ee0ea1d0 | 186 | |
0a3bacf3 | 187 | ret = pci_device_load(&d->dev, f); |
ee0ea1d0 FB |
188 | if (ret < 0) |
189 | return ret; | |
190 | i440fx_update_memory_mappings(d); | |
6c009fa4 | 191 | qemu_get_8s(f, &d->smm_enabled); |
52fc1d83 | 192 | |
e735b55a IY |
193 | if (version_id == 2) { |
194 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
195 | qemu_get_be32(f); /* dummy load for compatibility */ | |
196 | } | |
197 | } | |
52fc1d83 | 198 | |
ee0ea1d0 FB |
199 | return 0; |
200 | } | |
201 | ||
e59fb374 | 202 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
203 | { |
204 | PCII440FXState *d = opaque; | |
205 | ||
206 | i440fx_update_memory_mappings(d); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static const VMStateDescription vmstate_i440fx = { | |
211 | .name = "I440FX", | |
212 | .version_id = 3, | |
213 | .minimum_version_id = 3, | |
214 | .minimum_version_id_old = 1, | |
215 | .load_state_old = i440fx_load_old, | |
752ff2fa | 216 | .post_load = i440fx_post_load, |
0c7d19e5 JQ |
217 | .fields = (VMStateField []) { |
218 | VMSTATE_PCI_DEVICE(dev, PCII440FXState), | |
219 | VMSTATE_UINT8(smm_enabled, PCII440FXState), | |
220 | VMSTATE_END_OF_LIST() | |
221 | } | |
222 | }; | |
223 | ||
81a322d4 | 224 | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
502a5395 | 225 | { |
8558d942 | 226 | PCIHostState *s = PCI_HOST_BRIDGE(dev); |
502a5395 | 227 | |
d0ed8076 AK |
228 | memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, |
229 | "pci-conf-idx", 4); | |
230 | sysbus_add_io(dev, 0xcf8, &s->conf_mem); | |
231 | sysbus_init_ioports(&s->busdev, 0xcf8, 4); | |
232 | ||
233 | memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, | |
234 | "pci-conf-data", 4); | |
235 | sysbus_add_io(dev, 0xcfc, &s->data_mem); | |
236 | sysbus_init_ioports(&s->busdev, 0xcfc, 4); | |
502a5395 | 237 | |
81a322d4 | 238 | return 0; |
8a14daa5 | 239 | } |
502a5395 | 240 | |
0a3bacf3 | 241 | static int i440fx_initfn(PCIDevice *dev) |
8a14daa5 | 242 | { |
0a3bacf3 | 243 | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
ee0ea1d0 | 244 | |
f2c688bb | 245 | d->dev.config[I440FX_SMRAM] = 0x02; |
ee0ea1d0 | 246 | |
f885f1ea | 247 | cpu_smm_register(&i440fx_set_smm, d); |
81a322d4 | 248 | return 0; |
8a14daa5 GH |
249 | } |
250 | ||
41445300 AP |
251 | static PCIBus *i440fx_common_init(const char *device_name, |
252 | PCII440FXState **pi440fx_state, | |
253 | int *piix3_devfn, | |
60573079 | 254 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
255 | MemoryRegion *address_space_mem, |
256 | MemoryRegion *address_space_io, | |
ae0a5466 | 257 | ram_addr_t ram_size, |
a8170e5e AK |
258 | hwaddr pci_hole_start, |
259 | hwaddr pci_hole_size, | |
260 | hwaddr pci_hole64_start, | |
261 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
262 | MemoryRegion *pci_address_space, |
263 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
264 | { |
265 | DeviceState *dev; | |
266 | PCIBus *b; | |
267 | PCIDevice *d; | |
8558d942 | 268 | PCIHostState *s; |
7cd9eee0 | 269 | PIIX3State *piix3; |
ae0a5466 | 270 | PCII440FXState *f; |
2725aec7 | 271 | unsigned i; |
8a14daa5 GH |
272 | |
273 | dev = qdev_create(NULL, "i440FX-pcihost"); | |
8558d942 | 274 | s = PCI_HOST_BRIDGE(dev); |
aee97b84 | 275 | s->address_space = address_space_mem; |
67c332fd | 276 | b = pci_bus_new(dev, NULL, pci_address_space, |
aee97b84 | 277 | address_space_io, 0); |
8a14daa5 | 278 | s->bus = b; |
f05f6b4a | 279 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 280 | qdev_init_nofail(dev); |
8a14daa5 | 281 | |
41445300 | 282 | d = pci_create_simple(b, 0, device_name); |
0a3bacf3 | 283 | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
ae0a5466 AK |
284 | f = *pi440fx_state; |
285 | f->system_memory = address_space_mem; | |
286 | f->pci_address_space = pci_address_space; | |
287 | f->ram_memory = ram_memory; | |
288 | memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, | |
289 | pci_hole_start, pci_hole_size); | |
290 | memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); | |
291 | memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64", | |
292 | f->pci_address_space, | |
293 | pci_hole64_start, pci_hole64_size); | |
294 | if (pci_hole64_size) { | |
295 | memory_region_add_subregion(f->system_memory, pci_hole64_start, | |
296 | &f->pci_hole_64bit); | |
297 | } | |
298 | memory_region_init_alias(&f->smram_region, "smram-region", | |
299 | f->pci_address_space, 0xa0000, 0x20000); | |
b41e1ed4 AK |
300 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
301 | &f->smram_region, 1); | |
302 | memory_region_set_enabled(&f->smram_region, false); | |
2725aec7 AK |
303 | init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000); |
304 | for (i = 0; i < 12; ++i) { | |
305 | init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000); | |
306 | } | |
8a14daa5 | 307 | |
bf09551a SS |
308 | /* Xen supports additional interrupt routes from the PCI devices to |
309 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
310 | * connected to the IOAPIC directly. | |
311 | * These additional routes can be discovered through ACPI. */ | |
312 | if (xen_enabled()) { | |
313 | piix3 = DO_UPCAST(PIIX3State, dev, | |
314 | pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); | |
315 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, | |
316 | piix3, XEN_PIIX_NUM_PIRQS); | |
317 | } else { | |
318 | piix3 = DO_UPCAST(PIIX3State, dev, | |
319 | pci_create_simple_multifunction(b, -1, true, "PIIX3")); | |
320 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, | |
321 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 322 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 323 | } |
7cd9eee0 | 324 | piix3->pic = pic; |
60573079 HP |
325 | *isa_bus = DO_UPCAST(ISABus, qbus, |
326 | qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); | |
41445300 | 327 | |
7cd9eee0 | 328 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 329 | |
ec5f92ce BW |
330 | ram_size = ram_size / 8 / 1024 / 1024; |
331 | if (ram_size > 255) | |
332 | ram_size = 255; | |
333 | (*pi440fx_state)->dev.config[0x57]=ram_size; | |
334 | ||
ae0a5466 AK |
335 | i440fx_update_memory_mappings(f); |
336 | ||
502a5395 PB |
337 | return b; |
338 | } | |
339 | ||
41445300 | 340 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, |
60573079 | 341 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
342 | MemoryRegion *address_space_mem, |
343 | MemoryRegion *address_space_io, | |
ae0a5466 | 344 | ram_addr_t ram_size, |
a8170e5e AK |
345 | hwaddr pci_hole_start, |
346 | hwaddr pci_hole_size, | |
347 | hwaddr pci_hole64_start, | |
348 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
349 | MemoryRegion *pci_memory, MemoryRegion *ram_memory) |
350 | ||
41445300 AP |
351 | { |
352 | PCIBus *b; | |
353 | ||
60573079 | 354 | b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic, |
ae0a5466 AK |
355 | address_space_mem, address_space_io, ram_size, |
356 | pci_hole_start, pci_hole_size, | |
d50c6c8b | 357 | pci_hole64_start, pci_hole64_size, |
ae0a5466 | 358 | pci_memory, ram_memory); |
41445300 AP |
359 | return b; |
360 | } | |
361 | ||
502a5395 | 362 | /* PIIX3 PCI to ISA bridge */ |
ab431c28 IY |
363 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
364 | { | |
365 | qemu_set_irq(piix3->pic[pic_irq], | |
366 | !!(piix3->pic_levels & | |
09de0f46 | 367 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
368 | (pic_irq * PIIX_NUM_PIRQS)))); |
369 | } | |
502a5395 | 370 | |
afe3ef1d | 371 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
372 | { |
373 | int pic_irq; | |
374 | uint64_t mask; | |
375 | ||
376 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
377 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
378 | return; | |
379 | } | |
380 | ||
381 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
382 | piix3->pic_levels &= ~mask; | |
383 | piix3->pic_levels |= mask * !!level; | |
384 | ||
afe3ef1d | 385 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
386 | } |
387 | ||
388 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 389 | { |
7cd9eee0 | 390 | PIIX3State *piix3 = opaque; |
afe3ef1d | 391 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 392 | } |
502a5395 | 393 | |
3afa9bb4 MT |
394 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
395 | { | |
396 | PIIX3State *piix3 = opaque; | |
397 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
398 | PCIINTxRoute route; | |
399 | ||
400 | if (irq < PIIX_NUM_PIC_IRQS) { | |
401 | route.mode = PCI_INTX_ENABLED; | |
402 | route.irq = irq; | |
403 | } else { | |
404 | route.mode = PCI_INTX_DISABLED; | |
405 | route.irq = -1; | |
406 | } | |
407 | return route; | |
408 | } | |
409 | ||
ab431c28 IY |
410 | /* irq routing is changed. so rebuild bitmap */ |
411 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
412 | { | |
413 | int pirq; | |
414 | ||
415 | piix3->pic_levels = 0; | |
416 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
417 | piix3_set_irq_level(piix3, pirq, | |
afe3ef1d | 418 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
ab431c28 IY |
419 | } |
420 | } | |
421 | ||
422 | static void piix3_write_config(PCIDevice *dev, | |
423 | uint32_t address, uint32_t val, int len) | |
424 | { | |
425 | pci_default_write_config(dev, address, val, len); | |
426 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
427 | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); | |
428 | int pic_irq; | |
0ae16251 JK |
429 | |
430 | pci_bus_fire_intx_routing_notifier(piix3->dev.bus); | |
ab431c28 IY |
431 | piix3_update_irq_levels(piix3); |
432 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
433 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 434 | } |
502a5395 PB |
435 | } |
436 | } | |
437 | ||
bf09551a SS |
438 | static void piix3_write_config_xen(PCIDevice *dev, |
439 | uint32_t address, uint32_t val, int len) | |
440 | { | |
441 | xen_piix_pci_write_config_client(address, val, len); | |
442 | piix3_write_config(dev, address, val, len); | |
443 | } | |
444 | ||
15a1956a | 445 | static void piix3_reset(void *opaque) |
502a5395 | 446 | { |
fd37d881 JQ |
447 | PIIX3State *d = opaque; |
448 | uint8_t *pci_conf = d->dev.config; | |
502a5395 PB |
449 | |
450 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
451 | pci_conf[0x05] = 0x00; | |
452 | pci_conf[0x06] = 0x00; | |
453 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
454 | pci_conf[0x4c] = 0x4d; | |
455 | pci_conf[0x4e] = 0x03; | |
456 | pci_conf[0x4f] = 0x00; | |
457 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
458 | pci_conf[0x61] = 0x80; |
459 | pci_conf[0x62] = 0x80; | |
460 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
461 | pci_conf[0x69] = 0x02; |
462 | pci_conf[0x70] = 0x80; | |
463 | pci_conf[0x76] = 0x0c; | |
464 | pci_conf[0x77] = 0x0c; | |
465 | pci_conf[0x78] = 0x02; | |
466 | pci_conf[0x79] = 0x00; | |
467 | pci_conf[0x80] = 0x00; | |
468 | pci_conf[0x82] = 0x00; | |
469 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
470 | pci_conf[0xa2] = 0x00; |
471 | pci_conf[0xa3] = 0x00; | |
472 | pci_conf[0xa4] = 0x00; | |
473 | pci_conf[0xa5] = 0x00; | |
474 | pci_conf[0xa6] = 0x00; | |
475 | pci_conf[0xa7] = 0x00; | |
476 | pci_conf[0xa8] = 0x0f; | |
477 | pci_conf[0xaa] = 0x00; | |
478 | pci_conf[0xab] = 0x00; | |
479 | pci_conf[0xac] = 0x00; | |
480 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
481 | |
482 | d->pic_levels = 0; | |
483 | } | |
484 | ||
485 | static int piix3_post_load(void *opaque, int version_id) | |
486 | { | |
487 | PIIX3State *piix3 = opaque; | |
488 | piix3_update_irq_levels(piix3); | |
489 | return 0; | |
e735b55a | 490 | } |
15a1956a | 491 | |
e735b55a IY |
492 | static void piix3_pre_save(void *opaque) |
493 | { | |
494 | int i; | |
495 | PIIX3State *piix3 = opaque; | |
496 | ||
497 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
498 | piix3->pci_irq_levels_vmstate[i] = | |
499 | pci_bus_get_irq_level(piix3->dev.bus, i); | |
500 | } | |
502a5395 PB |
501 | } |
502 | ||
d1f171bd JQ |
503 | static const VMStateDescription vmstate_piix3 = { |
504 | .name = "PIIX3", | |
505 | .version_id = 3, | |
506 | .minimum_version_id = 2, | |
507 | .minimum_version_id_old = 2, | |
ab431c28 | 508 | .post_load = piix3_post_load, |
e735b55a | 509 | .pre_save = piix3_pre_save, |
d1f171bd JQ |
510 | .fields = (VMStateField []) { |
511 | VMSTATE_PCI_DEVICE(dev, PIIX3State), | |
e735b55a IY |
512 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
513 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 514 | VMSTATE_END_OF_LIST() |
da64182c | 515 | } |
d1f171bd | 516 | }; |
1941d19c | 517 | |
fd37d881 | 518 | static int piix3_initfn(PCIDevice *dev) |
502a5395 | 519 | { |
fd37d881 | 520 | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
502a5395 | 521 | |
c2d0d012 | 522 | isa_bus_new(&d->dev.qdev, pci_address_space_io(dev)); |
a08d4367 | 523 | qemu_register_reset(piix3_reset, d); |
81a322d4 | 524 | return 0; |
502a5395 | 525 | } |
5c2b87e3 | 526 | |
40021f08 AL |
527 | static void piix3_class_init(ObjectClass *klass, void *data) |
528 | { | |
39bffca2 | 529 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
530 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
531 | ||
39bffca2 AL |
532 | dc->desc = "ISA bridge"; |
533 | dc->vmsd = &vmstate_piix3; | |
534 | dc->no_user = 1, | |
40021f08 AL |
535 | k->no_hotplug = 1; |
536 | k->init = piix3_initfn; | |
537 | k->config_write = piix3_write_config; | |
538 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
539 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) | |
540 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
541 | } | |
542 | ||
4240abff | 543 | static const TypeInfo piix3_info = { |
39bffca2 AL |
544 | .name = "PIIX3", |
545 | .parent = TYPE_PCI_DEVICE, | |
546 | .instance_size = sizeof(PIIX3State), | |
547 | .class_init = piix3_class_init, | |
e855761c AL |
548 | }; |
549 | ||
40021f08 AL |
550 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
551 | { | |
39bffca2 | 552 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
553 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
554 | ||
39bffca2 AL |
555 | dc->desc = "ISA bridge"; |
556 | dc->vmsd = &vmstate_piix3; | |
557 | dc->no_user = 1; | |
40021f08 AL |
558 | k->no_hotplug = 1; |
559 | k->init = piix3_initfn; | |
560 | k->config_write = piix3_write_config_xen; | |
561 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
562 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) | |
563 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
e855761c AL |
564 | }; |
565 | ||
4240abff | 566 | static const TypeInfo piix3_xen_info = { |
39bffca2 AL |
567 | .name = "PIIX3-xen", |
568 | .parent = TYPE_PCI_DEVICE, | |
569 | .instance_size = sizeof(PIIX3State), | |
570 | .class_init = piix3_xen_class_init, | |
40021f08 AL |
571 | }; |
572 | ||
573 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
574 | { | |
39bffca2 | 575 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
576 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
577 | ||
578 | k->no_hotplug = 1; | |
579 | k->init = i440fx_initfn; | |
580 | k->config_write = i440fx_write_config; | |
581 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
582 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
583 | k->revision = 0x02; | |
584 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
585 | dc->desc = "Host bridge"; |
586 | dc->no_user = 1; | |
587 | dc->vmsd = &vmstate_i440fx; | |
40021f08 AL |
588 | } |
589 | ||
4240abff | 590 | static const TypeInfo i440fx_info = { |
39bffca2 AL |
591 | .name = "i440FX", |
592 | .parent = TYPE_PCI_DEVICE, | |
593 | .instance_size = sizeof(PCII440FXState), | |
594 | .class_init = i440fx_class_init, | |
8a14daa5 GH |
595 | }; |
596 | ||
999e12bb AL |
597 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
598 | { | |
39bffca2 | 599 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
600 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
601 | ||
602 | k->init = i440fx_pcihost_initfn; | |
39bffca2 AL |
603 | dc->fw_name = "pci"; |
604 | dc->no_user = 1; | |
999e12bb AL |
605 | } |
606 | ||
4240abff | 607 | static const TypeInfo i440fx_pcihost_info = { |
39bffca2 | 608 | .name = "i440FX-pcihost", |
8558d942 | 609 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
610 | .instance_size = sizeof(I440FXState), |
611 | .class_init = i440fx_pcihost_class_init, | |
8a14daa5 GH |
612 | }; |
613 | ||
83f7d43a | 614 | static void i440fx_register_types(void) |
8a14daa5 | 615 | { |
39bffca2 AL |
616 | type_register_static(&i440fx_info); |
617 | type_register_static(&piix3_info); | |
618 | type_register_static(&piix3_xen_info); | |
619 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 620 | } |
83f7d43a AF |
621 | |
622 | type_init(i440fx_register_types) |