[qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "pci_host.h"
#include "isa.h"
#include "sysbus.h"
#include "range.h"
#include "xen.h"

/*
 * I440FX chipset data sheet.
 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
 */

typedef PCIHostState I440FXState;

#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS      128ULL
#define PIIX_PIRQC              0x60

typedef struct PIIX3State {
    PCIDevice dev;

    /*
     * bitmap to track pic levels.
     * The pic level is the logical OR of all the PCI irqs mapped to it
     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
     *
     * PIRQ is mapped to PIC pins, we track it by
     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
     * pic_irq * PIIX_NUM_PIRQS + pirq
     */
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
    uint64_t pic_levels;

    qemu_irq *pic;

    /* This member isn't used. Just for save/load compatibility */
    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;

typedef struct PAMMemoryRegion {
    MemoryRegion mem;
    bool initialized;
} PAMMemoryRegion;

struct PCII440FXState {
    PCIDevice dev;
    MemoryRegion *system_memory;
    MemoryRegion *pci_address_space;
    MemoryRegion *ram_memory;
    MemoryRegion pci_hole;
    MemoryRegion pci_hole_64bit;
    PAMMemoryRegion pam_regions[13];
    MemoryRegion smram_region;
    uint8_t smm_enabled;
    bool smram_enabled;
    PIIX3State *piix3;
};


#define I440FX_PAM      0x59
#define I440FX_PAM_SIZE 7
#define I440FX_SMRAM    0x72

static void piix3_set_irq(void *opaque, int pirq, int level);
static void piix3_write_config_xen(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (pci_intx + slot_addend) & 3;
}

static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
                       PAMMemoryRegion *mem)
{
    if (mem->initialized) {
        memory_region_del_subregion(d->system_memory, &mem->mem);
        memory_region_destroy(&mem->mem);
    }

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
                                 start, end - start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
                                 start, end - start);
        memory_region_set_readonly(&mem->mem, true);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
                                 start, end - start);
        break;
    }
    memory_region_add_subregion_overlap(d->system_memory,
                                        start, &mem->mem, 1);
    mem->initialized = true;
}

static void i440fx_update_memory_mappings(PCII440FXState *d)
{
    int i, r;
    uint32_t smram;

    memory_region_transaction_begin();
    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
               &d->pam_regions[0]);
    for(i = 0; i < 12; i++) {
        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
                   &d->pam_regions[i+1]);
    }
    smram = d->dev.config[I440FX_SMRAM];
    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        if (!d->smram_enabled) {
            memory_region_del_subregion(d->system_memory, &d->smram_region);
            d->smram_enabled = true;
        }
    } else {
        if (d->smram_enabled) {
            memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
                                                &d->smram_region, 1);
            d->smram_enabled = false;
        }
    }
    memory_region_transaction_commit();
}

static void i440fx_set_smm(int val, void *arg)
{
    PCII440FXState *d = arg;

    val = (val != 0);
    if (d->smm_enabled != val) {
        d->smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


static void i440fx_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
        range_covers_byte(address, len, I440FX_SMRAM)) {
        i440fx_update_memory_mappings(d);
    }
}

static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
    PCII440FXState *d = opaque;
    int ret, i;

    ret = pci_device_load(&d->dev, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &d->smm_enabled);

    if (version_id == 2) {
        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
            qemu_get_be32(f); /* dummy load for compatibility */
        }
    }

    return 0;
}

static int i440fx_post_load(void *opaque, int version_id)
{
    PCII440FXState *d = opaque;

    i440fx_update_memory_mappings(d);
    return 0;
}

static const VMStateDescription vmstate_i440fx = {
    .name = "I440FX",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = i440fx_load_old,
    .post_load = i440fx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
        VMSTATE_UINT8(smm_enabled, PCII440FXState),
        VMSTATE_END_OF_LIST()
    }
};

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
                          "pci-conf-idx", 4);
    sysbus_add_io(dev, 0xcf8, &s->conf_mem);
    sysbus_init_ioports(&s->busdev, 0xcf8, 4);

    memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
                          "pci-conf-data", 4);
    sysbus_add_io(dev, 0xcfc, &s->data_mem);
    sysbus_init_ioports(&s->busdev, 0xcfc, 4);

    return 0;
}

static int i440fx_initfn(PCIDevice *dev)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    d->dev.config[I440FX_SMRAM] = 0x02;

    cpu_smm_register(&i440fx_set_smm, d);
    return 0;
}

static PCIBus *i440fx_common_init(const char *device_name,
                                  PCII440FXState **pi440fx_state,
                                  int *piix3_devfn,
                                  qemu_irq *pic,
                                  MemoryRegion *address_space_mem,
                                  MemoryRegion *address_space_io,
                                  ram_addr_t ram_size,
                                  target_phys_addr_t pci_hole_start,
                                  target_phys_addr_t pci_hole_size,
                                  target_phys_addr_t pci_hole64_start,
                                  target_phys_addr_t pci_hole64_size,
                                  MemoryRegion *pci_address_space,
                                  MemoryRegion *ram_memory)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;
    PIIX3State *piix3;
    PCII440FXState *f;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    s->address_space = address_space_mem;
    b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
                    address_space_io, 0);
    s->bus = b;
    qdev_init_nofail(dev);

    d = pci_create_simple(b, 0, device_name);
    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
    f = *pi440fx_state;
    f->system_memory = address_space_mem;
    f->pci_address_space = pci_address_space;
    f->ram_memory = ram_memory;
    memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
                             pci_hole_start, pci_hole_size);
    memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
    memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
                             f->pci_address_space,
                             pci_hole64_start, pci_hole64_size);
    if (pci_hole64_size) {
        memory_region_add_subregion(f->system_memory, pci_hole64_start,
                                    &f->pci_hole_64bit);
    }
    memory_region_init_alias(&f->smram_region, "smram-region",
                             f->pci_address_space, 0xa0000, 0x20000);
    f->smram_enabled = true;

    /* Xen supports additional interrupt routes from the PCI devices to
     * the IOAPIC: the four pins of each PCI device on the bus are also
     * connected to the IOAPIC directly.
     * These additional routes can be discovered through ACPI. */
    if (xen_enabled()) {
        piix3 = DO_UPCAST(PIIX3State, dev,
                pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
                piix3, XEN_PIIX_NUM_PIRQS);
    } else {
        piix3 = DO_UPCAST(PIIX3State, dev,
                pci_create_simple_multifunction(b, -1, true, "PIIX3"));
        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
                PIIX_NUM_PIRQS);
    }
    piix3->pic = pic;

    (*pi440fx_state)->piix3 = piix3;

    *piix3_devfn = piix3->dev.devfn;

    ram_size = ram_size / 8 / 1024 / 1024;
    if (ram_size > 255)
        ram_size = 255;
    (*pi440fx_state)->dev.config[0x57]=ram_size;

    i440fx_update_memory_mappings(f);

    return b;
}

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
                    qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size,
                    target_phys_addr_t pci_hole_start,
                    target_phys_addr_t pci_hole_size,
                    target_phys_addr_t pci_hole64_start,
                    target_phys_addr_t pci_hole64_size,
                    MemoryRegion *pci_memory, MemoryRegion *ram_memory)

{
    PCIBus *b;

    b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
                           address_space_mem, address_space_io, ram_size,
                           pci_hole_start, pci_hole_size,
                           pci_hole64_size, pci_hole64_size,
                           pci_memory, ram_memory);
    return b;
}

/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
    qemu_set_irq(piix3->pic[pic_irq],
                 !!(piix3->pic_levels &
                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
                     (pic_irq * PIIX_NUM_PIRQS))));
}

static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
    int pic_irq;
    uint64_t mask;

    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
    piix3->pic_levels &= ~mask;
    piix3->pic_levels |= mask * !!level;

    piix3_set_irq_pic(piix3, pic_irq);
}

static void piix3_set_irq(void *opaque, int pirq, int level)
{
    PIIX3State *piix3 = opaque;
    piix3_set_irq_level(piix3, pirq, level);
}

/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
    int pirq;

    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level(piix3, pirq,
                            pci_bus_get_irq_level(piix3->dev.bus, pirq));
    }
}

static void piix3_write_config(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
        PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
        int pic_irq;
        piix3_update_irq_levels(piix3);
        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
            piix3_set_irq_pic(piix3, pic_irq);
        }
    }
}

static void piix3_write_config_xen(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    xen_piix_pci_write_config_client(address, val, len);
    piix3_write_config(dev, address, val, len);
}

static void piix3_reset(void *opaque)
{
    PIIX3State *d = opaque;
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    d->pic_levels = 0;
}

static int piix3_post_load(void *opaque, int version_id)
{
    PIIX3State *piix3 = opaque;
    piix3_update_irq_levels(piix3);
    return 0;
}

static void piix3_pre_save(void *opaque)
{
    int i;
    PIIX3State *piix3 = opaque;

    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
        piix3->pci_irq_levels_vmstate[i] =
            pci_bus_get_irq_level(piix3->dev.bus, i);
    }
}

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .post_load = piix3_post_load,
    .pre_save = piix3_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                              PIIX_NUM_PIRQS, 3),
        VMSTATE_END_OF_LIST()
    }
};

static int piix3_initfn(PCIDevice *dev)
{
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);

    isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
    qemu_register_reset(piix3_reset, d);
    return 0;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.vmsd    = &vmstate_i440fx,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82441,
        .revision     = 0x02,
        .class_id     = PCI_CLASS_BRIDGE_HOST,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
        .class_id     = PCI_CLASS_BRIDGE_ISA,
    },{
        .qdev.name    = "PIIX3-xen",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config_xen,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
        .class_id     = PCI_CLASS_BRIDGE_ISA,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.fw_name = "pci",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
4f5e19e6	28	#include "pci_host.h"
f75247f1	29	#include "isa.h"
8a14daa5	30	#include "sysbus.h"
bf1b0071	31	#include "range.h"
41445300	32	#include "xen.h"
87ecb68b	33
56594fe3 IY	34	/*
	35	* I440FX chipset data sheet.
	36	* http://download.intel.com/design/chipsets/datashts/29054901.pdf
	37	*/
	38
502a5395 PB	39	typedef PCIHostState I440FXState;
502a5395 PB	40
ab431c28	41	#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
e735b55a	42	#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
bf09551a	43	#define XEN_PIIX_NUM_PIRQS 128ULL
ab431c28	44	#define PIIX_PIRQC 0x60
e735b55a	45
fd37d881 JQ	46	typedef struct PIIX3State {
fd37d881 JQ	47	PCIDevice dev;
ab431c28 IY	48
	49	/*
	50	* bitmap to track pic levels.
	51	* The pic level is the logical OR of all the PCI irqs mapped to it
	52	* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
	53	*
	54	* PIRQ is mapped to PIC pins, we track it by
	55	* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
	56	* pic_irq * PIIX_NUM_PIRQS + pirq
	57	*/
	58	#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
	59	#error "unable to encode pic state in 64bit in pic_levels."
	60	#endif
	61	uint64_t pic_levels;
	62
bd7dce87	63	qemu_irq *pic;
e735b55a IY	64
	65	/* This member isn't used. Just for save/load compatibility */
	66	int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
7cd9eee0	67	} PIIX3State;
bd7dce87	68
ae0a5466 AK	69	typedef struct PAMMemoryRegion {
	70	MemoryRegion mem;
	71	bool initialized;
	72	} PAMMemoryRegion;
	73
0a3bacf3 JQ	74	struct PCII440FXState {
0a3bacf3 JQ	75	PCIDevice dev;
ae0a5466 AK	76	MemoryRegion *system_memory;
	77	MemoryRegion *pci_address_space;
	78	MemoryRegion *ram_memory;
	79	MemoryRegion pci_hole;
	80	MemoryRegion pci_hole_64bit;
	81	PAMMemoryRegion pam_regions[13];
	82	MemoryRegion smram_region;
6c009fa4	83	uint8_t smm_enabled;
ae0a5466	84	bool smram_enabled;
7cd9eee0	85	PIIX3State *piix3;
0a3bacf3 JQ	86	};
0a3bacf3 JQ	87
f2c688bb IY	88
	89	#define I440FX_PAM 0x59
	90	#define I440FX_PAM_SIZE 7
	91	#define I440FX_SMRAM 0x72
	92
ab431c28	93	static void piix3_set_irq(void *opaque, int pirq, int level);
bf09551a SS	94	static void piix3_write_config_xen(PCIDevice *dev,
bf09551a SS	95	uint32_t address, uint32_t val, int len);
d2b59317 PB	96
	97	/* return the global irq number corresponding to a given device irq
	98	pin. We could also use the bus number to have a more precise
	99	mapping. */
ab431c28	100	static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
d2b59317 PB	101	{
	102	int slot_addend;
	103	slot_addend = (pci_dev->devfn >> 3) - 1;
ab431c28	104	return (pci_intx + slot_addend) & 3;
d2b59317	105	}
502a5395	106
ae0a5466 AK	107	static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
ae0a5466 AK	108	PAMMemoryRegion *mem)
84631fd7	109	{
ae0a5466 AK	110	if (mem->initialized) {
	111	memory_region_del_subregion(d->system_memory, &mem->mem);
	112	memory_region_destroy(&mem->mem);
	113	}
84631fd7 FB	114
	115	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	116	switch(r) {
	117	case 3:
	118	/* RAM */
ae0a5466 AK	119	memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
ae0a5466 AK	120	start, end - start);
84631fd7 FB	121	break;
	122	case 1:
	123	/* ROM (XXX: not quite correct) */
ae0a5466 AK	124	memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
	125	start, end - start);
	126	memory_region_set_readonly(&mem->mem, true);
84631fd7 FB	127	break;
	128	case 2:
	129	case 0:
	130	/* XXX: should distinguish read/write cases */
ae0a5466 AK	131	memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
ae0a5466 AK	132	start, end - start);
84631fd7 FB	133	break;
84631fd7 FB	134	}
ae0a5466 AK	135	memory_region_add_subregion_overlap(d->system_memory,
	136	start, &mem->mem, 1);
	137	mem->initialized = true;
84631fd7	138	}
ee0ea1d0	139
0a3bacf3	140	static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	141	{
ee0ea1d0 FB	142	int i, r;
ae0a5466	143	uint32_t smram;
84631fd7	144
72124c01	145	memory_region_transaction_begin();
ae0a5466 AK	146	update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
ae0a5466 AK	147	&d->pam_regions[0]);
84631fd7	148	for(i = 0; i < 12; i++) {
f2c688bb	149	r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
ae0a5466 AK	150	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
ae0a5466 AK	151	&d->pam_regions[i+1]);
ee0ea1d0	152	}
f2c688bb	153	smram = d->dev.config[I440FX_SMRAM];
6c009fa4	154	if ((d->smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
ae0a5466 AK	155	if (!d->smram_enabled) {
	156	memory_region_del_subregion(d->system_memory, &d->smram_region);
	157	d->smram_enabled = true;
	158	}
84631fd7	159	} else {
ae0a5466 AK	160	if (d->smram_enabled) {
	161	memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
	162	&d->smram_region, 1);
	163	d->smram_enabled = false;
ee0ea1d0 FB	164	}
ee0ea1d0 FB	165	}
72124c01	166	memory_region_transaction_commit();
ee0ea1d0 FB	167	}
ee0ea1d0 FB	168
f885f1ea	169	static void i440fx_set_smm(int val, void *arg)
ee0ea1d0	170	{
f885f1ea IY	171	PCII440FXState *d = arg;
f885f1ea IY	172
ee0ea1d0	173	val = (val != 0);
6c009fa4 JQ	174	if (d->smm_enabled != val) {
6c009fa4 JQ	175	d->smm_enabled = val;
ee0ea1d0 FB	176	i440fx_update_memory_mappings(d);
	177	}
	178	}
	179
	180
0a3bacf3	181	static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0 FB	182	uint32_t address, uint32_t val, int len)
ee0ea1d0 FB	183	{
0a3bacf3 JQ	184	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
0a3bacf3 JQ	185
ee0ea1d0	186	/* XXX: implement SMRAM.D_LOCK */
0a3bacf3	187	pci_default_write_config(dev, address, val, len);
4da5fcd3 IY	188	if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) \|\|
4da5fcd3 IY	189	range_covers_byte(address, len, I440FX_SMRAM)) {
ee0ea1d0	190	i440fx_update_memory_mappings(d);
4da5fcd3	191	}
ee0ea1d0 FB	192	}
ee0ea1d0 FB	193
0c7d19e5	194	static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
ee0ea1d0	195	{
0a3bacf3	196	PCII440FXState *d = opaque;
52fc1d83	197	int ret, i;
ee0ea1d0	198
0a3bacf3	199	ret = pci_device_load(&d->dev, f);
ee0ea1d0 FB	200	if (ret < 0)
	201	return ret;
	202	i440fx_update_memory_mappings(d);
6c009fa4	203	qemu_get_8s(f, &d->smm_enabled);
52fc1d83	204
e735b55a IY	205	if (version_id == 2) {
	206	for (i = 0; i < PIIX_NUM_PIRQS; i++) {
	207	qemu_get_be32(f); /* dummy load for compatibility */
	208	}
	209	}
52fc1d83	210
ee0ea1d0 FB	211	return 0;
	212	}
	213
e59fb374	214	static int i440fx_post_load(void *opaque, int version_id)
0c7d19e5 JQ	215	{
	216	PCII440FXState *d = opaque;
	217
	218	i440fx_update_memory_mappings(d);
	219	return 0;
	220	}
	221
	222	static const VMStateDescription vmstate_i440fx = {
	223	.name = "I440FX",
	224	.version_id = 3,
	225	.minimum_version_id = 3,
	226	.minimum_version_id_old = 1,
	227	.load_state_old = i440fx_load_old,
752ff2fa	228	.post_load = i440fx_post_load,
0c7d19e5 JQ	229	.fields = (VMStateField []) {
	230	VMSTATE_PCI_DEVICE(dev, PCII440FXState),
	231	VMSTATE_UINT8(smm_enabled, PCII440FXState),
	232	VMSTATE_END_OF_LIST()
	233	}
	234	};
	235
81a322d4	236	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	237	{
8a14daa5	238	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395	239
d0ed8076 AK	240	memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
	241	"pci-conf-idx", 4);
	242	sysbus_add_io(dev, 0xcf8, &s->conf_mem);
	243	sysbus_init_ioports(&s->busdev, 0xcf8, 4);
	244
	245	memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
	246	"pci-conf-data", 4);
	247	sysbus_add_io(dev, 0xcfc, &s->data_mem);
	248	sysbus_init_ioports(&s->busdev, 0xcfc, 4);
502a5395	249
81a322d4	250	return 0;
8a14daa5	251	}
502a5395	252
0a3bacf3	253	static int i440fx_initfn(PCIDevice *dev)
8a14daa5	254	{
0a3bacf3	255	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0	256
f2c688bb	257	d->dev.config[I440FX_SMRAM] = 0x02;
ee0ea1d0	258
f885f1ea	259	cpu_smm_register(&i440fx_set_smm, d);
81a322d4	260	return 0;
8a14daa5 GH	261	}
8a14daa5 GH	262
41445300 AP	263	static PCIBus i440fx_common_init(const char device_name,
	264	PCII440FXState **pi440fx_state,
	265	int *piix3_devfn,
1e39101c	266	qemu_irq *pic,
aee97b84 AK	267	MemoryRegion *address_space_mem,
aee97b84 AK	268	MemoryRegion *address_space_io,
ae0a5466 AK	269	ram_addr_t ram_size,
	270	target_phys_addr_t pci_hole_start,
	271	target_phys_addr_t pci_hole_size,
	272	target_phys_addr_t pci_hole64_start,
	273	target_phys_addr_t pci_hole64_size,
	274	MemoryRegion *pci_address_space,
	275	MemoryRegion *ram_memory)
8a14daa5 GH	276	{
	277	DeviceState *dev;
	278	PCIBus *b;
	279	PCIDevice *d;
	280	I440FXState *s;
7cd9eee0	281	PIIX3State *piix3;
ae0a5466	282	PCII440FXState *f;
8a14daa5 GH	283
	284	dev = qdev_create(NULL, "i440FX-pcihost");
	285	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
aee97b84	286	s->address_space = address_space_mem;
ae0a5466	287	b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
aee97b84	288	address_space_io, 0);
8a14daa5	289	s->bus = b;
e23a1b33	290	qdev_init_nofail(dev);
8a14daa5	291
41445300	292	d = pci_create_simple(b, 0, device_name);
0a3bacf3	293	*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
ae0a5466 AK	294	f = *pi440fx_state;
	295	f->system_memory = address_space_mem;
	296	f->pci_address_space = pci_address_space;
	297	f->ram_memory = ram_memory;
	298	memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
	299	pci_hole_start, pci_hole_size);
	300	memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
	301	memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
	302	f->pci_address_space,
	303	pci_hole64_start, pci_hole64_size);
	304	if (pci_hole64_size) {
	305	memory_region_add_subregion(f->system_memory, pci_hole64_start,
	306	&f->pci_hole_64bit);
	307	}
	308	memory_region_init_alias(&f->smram_region, "smram-region",
	309	f->pci_address_space, 0xa0000, 0x20000);
	310	f->smram_enabled = true;
8a14daa5	311
bf09551a SS	312	/* Xen supports additional interrupt routes from the PCI devices to
	313	* the IOAPIC: the four pins of each PCI device on the bus are also
	314	* connected to the IOAPIC directly.
	315	* These additional routes can be discovered through ACPI. */
	316	if (xen_enabled()) {
	317	piix3 = DO_UPCAST(PIIX3State, dev,
	318	pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
	319	pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
	320	piix3, XEN_PIIX_NUM_PIRQS);
	321	} else {
	322	piix3 = DO_UPCAST(PIIX3State, dev,
	323	pci_create_simple_multifunction(b, -1, true, "PIIX3"));
	324	pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
	325	PIIX_NUM_PIRQS);
	326	}
7cd9eee0	327	piix3->pic = pic;
41445300	328
7cd9eee0 GH	329	(*pi440fx_state)->piix3 = piix3;
	330
	331	*piix3_devfn = piix3->dev.devfn;
85a750ca	332
ec5f92ce BW	333	ram_size = ram_size / 8 / 1024 / 1024;
	334	if (ram_size > 255)
	335	ram_size = 255;
	336	(*pi440fx_state)->dev.config[0x57]=ram_size;
	337
ae0a5466 AK	338	i440fx_update_memory_mappings(f);
ae0a5466 AK	339
502a5395 PB	340	return b;
	341	}
	342
41445300	343	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix3_devfn,
aee97b84 AK	344	qemu_irq *pic,
	345	MemoryRegion *address_space_mem,
	346	MemoryRegion *address_space_io,
ae0a5466 AK	347	ram_addr_t ram_size,
	348	target_phys_addr_t pci_hole_start,
	349	target_phys_addr_t pci_hole_size,
	350	target_phys_addr_t pci_hole64_start,
	351	target_phys_addr_t pci_hole64_size,
	352	MemoryRegion pci_memory, MemoryRegion ram_memory)
	353
41445300 AP	354	{
	355	PCIBus *b;
	356
1e39101c	357	b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
ae0a5466 AK	358	address_space_mem, address_space_io, ram_size,
	359	pci_hole_start, pci_hole_size,
	360	pci_hole64_size, pci_hole64_size,
	361	pci_memory, ram_memory);
41445300 AP	362	return b;
	363	}
	364
502a5395	365	/* PIIX3 PCI to ISA bridge */
ab431c28 IY	366	static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
	367	{
	368	qemu_set_irq(piix3->pic[pic_irq],
	369	!!(piix3->pic_levels &
09de0f46	370	(((1ULL << PIIX_NUM_PIRQS) - 1) <<
ab431c28 IY	371	(pic_irq * PIIX_NUM_PIRQS))));
ab431c28 IY	372	}
502a5395	373
afe3ef1d	374	static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
ab431c28 IY	375	{
	376	int pic_irq;
	377	uint64_t mask;
	378
	379	pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
	380	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	381	return;
	382	}
	383
	384	mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
	385	piix3->pic_levels &= ~mask;
	386	piix3->pic_levels \|= mask * !!level;
	387
afe3ef1d	388	piix3_set_irq_pic(piix3, pic_irq);
ab431c28 IY	389	}
	390
	391	static void piix3_set_irq(void *opaque, int pirq, int level)
502a5395	392	{
7cd9eee0	393	PIIX3State *piix3 = opaque;
afe3ef1d	394	piix3_set_irq_level(piix3, pirq, level);
ab431c28	395	}
502a5395	396
ab431c28 IY	397	/* irq routing is changed. so rebuild bitmap */
	398	static void piix3_update_irq_levels(PIIX3State *piix3)
	399	{
	400	int pirq;
	401
	402	piix3->pic_levels = 0;
	403	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
	404	piix3_set_irq_level(piix3, pirq,
afe3ef1d	405	pci_bus_get_irq_level(piix3->dev.bus, pirq));
ab431c28 IY	406	}
	407	}
	408
	409	static void piix3_write_config(PCIDevice *dev,
	410	uint32_t address, uint32_t val, int len)
	411	{
	412	pci_default_write_config(dev, address, val, len);
	413	if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
	414	PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
	415	int pic_irq;
	416	piix3_update_irq_levels(piix3);
	417	for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
	418	piix3_set_irq_pic(piix3, pic_irq);
d2b59317	419	}
502a5395 PB	420	}
	421	}
	422
bf09551a SS	423	static void piix3_write_config_xen(PCIDevice *dev,
	424	uint32_t address, uint32_t val, int len)
	425	{
	426	xen_piix_pci_write_config_client(address, val, len);
	427	piix3_write_config(dev, address, val, len);
	428	}
	429
15a1956a	430	static void piix3_reset(void *opaque)
502a5395	431	{
fd37d881 JQ	432	PIIX3State *d = opaque;
fd37d881 JQ	433	uint8_t *pci_conf = d->dev.config;
502a5395 PB	434
	435	pci_conf[0x04] = 0x07; // master, memory and I/O
	436	pci_conf[0x05] = 0x00;
	437	pci_conf[0x06] = 0x00;
	438	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	439	pci_conf[0x4c] = 0x4d;
	440	pci_conf[0x4e] = 0x03;
	441	pci_conf[0x4f] = 0x00;
	442	pci_conf[0x60] = 0x80;
477afee3 AJ	443	pci_conf[0x61] = 0x80;
	444	pci_conf[0x62] = 0x80;
	445	pci_conf[0x63] = 0x80;
502a5395 PB	446	pci_conf[0x69] = 0x02;
	447	pci_conf[0x70] = 0x80;
	448	pci_conf[0x76] = 0x0c;
	449	pci_conf[0x77] = 0x0c;
	450	pci_conf[0x78] = 0x02;
	451	pci_conf[0x79] = 0x00;
	452	pci_conf[0x80] = 0x00;
	453	pci_conf[0x82] = 0x00;
	454	pci_conf[0xa0] = 0x08;
502a5395 PB	455	pci_conf[0xa2] = 0x00;
	456	pci_conf[0xa3] = 0x00;
	457	pci_conf[0xa4] = 0x00;
	458	pci_conf[0xa5] = 0x00;
	459	pci_conf[0xa6] = 0x00;
	460	pci_conf[0xa7] = 0x00;
	461	pci_conf[0xa8] = 0x0f;
	462	pci_conf[0xaa] = 0x00;
	463	pci_conf[0xab] = 0x00;
	464	pci_conf[0xac] = 0x00;
	465	pci_conf[0xae] = 0x00;
ab431c28 IY	466
	467	d->pic_levels = 0;
	468	}
	469
	470	static int piix3_post_load(void *opaque, int version_id)
	471	{
	472	PIIX3State *piix3 = opaque;
	473	piix3_update_irq_levels(piix3);
	474	return 0;
e735b55a	475	}
15a1956a	476
e735b55a IY	477	static void piix3_pre_save(void *opaque)
	478	{
	479	int i;
	480	PIIX3State *piix3 = opaque;
	481
	482	for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
	483	piix3->pci_irq_levels_vmstate[i] =
	484	pci_bus_get_irq_level(piix3->dev.bus, i);
	485	}
502a5395 PB	486	}
502a5395 PB	487
d1f171bd JQ	488	static const VMStateDescription vmstate_piix3 = {
	489	.name = "PIIX3",
	490	.version_id = 3,
	491	.minimum_version_id = 2,
	492	.minimum_version_id_old = 2,
ab431c28	493	.post_load = piix3_post_load,
e735b55a	494	.pre_save = piix3_pre_save,
d1f171bd JQ	495	.fields = (VMStateField []) {
d1f171bd JQ	496	VMSTATE_PCI_DEVICE(dev, PIIX3State),
e735b55a IY	497	VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
e735b55a IY	498	PIIX_NUM_PIRQS, 3),
d1f171bd	499	VMSTATE_END_OF_LIST()
da64182c	500	}
d1f171bd	501	};
1941d19c	502
fd37d881	503	static int piix3_initfn(PCIDevice *dev)
502a5395	504	{
fd37d881	505	PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395	506
c2d0d012	507	isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
a08d4367	508	qemu_register_reset(piix3_reset, d);
81a322d4	509	return 0;
502a5395	510	}
5c2b87e3	511
8a14daa5 GH	512	static PCIDeviceInfo i440fx_info[] = {
	513	{
	514	.qdev.name = "i440FX",
	515	.qdev.desc = "Host bridge",
0a3bacf3	516	.qdev.size = sizeof(PCII440FXState),
be73cfe2	517	.qdev.vmsd = &vmstate_i440fx,
8a14daa5	518	.qdev.no_user = 1,
0965f12d	519	.no_hotplug = 1,
8a14daa5 GH	520	.init = i440fx_initfn,
8a14daa5 GH	521	.config_write = i440fx_write_config,
3a9d8549 IY	522	.vendor_id = PCI_VENDOR_ID_INTEL,
	523	.device_id = PCI_DEVICE_ID_INTEL_82441,
	524	.revision = 0x02,
	525	.class_id = PCI_CLASS_BRIDGE_HOST,
8a14daa5 GH	526	},{
	527	.qdev.name = "PIIX3",
	528	.qdev.desc = "ISA bridge",
fd37d881	529	.qdev.size = sizeof(PIIX3State),
be73cfe2	530	.qdev.vmsd = &vmstate_piix3,
8a14daa5	531	.qdev.no_user = 1,
0965f12d	532	.no_hotplug = 1,
8a14daa5	533	.init = piix3_initfn,
ab431c28	534	.config_write = piix3_write_config,
3a9d8549 IY	535	.vendor_id = PCI_VENDOR_ID_INTEL,
	536	.device_id = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
	537	.class_id = PCI_CLASS_BRIDGE_ISA,
bf09551a SS	538	},{
	539	.qdev.name = "PIIX3-xen",
	540	.qdev.desc = "ISA bridge",
	541	.qdev.size = sizeof(PIIX3State),
	542	.qdev.vmsd = &vmstate_piix3,
	543	.qdev.no_user = 1,
	544	.no_hotplug = 1,
	545	.init = piix3_initfn,
	546	.config_write = piix3_write_config_xen,
ce4fd422 AP	547	.vendor_id = PCI_VENDOR_ID_INTEL,
	548	.device_id = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
	549	.class_id = PCI_CLASS_BRIDGE_ISA,
8a14daa5 GH	550	},{
	551	/* end of list */
	552	}
	553	};
	554
	555	static SysBusDeviceInfo i440fx_pcihost_info = {
	556	.init = i440fx_pcihost_initfn,
	557	.qdev.name = "i440FX-pcihost",
779206de	558	.qdev.fw_name = "pci",
8a14daa5 GH	559	.qdev.size = sizeof(I440FXState),
	560	.qdev.no_user = 1,
	561	};
	562
	563	static void i440fx_register(void)
	564	{
	565	sysbus_register_withprop(&i440fx_pcihost_info);
	566	pci_qdev_register_many(i440fx_info);
	567	}
	568	device_init(i440fx_register);