[qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "sysbus.h"

typedef uint32_t pci_addr_t;
#include "pci_host.h"

typedef PCIHostState I440FXState;

static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
{
    I440FXState *s = opaque;
    s->config_reg = val;
}

static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
{
    I440FXState *s = opaque;
    return s->config_reg;
}

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (irq_num + slot_addend) & 3;
}

static target_phys_addr_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];

static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCIDevice *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->config[0x72];
    if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

void i440fx_set_smm(PCIDevice *d, int val)
{
    val = (val != 0);
    if (smm_enabled != val) {
        smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCIDevice *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *d,
                                uint32_t address, uint32_t val, int len)
{
    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(d, address, val, len);
    if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
        i440fx_update_memory_mappings(d);
}

static void i440fx_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    int i;

    pci_device_save(d, f);
    qemu_put_8s(f, &smm_enabled);

    for (i = 0; i < 4; i++)
        qemu_put_be32(f, pci_irq_levels[i]);
}

static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    int ret, i;

    if (version_id > 2)
        return -EINVAL;
    ret = pci_device_load(d, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &smm_enabled);

    if (version_id >= 2)
        for (i = 0; i < 4; i++)
            pci_irq_levels[i] = qemu_get_be32(f);

    return 0;
}

static void i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
    register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
}

static void i440fx_initfn(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
    d->config[0x08] = 0x02; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    d->config[0x72] = 0x02; /* SMRAM */

    register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
}

PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    b = pci_register_bus(&s->busdev.qdev, "pci.0",
                         piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
    s->bus = b;
    qdev_init(dev);

    d = pci_create_simple(b, 0, "i440FX");
    *pi440fx_state = d;

    return b;
}

/* PIIX3 PCI to ISA bridge */

static PCIDevice *piix3_dev;
PCIDevice *piix4_dev;

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
    int i, pic_irq, pic_level;

    pci_irq_levels[irq_num] = level;

    /* now we change the pic irq level according to the piix irq mappings */
    /* XXX: optimize */
    pic_irq = piix3_dev->config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
        for (i = 0; i < 4; i++) {
            if (pic_irq == piix3_dev->config[0x60 + i])
                pic_level |= pci_irq_levels[i];
        }
        qemu_set_irq(pic[pic_irq], pic_level);
    }
}

static void piix3_reset(void *opaque)
{
    PCIDevice *d = opaque;
    uint8_t *pci_conf = d->config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}

static void piix4_reset(void *opaque)
{
    PCIDevice *d = opaque;
    uint8_t *pci_conf = d->config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
    pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
    pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
    pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}

static void piix_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    pci_device_save(d, f);
}

static int piix_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    if (version_id != 2)
        return -EINVAL;
    return pci_device_load(d, f);
}

static void piix3_initfn(PCIDevice *d)
{
    uint8_t *pci_conf;

    register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);

    pci_conf = d->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
    pci_conf[PCI_HEADER_TYPE] =
        PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic

    piix3_dev = d;
    piix3_reset(d);
    qemu_register_reset(piix3_reset, d);
}

static void piix4_initfn(PCIDevice *d)
{
    uint8_t *pci_conf;

    register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);

    pci_conf = d->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
    pci_conf[PCI_HEADER_TYPE] =
        PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic

    piix4_dev = d;
    piix4_reset(d);
    qemu_register_reset(piix4_reset, d);
}

int piix3_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;

    d = pci_create_simple(bus, devfn, "PIIX3");
    return d->devfn;
}

int piix4_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;

    d = pci_create_simple(bus, devfn, "PIIX4");
    return d->devfn;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCIDevice),
        .qdev.no_user = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PCIDevice),
        .qdev.no_user = 1,
        .init         = piix3_initfn,
    },{
        .qdev.name    = "PIIX4",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PCIDevice),
        .qdev.no_user = 1,
        .init         = piix4_initfn,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
8a14daa5	28	#include "sysbus.h"
87ecb68b	29
502a5395 PB	30	typedef uint32_t pci_addr_t;
	31	#include "pci_host.h"
	32
	33	typedef PCIHostState I440FXState;
	34
	35	static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
	36	{
	37	I440FXState *s = opaque;
	38	s->config_reg = val;
	39	}
	40
	41	static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
	42	{
	43	I440FXState *s = opaque;
	44	return s->config_reg;
	45	}
	46
d537cf6c	47	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
d2b59317 PB	48
	49	/* return the global irq number corresponding to a given device irq
	50	pin. We could also use the bus number to have a more precise
	51	mapping. */
	52	static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
	53	{
	54	int slot_addend;
	55	slot_addend = (pci_dev->devfn >> 3) - 1;
	56	return (irq_num + slot_addend) & 3;
	57	}
502a5395	58
00f82b8a	59	static target_phys_addr_t isa_page_descs[384 / 4];
ee0ea1d0	60	static uint8_t smm_enabled;
52fc1d83	61	static int pci_irq_levels[4];
ee0ea1d0	62
84631fd7 FB	63	static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
	64	{
	65	uint32_t addr;
	66
	67	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	68	switch(r) {
	69	case 3:
	70	/* RAM */
5fafdf24	71	cpu_register_physical_memory(start, end - start,
84631fd7 FB	72	start);
	73	break;
	74	case 1:
	75	/* ROM (XXX: not quite correct) */
5fafdf24	76	cpu_register_physical_memory(start, end - start,
84631fd7 FB	77	start \| IO_MEM_ROM);
	78	break;
	79	case 2:
	80	case 0:
	81	/* XXX: should distinguish read/write cases */
	82	for(addr = start; addr < end; addr += 4096) {
5fafdf24	83	cpu_register_physical_memory(addr, 4096,
84631fd7 FB	84	isa_page_descs[(addr - 0xa0000) >> 12]);
	85	}
	86	break;
	87	}
	88	}
ee0ea1d0 FB	89
	90	static void i440fx_update_memory_mappings(PCIDevice *d)
	91	{
	92	int i, r;
84631fd7 FB	93	uint32_t smram, addr;
	94
	95	update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
	96	for(i = 0; i < 12; i++) {
	97	r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
	98	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	99	}
84631fd7 FB	100	smram = d->config[0x72];
	101	if ((smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
	102	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	103	} else {
	104	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	105	cpu_register_physical_memory(addr, 4096,
84631fd7	106	isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	107	}
	108	}
	109	}
	110
	111	void i440fx_set_smm(PCIDevice *d, int val)
	112	{
	113	val = (val != 0);
	114	if (smm_enabled != val) {
	115	smm_enabled = val;
	116	i440fx_update_memory_mappings(d);
	117	}
	118	}
	119
	120
	121	/* XXX: suppress when better memory API. We make the assumption that
	122	no device (in particular the VGA) changes the memory mappings in
	123	the 0xa0000-0x100000 range */
	124	void i440fx_init_memory_mappings(PCIDevice *d)
	125	{
	126	int i;
	127	for(i = 0; i < 96; i++) {
	128	isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
	129	}
	130	}
	131
5fafdf24	132	static void i440fx_write_config(PCIDevice *d,
ee0ea1d0 FB	133	uint32_t address, uint32_t val, int len)
	134	{
	135	/* XXX: implement SMRAM.D_LOCK */
	136	pci_default_write_config(d, address, val, len);
84631fd7	137	if ((address >= 0x59 && address <= 0x5f) \|\| address == 0x72)
ee0ea1d0 FB	138	i440fx_update_memory_mappings(d);
	139	}
	140
	141	static void i440fx_save(QEMUFile* f, void *opaque)
	142	{
	143	PCIDevice *d = opaque;
52fc1d83 AZ	144	int i;
52fc1d83 AZ	145
ee0ea1d0 FB	146	pci_device_save(d, f);
ee0ea1d0 FB	147	qemu_put_8s(f, &smm_enabled);
52fc1d83 AZ	148
	149	for (i = 0; i < 4; i++)
	150	qemu_put_be32(f, pci_irq_levels[i]);
ee0ea1d0 FB	151	}
	152
	153	static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
	154	{
	155	PCIDevice *d = opaque;
52fc1d83	156	int ret, i;
ee0ea1d0	157
52fc1d83	158	if (version_id > 2)
ee0ea1d0 FB	159	return -EINVAL;
	160	ret = pci_device_load(d, f);
	161	if (ret < 0)
	162	return ret;
	163	i440fx_update_memory_mappings(d);
	164	qemu_get_8s(f, &smm_enabled);
52fc1d83 AZ	165
	166	if (version_id >= 2)
	167	for (i = 0; i < 4; i++)
	168	pci_irq_levels[i] = qemu_get_be32(f);
	169
ee0ea1d0 FB	170	return 0;
	171	}
	172
8a14daa5	173	static void i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	174	{
8a14daa5	175	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395 PB	176
	177	register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
	178	register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
	179
	180	register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
	181	register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
	182	register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
	183	register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
	184	register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
	185	register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
8a14daa5	186	}
502a5395	187
8a14daa5 GH	188	static void i440fx_initfn(PCIDevice *d)
8a14daa5 GH	189	{
deb54399 AL	190	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
deb54399 AL	191	pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
502a5395	192	d->config[0x08] = 0x02; // revision
173a543b	193	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
6407f373	194	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
ee0ea1d0	195
84631fd7	196	d->config[0x72] = 0x02; /* SMRAM */
ee0ea1d0	197
52fc1d83	198	register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
8a14daa5 GH	199	}
	200
	201	PCIBus i440fx_init(PCIDevice pi440fx_state, qemu_irq pic)
	202	{
	203	DeviceState *dev;
	204	PCIBus *b;
	205	PCIDevice *d;
	206	I440FXState *s;
	207
	208	dev = qdev_create(NULL, "i440FX-pcihost");
	209	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
	210	b = pci_register_bus(&s->busdev.qdev, "pci.0",
	211	piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
	212	s->bus = b;
	213	qdev_init(dev);
	214
	215	d = pci_create_simple(b, 0, "i440FX");
ee0ea1d0	216	*pi440fx_state = d;
8a14daa5	217
502a5395 PB	218	return b;
	219	}
	220
	221	/* PIIX3 PCI to ISA bridge */
	222
b1d8e52e	223	static PCIDevice *piix3_dev;
5c2b87e3	224	PCIDevice *piix4_dev;
502a5395	225
d537cf6c	226	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
502a5395	227	{
d2b59317	228	int i, pic_irq, pic_level;
502a5395	229
d2b59317	230	pci_irq_levels[irq_num] = level;
502a5395 PB	231
	232	/* now we change the pic irq level according to the piix irq mappings */
	233	/* XXX: optimize */
	234	pic_irq = piix3_dev->config[0x60 + irq_num];
	235	if (pic_irq < 16) {
d2b59317	236	/* The pic level is the logical OR of all the PCI irqs mapped
502a5395 PB	237	to it */
502a5395 PB	238	pic_level = 0;
d2b59317 PB	239	for (i = 0; i < 4; i++) {
	240	if (pic_irq == piix3_dev->config[0x60 + i])
	241	pic_level \|= pci_irq_levels[i];
	242	}
d537cf6c	243	qemu_set_irq(pic[pic_irq], pic_level);
502a5395 PB	244	}
	245	}
	246
15a1956a	247	static void piix3_reset(void *opaque)
502a5395	248	{
15a1956a	249	PCIDevice *d = opaque;
502a5395 PB	250	uint8_t *pci_conf = d->config;
	251
	252	pci_conf[0x04] = 0x07; // master, memory and I/O
	253	pci_conf[0x05] = 0x00;
	254	pci_conf[0x06] = 0x00;
	255	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	256	pci_conf[0x4c] = 0x4d;
	257	pci_conf[0x4e] = 0x03;
	258	pci_conf[0x4f] = 0x00;
	259	pci_conf[0x60] = 0x80;
477afee3 AJ	260	pci_conf[0x61] = 0x80;
	261	pci_conf[0x62] = 0x80;
	262	pci_conf[0x63] = 0x80;
502a5395 PB	263	pci_conf[0x69] = 0x02;
	264	pci_conf[0x70] = 0x80;
	265	pci_conf[0x76] = 0x0c;
	266	pci_conf[0x77] = 0x0c;
	267	pci_conf[0x78] = 0x02;
	268	pci_conf[0x79] = 0x00;
	269	pci_conf[0x80] = 0x00;
	270	pci_conf[0x82] = 0x00;
	271	pci_conf[0xa0] = 0x08;
502a5395 PB	272	pci_conf[0xa2] = 0x00;
	273	pci_conf[0xa3] = 0x00;
	274	pci_conf[0xa4] = 0x00;
	275	pci_conf[0xa5] = 0x00;
	276	pci_conf[0xa6] = 0x00;
	277	pci_conf[0xa7] = 0x00;
	278	pci_conf[0xa8] = 0x0f;
	279	pci_conf[0xaa] = 0x00;
	280	pci_conf[0xab] = 0x00;
	281	pci_conf[0xac] = 0x00;
	282	pci_conf[0xae] = 0x00;
15a1956a GN	283
15a1956a GN	284	memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
502a5395 PB	285	}
502a5395 PB	286
eae6bcbf	287	static void piix4_reset(void *opaque)
5c2b87e3	288	{
eae6bcbf	289	PCIDevice *d = opaque;
5c2b87e3 TS	290	uint8_t *pci_conf = d->config;
	291
	292	pci_conf[0x04] = 0x07; // master, memory and I/O
	293	pci_conf[0x05] = 0x00;
	294	pci_conf[0x06] = 0x00;
	295	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	296	pci_conf[0x4c] = 0x4d;
	297	pci_conf[0x4e] = 0x03;
	298	pci_conf[0x4f] = 0x00;
	299	pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
	300	pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
	301	pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
	302	pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
	303	pci_conf[0x69] = 0x02;
	304	pci_conf[0x70] = 0x80;
	305	pci_conf[0x76] = 0x0c;
	306	pci_conf[0x77] = 0x0c;
	307	pci_conf[0x78] = 0x02;
	308	pci_conf[0x79] = 0x00;
	309	pci_conf[0x80] = 0x00;
	310	pci_conf[0x82] = 0x00;
	311	pci_conf[0xa0] = 0x08;
5c2b87e3 TS	312	pci_conf[0xa2] = 0x00;
	313	pci_conf[0xa3] = 0x00;
	314	pci_conf[0xa4] = 0x00;
	315	pci_conf[0xa5] = 0x00;
	316	pci_conf[0xa6] = 0x00;
	317	pci_conf[0xa7] = 0x00;
	318	pci_conf[0xa8] = 0x0f;
	319	pci_conf[0xaa] = 0x00;
	320	pci_conf[0xab] = 0x00;
	321	pci_conf[0xac] = 0x00;
	322	pci_conf[0xae] = 0x00;
eae6bcbf BS	323
eae6bcbf BS	324	memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
5c2b87e3 TS	325	}
5c2b87e3 TS	326
1941d19c FB	327	static void piix_save(QEMUFile* f, void *opaque)
	328	{
	329	PCIDevice *d = opaque;
	330	pci_device_save(d, f);
	331	}
	332
	333	static int piix_load(QEMUFile* f, void *opaque, int version_id)
	334	{
	335	PCIDevice *d = opaque;
	336	if (version_id != 2)
	337	return -EINVAL;
	338	return pci_device_load(d, f);
	339	}
	340
8a14daa5	341	static void piix3_initfn(PCIDevice *d)
502a5395	342	{
502a5395 PB	343	uint8_t *pci_conf;
502a5395 PB	344
1941d19c	345	register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
502a5395	346
502a5395	347	pci_conf = d->config;
deb54399 AL	348	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	349	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b	350	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
6407f373 IY	351	pci_conf[PCI_HEADER_TYPE] =
6407f373 IY	352	PCI_HEADER_TYPE_NORMAL \| PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
502a5395	353
8a14daa5	354	piix3_dev = d;
502a5395	355	piix3_reset(d);
a08d4367	356	qemu_register_reset(piix3_reset, d);
502a5395	357	}
5c2b87e3	358
8a14daa5	359	static void piix4_initfn(PCIDevice *d)
5c2b87e3	360	{
5c2b87e3 TS	361	uint8_t *pci_conf;
5c2b87e3 TS	362
5c2b87e3 TS	363	register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
5c2b87e3 TS	364
5c2b87e3	365	pci_conf = d->config;
deb54399 AL	366	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	367	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
173a543b	368	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
6407f373 IY	369	pci_conf[PCI_HEADER_TYPE] =
	370	PCI_HEADER_TYPE_NORMAL \| PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
	371
8a14daa5	372	piix4_dev = d;
5c2b87e3	373	piix4_reset(d);
a08d4367	374	qemu_register_reset(piix4_reset, d);
8a14daa5 GH	375	}
	376
	377	int piix3_init(PCIBus *bus, int devfn)
	378	{
	379	PCIDevice *d;
	380
	381	d = pci_create_simple(bus, devfn, "PIIX3");
5c2b87e3 TS	382	return d->devfn;
5c2b87e3 TS	383	}
8a14daa5 GH	384
	385	int piix4_init(PCIBus *bus, int devfn)
	386	{
	387	PCIDevice *d;
	388
	389	d = pci_create_simple(bus, devfn, "PIIX4");
	390	return d->devfn;
	391	}
	392
	393	static PCIDeviceInfo i440fx_info[] = {
	394	{
	395	.qdev.name = "i440FX",
	396	.qdev.desc = "Host bridge",
	397	.qdev.size = sizeof(PCIDevice),
	398	.qdev.no_user = 1,
	399	.init = i440fx_initfn,
	400	.config_write = i440fx_write_config,
	401	},{
	402	.qdev.name = "PIIX3",
	403	.qdev.desc = "ISA bridge",
	404	.qdev.size = sizeof(PCIDevice),
	405	.qdev.no_user = 1,
	406	.init = piix3_initfn,
	407	},{
	408	.qdev.name = "PIIX4",
	409	.qdev.desc = "ISA bridge",
	410	.qdev.size = sizeof(PCIDevice),
	411	.qdev.no_user = 1,
	412	.init = piix4_initfn,
	413	},{
	414	/* end of list */
	415	}
	416	};
	417
	418	static SysBusDeviceInfo i440fx_pcihost_info = {
	419	.init = i440fx_pcihost_initfn,
	420	.qdev.name = "i440FX-pcihost",
	421	.qdev.size = sizeof(I440FXState),
	422	.qdev.no_user = 1,
	423	};
	424
	425	static void i440fx_register(void)
	426	{
	427	sysbus_register_withprop(&i440fx_pcihost_info);
	428	pci_qdev_register_many(i440fx_info);
	429	}
	430	device_init(i440fx_register);