[qemu.git] / hw / pl061.c

/*
 * Arm PrimeCell PL061 General Purpose IO with additional
 * Luminary Micro Stellaris bits.
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

//#define DEBUG_PL061 1

#ifdef DEBUG_PL061
#define DPRINTF(fmt, ...) \
do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

static const uint8_t pl061_id[12] =
  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const uint8_t pl061_id_luminary[12] =
  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };

typedef struct {
    SysBusDevice busdev;
    uint32_t locked;
    uint32_t data;
    uint32_t old_data;
    uint32_t dir;
    uint32_t isense;
    uint32_t ibe;
    uint32_t iev;
    uint32_t im;
    uint32_t istate;
    uint32_t afsel;
    uint32_t dr2r;
    uint32_t dr4r;
    uint32_t dr8r;
    uint32_t odr;
    uint32_t pur;
    uint32_t pdr;
    uint32_t slr;
    uint32_t den;
    uint32_t cr;
    uint32_t float_high;
    uint32_t amsel;
    qemu_irq irq;
    qemu_irq out[8];
    const unsigned char *id;
} pl061_state;

static const VMStateDescription vmstate_pl061 = {
    .name = "pl061",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(locked, pl061_state),
        VMSTATE_UINT32(data, pl061_state),
        VMSTATE_UINT32(old_data, pl061_state),
        VMSTATE_UINT32(dir, pl061_state),
        VMSTATE_UINT32(isense, pl061_state),
        VMSTATE_UINT32(ibe, pl061_state),
        VMSTATE_UINT32(iev, pl061_state),
        VMSTATE_UINT32(im, pl061_state),
        VMSTATE_UINT32(istate, pl061_state),
        VMSTATE_UINT32(afsel, pl061_state),
        VMSTATE_UINT32(dr2r, pl061_state),
        VMSTATE_UINT32(dr4r, pl061_state),
        VMSTATE_UINT32(dr8r, pl061_state),
        VMSTATE_UINT32(odr, pl061_state),
        VMSTATE_UINT32(pur, pl061_state),
        VMSTATE_UINT32(pdr, pl061_state),
        VMSTATE_UINT32(slr, pl061_state),
        VMSTATE_UINT32(den, pl061_state),
        VMSTATE_UINT32(cr, pl061_state),
        VMSTATE_UINT32(float_high, pl061_state),
        VMSTATE_UINT32_V(amsel, pl061_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static void pl061_update(pl061_state *s)
{
    uint8_t changed;
    uint8_t mask;
    uint8_t out;
    int i;

    /* Outputs float high.  */
    /* FIXME: This is board dependent.  */
    out = (s->data & s->dir) | ~s->dir;
    changed = s->old_data ^ out;
    if (!changed)
        return;

    s->old_data = out;
    for (i = 0; i < 8; i++) {
        mask = 1 << i;
        if ((changed & mask) && s->out) {
            DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
            qemu_set_irq(s->out[i], (out & mask) != 0);
        }
    }

    /* FIXME: Implement input interrupts.  */
}

static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
{
    pl061_state *s = (pl061_state *)opaque;

    if (offset >= 0xfd0 && offset < 0x1000) {
        return s->id[(offset - 0xfd0) >> 2];
    }
    if (offset < 0x400) {
        return s->data & (offset >> 2);
    }
    switch (offset) {
    case 0x400: /* Direction */
        return s->dir;
    case 0x404: /* Interrupt sense */
        return s->isense;
    case 0x408: /* Interrupt both edges */
        return s->ibe;
    case 0x40c: /* Interrupt event */
        return s->iev;
    case 0x410: /* Interrupt mask */
        return s->im;
    case 0x414: /* Raw interrupt status */
        return s->istate;
    case 0x418: /* Masked interrupt status */
        return s->istate | s->im;
    case 0x420: /* Alternate function select */
        return s->afsel;
    case 0x500: /* 2mA drive */
        return s->dr2r;
    case 0x504: /* 4mA drive */
        return s->dr4r;
    case 0x508: /* 8mA drive */
        return s->dr8r;
    case 0x50c: /* Open drain */
        return s->odr;
    case 0x510: /* Pull-up */
        return s->pur;
    case 0x514: /* Pull-down */
        return s->pdr;
    case 0x518: /* Slew rate control */
        return s->slr;
    case 0x51c: /* Digital enable */
        return s->den;
    case 0x520: /* Lock */
        return s->locked;
    case 0x524: /* Commit */
        return s->cr;
    case 0x528: /* Analog mode select */
        return s->amsel;
    default:
        hw_error("pl061_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl061_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    pl061_state *s = (pl061_state *)opaque;
    uint8_t mask;

    if (offset < 0x400) {
        mask = (offset >> 2) & s->dir;
        s->data = (s->data & ~mask) | (value & mask);
        pl061_update(s);
        return;
    }
    switch (offset) {
    case 0x400: /* Direction */
        s->dir = value & 0xff;
        break;
    case 0x404: /* Interrupt sense */
        s->isense = value & 0xff;
        break;
    case 0x408: /* Interrupt both edges */
        s->ibe = value & 0xff;
        break;
    case 0x40c: /* Interrupt event */
        s->iev = value & 0xff;
        break;
    case 0x410: /* Interrupt mask */
        s->im = value & 0xff;
        break;
    case 0x41c: /* Interrupt clear */
        s->istate &= ~value;
        break;
    case 0x420: /* Alternate function select */
        mask = s->cr;
        s->afsel = (s->afsel & ~mask) | (value & mask);
        break;
    case 0x500: /* 2mA drive */
        s->dr2r = value & 0xff;
        break;
    case 0x504: /* 4mA drive */
        s->dr4r = value & 0xff;
        break;
    case 0x508: /* 8mA drive */
        s->dr8r = value & 0xff;
        break;
    case 0x50c: /* Open drain */
        s->odr = value & 0xff;
        break;
    case 0x510: /* Pull-up */
        s->pur = value & 0xff;
        break;
    case 0x514: /* Pull-down */
        s->pdr = value & 0xff;
        break;
    case 0x518: /* Slew rate control */
        s->slr = value & 0xff;
        break;
    case 0x51c: /* Digital enable */
        s->den = value & 0xff;
        break;
    case 0x520: /* Lock */
        s->locked = (value != 0xacce551);
        break;
    case 0x524: /* Commit */
        if (!s->locked)
            s->cr = value & 0xff;
        break;
    case 0x528:
        s->amsel = value & 0xff;
        break;
    default:
        hw_error("pl061_write: Bad offset %x\n", (int)offset);
    }
    pl061_update(s);
}

static void pl061_reset(pl061_state *s)
{
  s->locked = 1;
  s->cr = 0xff;
}

static void pl061_set_irq(void * opaque, int irq, int level)
{
    pl061_state *s = (pl061_state *)opaque;
    uint8_t mask;

    mask = 1 << irq;
    if ((s->dir & mask) == 0) {
        s->data &= ~mask;
        if (level)
            s->data |= mask;
        pl061_update(s);
    }
}

static CPUReadMemoryFunc * const pl061_readfn[] = {
   pl061_read,
   pl061_read,
   pl061_read
};

static CPUWriteMemoryFunc * const pl061_writefn[] = {
   pl061_write,
   pl061_write,
   pl061_write
};

static int pl061_init(SysBusDevice *dev, const unsigned char *id)
{
    int iomemtype;
    pl061_state *s = FROM_SYSBUS(pl061_state, dev);
    s->id = id;
    iomemtype = cpu_register_io_memory(pl061_readfn,
                                       pl061_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq);
    qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
    qdev_init_gpio_out(&dev->qdev, s->out, 8);
    pl061_reset(s);
    return 0;
}

static int pl061_init_luminary(SysBusDevice *dev)
{
    return pl061_init(dev, pl061_id_luminary);
}

static int pl061_init_arm(SysBusDevice *dev)
{
    return pl061_init(dev, pl061_id);
}

static SysBusDeviceInfo pl061_info = {
    .init = pl061_init_arm,
    .qdev.name = "pl061",
    .qdev.size = sizeof(pl061_state),
    .qdev.vmsd = &vmstate_pl061,
};

static SysBusDeviceInfo pl061_luminary_info = {
    .init = pl061_init_luminary,
    .qdev.name = "pl061_luminary",
    .qdev.size = sizeof(pl061_state),
    .qdev.vmsd = &vmstate_pl061,
};

static void pl061_register_devices(void)
{
    sysbus_register_withprop(&pl061_info);
    sysbus_register_withprop(&pl061_luminary_info);
}

device_init(pl061_register_devices)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* Arm PrimeCell PL061 General Purpose IO with additional
	3	* Luminary Micro Stellaris bits.
	4	*
	5	* Copyright (c) 2007 CodeSourcery.
	6	* Written by Paul Brook
	7	*
8e31bf38	8	* This code is licensed under the GPL.
9ee6e8bb PB	9	*/
9ee6e8bb PB	10
40905a6a	11	#include "sysbus.h"
9ee6e8bb PB	12
	13	//#define DEBUG_PL061 1
	14
	15	#ifdef DEBUG_PL061
001faf32 BS	16	#define DPRINTF(fmt, ...) \
	17	do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
	18	#define BADF(fmt, ...) \
	19	do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
9ee6e8bb	20	#else
001faf32 BS	21	#define DPRINTF(fmt, ...) do {} while(0)
	22	#define BADF(fmt, ...) \
	23	do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	24	#endif
	25
	26	static const uint8_t pl061_id[12] =
7063f49f PM	27	{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
7063f49f PM	28	static const uint8_t pl061_id_luminary[12] =
9ee6e8bb PB	29	{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
	30
	31	typedef struct {
40905a6a	32	SysBusDevice busdev;
a35faa94 PM	33	uint32_t locked;
	34	uint32_t data;
	35	uint32_t old_data;
	36	uint32_t dir;
	37	uint32_t isense;
	38	uint32_t ibe;
	39	uint32_t iev;
	40	uint32_t im;
	41	uint32_t istate;
	42	uint32_t afsel;
	43	uint32_t dr2r;
	44	uint32_t dr4r;
	45	uint32_t dr8r;
	46	uint32_t odr;
	47	uint32_t pur;
	48	uint32_t pdr;
	49	uint32_t slr;
	50	uint32_t den;
	51	uint32_t cr;
	52	uint32_t float_high;
b3aaff11	53	uint32_t amsel;
9ee6e8bb PB	54	qemu_irq irq;
9ee6e8bb PB	55	qemu_irq out[8];
7063f49f	56	const unsigned char *id;
9ee6e8bb PB	57	} pl061_state;
9ee6e8bb PB	58
a35faa94 PM	59	static const VMStateDescription vmstate_pl061 = {
a35faa94 PM	60	.name = "pl061",
b3aaff11	61	.version_id = 2,
a35faa94 PM	62	.minimum_version_id = 1,
	63	.fields = (VMStateField[]) {
	64	VMSTATE_UINT32(locked, pl061_state),
	65	VMSTATE_UINT32(data, pl061_state),
	66	VMSTATE_UINT32(old_data, pl061_state),
	67	VMSTATE_UINT32(dir, pl061_state),
	68	VMSTATE_UINT32(isense, pl061_state),
	69	VMSTATE_UINT32(ibe, pl061_state),
	70	VMSTATE_UINT32(iev, pl061_state),
	71	VMSTATE_UINT32(im, pl061_state),
	72	VMSTATE_UINT32(istate, pl061_state),
	73	VMSTATE_UINT32(afsel, pl061_state),
	74	VMSTATE_UINT32(dr2r, pl061_state),
	75	VMSTATE_UINT32(dr4r, pl061_state),
	76	VMSTATE_UINT32(dr8r, pl061_state),
	77	VMSTATE_UINT32(odr, pl061_state),
	78	VMSTATE_UINT32(pur, pl061_state),
	79	VMSTATE_UINT32(pdr, pl061_state),
	80	VMSTATE_UINT32(slr, pl061_state),
	81	VMSTATE_UINT32(den, pl061_state),
	82	VMSTATE_UINT32(cr, pl061_state),
	83	VMSTATE_UINT32(float_high, pl061_state),
b3aaff11	84	VMSTATE_UINT32_V(amsel, pl061_state, 2),
a35faa94 PM	85	VMSTATE_END_OF_LIST()
	86	}
	87	};
	88
9ee6e8bb PB	89	static void pl061_update(pl061_state *s)
	90	{
	91	uint8_t changed;
	92	uint8_t mask;
775616c3	93	uint8_t out;
9ee6e8bb PB	94	int i;
9ee6e8bb PB	95
775616c3 PB	96	/* Outputs float high. */
	97	/* FIXME: This is board dependent. */
	98	out = (s->data & s->dir) \| ~s->dir;
	99	changed = s->old_data ^ out;
9ee6e8bb PB	100	if (!changed)
	101	return;
	102
775616c3	103	s->old_data = out;
9ee6e8bb PB	104	for (i = 0; i < 8; i++) {
9ee6e8bb PB	105	mask = 1 << i;
775616c3 PB	106	if ((changed & mask) && s->out) {
	107	DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
	108	qemu_set_irq(s->out[i], (out & mask) != 0);
9ee6e8bb PB	109	}
	110	}
	111
	112	/* FIXME: Implement input interrupts. */
	113	}
	114
c227f099	115	static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
9ee6e8bb PB	116	{
	117	pl061_state s = (pl061_state )opaque;
	118
9ee6e8bb	119	if (offset >= 0xfd0 && offset < 0x1000) {
7063f49f	120	return s->id[(offset - 0xfd0) >> 2];
9ee6e8bb PB	121	}
	122	if (offset < 0x400) {
	123	return s->data & (offset >> 2);
	124	}
	125	switch (offset) {
	126	case 0x400: /* Direction */
	127	return s->dir;
	128	case 0x404: /* Interrupt sense */
	129	return s->isense;
	130	case 0x408: /* Interrupt both edges */
	131	return s->ibe;
ff2712ba	132	case 0x40c: /* Interrupt event */
9ee6e8bb PB	133	return s->iev;
	134	case 0x410: /* Interrupt mask */
	135	return s->im;
	136	case 0x414: /* Raw interrupt status */
	137	return s->istate;
	138	case 0x418: /* Masked interrupt status */
	139	return s->istate \| s->im;
	140	case 0x420: /* Alternate function select */
	141	return s->afsel;
	142	case 0x500: /* 2mA drive */
	143	return s->dr2r;
	144	case 0x504: /* 4mA drive */
	145	return s->dr4r;
	146	case 0x508: /* 8mA drive */
	147	return s->dr8r;
	148	case 0x50c: /* Open drain */
	149	return s->odr;
	150	case 0x510: /* Pull-up */
	151	return s->pur;
	152	case 0x514: /* Pull-down */
	153	return s->pdr;
	154	case 0x518: /* Slew rate control */
	155	return s->slr;
	156	case 0x51c: /* Digital enable */
	157	return s->den;
	158	case 0x520: /* Lock */
	159	return s->locked;
	160	case 0x524: /* Commit */
	161	return s->cr;
b3aaff11 PM	162	case 0x528: /* Analog mode select */
b3aaff11 PM	163	return s->amsel;
9ee6e8bb	164	default:
2ac71179	165	hw_error("pl061_read: Bad offset %x\n", (int)offset);
9ee6e8bb PB	166	return 0;
	167	}
	168	}
	169
c227f099	170	static void pl061_write(void *opaque, target_phys_addr_t offset,
9ee6e8bb PB	171	uint32_t value)
	172	{
	173	pl061_state s = (pl061_state )opaque;
	174	uint8_t mask;
	175
9ee6e8bb PB	176	if (offset < 0x400) {
	177	mask = (offset >> 2) & s->dir;
	178	s->data = (s->data & ~mask) \| (value & mask);
	179	pl061_update(s);
	180	return;
	181	}
	182	switch (offset) {
	183	case 0x400: /* Direction */
a35faa94	184	s->dir = value & 0xff;
9ee6e8bb PB	185	break;
9ee6e8bb PB	186	case 0x404: /* Interrupt sense */
a35faa94	187	s->isense = value & 0xff;
9ee6e8bb PB	188	break;
9ee6e8bb PB	189	case 0x408: /* Interrupt both edges */
a35faa94	190	s->ibe = value & 0xff;
9ee6e8bb	191	break;
ff2712ba	192	case 0x40c: /* Interrupt event */
a35faa94	193	s->iev = value & 0xff;
9ee6e8bb PB	194	break;
9ee6e8bb PB	195	case 0x410: /* Interrupt mask */
a35faa94	196	s->im = value & 0xff;
9ee6e8bb PB	197	break;
	198	case 0x41c: /* Interrupt clear */
	199	s->istate &= ~value;
	200	break;
	201	case 0x420: /* Alternate function select */
	202	mask = s->cr;
	203	s->afsel = (s->afsel & ~mask) \| (value & mask);
	204	break;
	205	case 0x500: /* 2mA drive */
a35faa94	206	s->dr2r = value & 0xff;
9ee6e8bb PB	207	break;
9ee6e8bb PB	208	case 0x504: /* 4mA drive */
a35faa94	209	s->dr4r = value & 0xff;
9ee6e8bb PB	210	break;
9ee6e8bb PB	211	case 0x508: /* 8mA drive */
a35faa94	212	s->dr8r = value & 0xff;
9ee6e8bb PB	213	break;
9ee6e8bb PB	214	case 0x50c: /* Open drain */
a35faa94	215	s->odr = value & 0xff;
9ee6e8bb PB	216	break;
9ee6e8bb PB	217	case 0x510: /* Pull-up */
a35faa94	218	s->pur = value & 0xff;
9ee6e8bb PB	219	break;
9ee6e8bb PB	220	case 0x514: /* Pull-down */
a35faa94	221	s->pdr = value & 0xff;
9ee6e8bb PB	222	break;
9ee6e8bb PB	223	case 0x518: /* Slew rate control */
a35faa94	224	s->slr = value & 0xff;
9ee6e8bb PB	225	break;
9ee6e8bb PB	226	case 0x51c: /* Digital enable */
a35faa94	227	s->den = value & 0xff;
9ee6e8bb PB	228	break;
	229	case 0x520: /* Lock */
	230	s->locked = (value != 0xacce551);
	231	break;
	232	case 0x524: /* Commit */
	233	if (!s->locked)
a35faa94	234	s->cr = value & 0xff;
9ee6e8bb	235	break;
b3aaff11 PM	236	case 0x528:
	237	s->amsel = value & 0xff;
	238	break;
9ee6e8bb	239	default:
2ac71179	240	hw_error("pl061_write: Bad offset %x\n", (int)offset);
9ee6e8bb PB	241	}
	242	pl061_update(s);
	243	}
	244
	245	static void pl061_reset(pl061_state *s)
	246	{
	247	s->locked = 1;
	248	s->cr = 0xff;
	249	}
	250
9596ebb7	251	static void pl061_set_irq(void * opaque, int irq, int level)
9ee6e8bb PB	252	{
	253	pl061_state s = (pl061_state )opaque;
	254	uint8_t mask;
	255
	256	mask = 1 << irq;
	257	if ((s->dir & mask) == 0) {
	258	s->data &= ~mask;
	259	if (level)
	260	s->data \|= mask;
	261	pl061_update(s);
	262	}
	263	}
	264
d60efc6b	265	static CPUReadMemoryFunc * const pl061_readfn[] = {
9ee6e8bb PB	266	pl061_read,
	267	pl061_read,
	268	pl061_read
	269	};
	270
d60efc6b	271	static CPUWriteMemoryFunc * const pl061_writefn[] = {
9ee6e8bb PB	272	pl061_write,
	273	pl061_write,
	274	pl061_write
	275	};
	276
7063f49f	277	static int pl061_init(SysBusDevice dev, const unsigned char id)
9ee6e8bb PB	278	{
9ee6e8bb PB	279	int iomemtype;
40905a6a	280	pl061_state *s = FROM_SYSBUS(pl061_state, dev);
7063f49f	281	s->id = id;
1eed09cb	282	iomemtype = cpu_register_io_memory(pl061_readfn,
2507c12a AG	283	pl061_writefn, s,
2507c12a AG	284	DEVICE_NATIVE_ENDIAN);
40905a6a PB	285	sysbus_init_mmio(dev, 0x1000, iomemtype);
	286	sysbus_init_irq(dev, &s->irq);
	287	qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
	288	qdev_init_gpio_out(&dev->qdev, s->out, 8);
9ee6e8bb	289	pl061_reset(s);
81a322d4	290	return 0;
9ee6e8bb	291	}
40905a6a	292
7063f49f PM	293	static int pl061_init_luminary(SysBusDevice *dev)
	294	{
	295	return pl061_init(dev, pl061_id_luminary);
	296	}
	297
	298	static int pl061_init_arm(SysBusDevice *dev)
	299	{
	300	return pl061_init(dev, pl061_id);
	301	}
	302
a35faa94 PM	303	static SysBusDeviceInfo pl061_info = {
	304	.init = pl061_init_arm,
	305	.qdev.name = "pl061",
	306	.qdev.size = sizeof(pl061_state),
	307	.qdev.vmsd = &vmstate_pl061,
	308	};
	309
	310	static SysBusDeviceInfo pl061_luminary_info = {
	311	.init = pl061_init_luminary,
	312	.qdev.name = "pl061_luminary",
	313	.qdev.size = sizeof(pl061_state),
	314	.qdev.vmsd = &vmstate_pl061,
	315	};
	316
40905a6a PB	317	static void pl061_register_devices(void)
40905a6a PB	318	{
a35faa94 PM	319	sysbus_register_withprop(&pl061_info);
a35faa94 PM	320	sysbus_register_withprop(&pl061_luminary_info);
40905a6a PB	321	}
	322
	323	device_init(pl061_register_devices)