[qemu.git] / hw / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

typedef struct {
    SysBusDevice busdev;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} pl080_state;

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, pl080_state),
        VMSTATE_UINT8(tc_mask, pl080_state),
        VMSTATE_UINT8(err_int, pl080_state),
        VMSTATE_UINT8(err_mask, pl080_state),
        VMSTATE_UINT32(conf, pl080_state),
        VMSTATE_UINT32(sync, pl080_state),
        VMSTATE_UINT32(req_single, pl080_state),
        VMSTATE_UINT32(req_burst, pl080_state),
        VMSTATE_UINT8(tc_int, pl080_state),
        VMSTATE_UINT8(tc_int, pl080_state),
        VMSTATE_UINT8(tc_int, pl080_state),
        VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, pl080_state),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(pl080_state *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(pl080_state *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = ldl_le_phys(ch->lli);
                    ch->dest = ldl_le_phys(ch->lli + 4);
                    ch->ctrl = ldl_le_phys(ch->lli + 12);
                    ch->lli = ldl_le_phys(ch->lli + 8);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
{
    pl080_state *s = (pl080_state *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        hw_error("pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    pl080_state *s = (pl080_state *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        hw_error("pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            hw_error("pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        hw_error("pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static CPUReadMemoryFunc * const pl080_readfn[] = {
   pl080_read,
   pl080_read,
   pl080_read
};

static CPUWriteMemoryFunc * const pl080_writefn[] = {
   pl080_write,
   pl080_write,
   pl080_write
};

static int pl08x_init(SysBusDevice *dev, int nchannels)
{
    int iomemtype;
    pl080_state *s = FROM_SYSBUS(pl080_state, dev);

    iomemtype = cpu_register_io_memory(pl080_readfn,
                                       pl080_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq);
    s->nchannels = nchannels;
    return 0;
}

static int pl080_init(SysBusDevice *dev)
{
    return pl08x_init(dev, 8);
}

static int pl081_init(SysBusDevice *dev)
{
    return pl08x_init(dev, 2);
}

static SysBusDeviceInfo pl080_info = {
    .init = pl080_init,
    .qdev.name = "pl080",
    .qdev.size = sizeof(pl080_state),
    .qdev.vmsd = &vmstate_pl080,
    .qdev.no_user = 1,
};

static SysBusDeviceInfo pl081_info = {
    .init = pl081_init,
    .qdev.name = "pl081",
    .qdev.size = sizeof(pl080_state),
    .qdev.vmsd = &vmstate_pl080,
    .qdev.no_user = 1,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_devices(void)
{
    sysbus_register_withprop(&pl080_info);
    sysbus_register_withprop(&pl081_info);
}

device_init(pl080_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
b4496b13	10	#include "sysbus.h"
cdbdb648	11
e69954b9	12	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	13	#define PL080_CONF_E 0x1
	14	#define PL080_CONF_M1 0x2
	15	#define PL080_CONF_M2 0x4
	16
	17	#define PL080_CCONF_H 0x40000
	18	#define PL080_CCONF_A 0x20000
	19	#define PL080_CCONF_L 0x10000
	20	#define PL080_CCONF_ITC 0x08000
	21	#define PL080_CCONF_IE 0x04000
	22	#define PL080_CCONF_E 0x00001
	23
	24	#define PL080_CCTRL_I 0x80000000
	25	#define PL080_CCTRL_DI 0x08000000
	26	#define PL080_CCTRL_SI 0x04000000
	27	#define PL080_CCTRL_D 0x02000000
	28	#define PL080_CCTRL_S 0x01000000
	29
	30	typedef struct {
	31	uint32_t src;
	32	uint32_t dest;
	33	uint32_t lli;
	34	uint32_t ctrl;
	35	uint32_t conf;
	36	} pl080_channel;
	37
	38	typedef struct {
b4496b13	39	SysBusDevice busdev;
cdbdb648 PB	40	uint8_t tc_int;
	41	uint8_t tc_mask;
	42	uint8_t err_int;
	43	uint8_t err_mask;
	44	uint32_t conf;
	45	uint32_t sync;
	46	uint32_t req_single;
	47	uint32_t req_burst;
e69954b9 PB	48	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	49	int nchannels;
cdbdb648 PB	50	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	51	int running;
d537cf6c	52	qemu_irq irq;
cdbdb648 PB	53	} pl080_state;
cdbdb648 PB	54
ff175853 PM	55	static const VMStateDescription vmstate_pl080_channel = {
	56	.name = "pl080_channel",
	57	.version_id = 1,
	58	.minimum_version_id = 1,
	59	.fields = (VMStateField[]) {
	60	VMSTATE_UINT32(src, pl080_channel),
	61	VMSTATE_UINT32(dest, pl080_channel),
	62	VMSTATE_UINT32(lli, pl080_channel),
	63	VMSTATE_UINT32(ctrl, pl080_channel),
	64	VMSTATE_UINT32(conf, pl080_channel),
	65	VMSTATE_END_OF_LIST()
	66	}
	67	};
	68
	69	static const VMStateDescription vmstate_pl080 = {
	70	.name = "pl080",
	71	.version_id = 1,
	72	.minimum_version_id = 1,
	73	.fields = (VMStateField[]) {
	74	VMSTATE_UINT8(tc_int, pl080_state),
	75	VMSTATE_UINT8(tc_mask, pl080_state),
	76	VMSTATE_UINT8(err_int, pl080_state),
	77	VMSTATE_UINT8(err_mask, pl080_state),
	78	VMSTATE_UINT32(conf, pl080_state),
	79	VMSTATE_UINT32(sync, pl080_state),
	80	VMSTATE_UINT32(req_single, pl080_state),
	81	VMSTATE_UINT32(req_burst, pl080_state),
	82	VMSTATE_UINT8(tc_int, pl080_state),
	83	VMSTATE_UINT8(tc_int, pl080_state),
	84	VMSTATE_UINT8(tc_int, pl080_state),
	85	VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS,
	86	1, vmstate_pl080_channel, pl080_channel),
	87	VMSTATE_INT32(running, pl080_state),
	88	VMSTATE_END_OF_LIST()
	89	}
	90	};
	91
cdbdb648 PB	92	static const unsigned char pl080_id[] =
	93	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	94
e69954b9 PB	95	static const unsigned char pl081_id[] =
	96	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	97
cdbdb648 PB	98	static void pl080_update(pl080_state *s)
	99	{
	100	if ((s->tc_int & s->tc_mask)
	101	\|\| (s->err_int & s->err_mask))
d537cf6c	102	qemu_irq_raise(s->irq);
cdbdb648	103	else
d537cf6c	104	qemu_irq_lower(s->irq);
cdbdb648 PB	105	}
	106
	107	static void pl080_run(pl080_state *s)
	108	{
	109	int c;
	110	int flow;
	111	pl080_channel *ch;
	112	int swidth;
	113	int dwidth;
	114	int xsize;
	115	int n;
	116	int src_id;
	117	int dest_id;
	118	int size;
b55266b5	119	uint8_t buff[4];
cdbdb648 PB	120	uint32_t req;
	121
	122	s->tc_mask = 0;
e69954b9	123	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	124	if (s->chan[c].conf & PL080_CCONF_ITC)
	125	s->tc_mask \|= 1 << c;
	126	if (s->chan[c].conf & PL080_CCONF_IE)
	127	s->err_mask \|= 1 << c;
	128	}
	129
	130	if ((s->conf & PL080_CONF_E) == 0)
	131	return;
	132
2ac71179	133	hw_error("DMA active\n");
cdbdb648 PB	134	/* If we are already in the middle of a DMA operation then indicate that
	135	there may be new DMA requests and return immediately. */
	136	if (s->running) {
	137	s->running++;
	138	return;
	139	}
	140	s->running = 1;
	141	while (s->running) {
e69954b9	142	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	143	ch = &s->chan[c];
	144	again:
	145	/* Test if thiws channel has any pending DMA requests. */
	146	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	147	!= PL080_CCONF_E)
	148	continue;
	149	flow = (ch->conf >> 11) & 7;
	150	if (flow >= 4) {
2ac71179	151	hw_error(
cdbdb648 PB	152	"pl080_run: Peripheral flow control not implemented\n");
	153	}
	154	src_id = (ch->conf >> 1) & 0x1f;
	155	dest_id = (ch->conf >> 6) & 0x1f;
	156	size = ch->ctrl & 0xfff;
	157	req = s->req_single \| s->req_burst;
	158	switch (flow) {
	159	case 0:
	160	break;
	161	case 1:
	162	if ((req & (1u << dest_id)) == 0)
	163	size = 0;
	164	break;
	165	case 2:
	166	if ((req & (1u << src_id)) == 0)
	167	size = 0;
	168	break;
	169	case 3:
	170	if ((req & (1u << src_id)) == 0
	171	\|\| (req & (1u << dest_id)) == 0)
	172	size = 0;
	173	break;
	174	}
	175	if (!size)
	176	continue;
	177
	178	/* Transfer one element. */
	179	/* ??? Should transfer multiple elements for a burst request. */
	180	/* ??? Unclear what the proper behavior is when source and
	181	destination widths are different. */
	182	swidth = 1 << ((ch->ctrl >> 18) & 7);
	183	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	184	for (n = 0; n < dwidth; n+= swidth) {
	185	cpu_physical_memory_read(ch->src, buff + n, swidth);
	186	if (ch->ctrl & PL080_CCTRL_SI)
	187	ch->src += swidth;
	188	}
	189	xsize = (dwidth < swidth) ? swidth : dwidth;
	190	/* ??? This may pad the value incorrectly for dwidth < 32. */
	191	for (n = 0; n < xsize; n += dwidth) {
	192	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	193	if (ch->ctrl & PL080_CCTRL_DI)
	194	ch->dest += swidth;
	195	}
	196
	197	size--;
	198	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	199	if (size == 0) {
	200	/* Transfer complete. */
	201	if (ch->lli) {
75b0646f AG	202	ch->src = ldl_le_phys(ch->lli);
	203	ch->dest = ldl_le_phys(ch->lli + 4);
	204	ch->ctrl = ldl_le_phys(ch->lli + 12);
	205	ch->lli = ldl_le_phys(ch->lli + 8);
cdbdb648 PB	206	} else {
	207	ch->conf &= ~PL080_CCONF_E;
	208	}
	209	if (ch->ctrl & PL080_CCTRL_I) {
	210	s->tc_int \|= 1 << c;
	211	}
	212	}
	213	goto again;
	214	}
	215	if (--s->running)
	216	s->running = 1;
	217	}
	218	}
	219
c227f099	220	static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	221	{
	222	pl080_state s = (pl080_state )opaque;
	223	uint32_t i;
	224	uint32_t mask;
	225
cdbdb648	226	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	227	if (s->nchannels == 8) {
	228	return pl080_id[(offset - 0xfe0) >> 2];
	229	} else {
	230	return pl081_id[(offset - 0xfe0) >> 2];
	231	}
cdbdb648 PB	232	}
	233	if (offset >= 0x100 && offset < 0x200) {
	234	i = (offset & 0xe0) >> 5;
e69954b9 PB	235	if (i >= s->nchannels)
e69954b9 PB	236	goto bad_offset;
cdbdb648 PB	237	switch (offset >> 2) {
	238	case 0: /* SrcAddr */
	239	return s->chan[i].src;
	240	case 1: /* DestAddr */
	241	return s->chan[i].dest;
	242	case 2: /* LLI */
	243	return s->chan[i].lli;
	244	case 3: /* Control */
	245	return s->chan[i].ctrl;
	246	case 4: /* Configuration */
	247	return s->chan[i].conf;
	248	default:
	249	goto bad_offset;
	250	}
	251	}
	252	switch (offset >> 2) {
	253	case 0: /* IntStatus */
	254	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	255	case 1: /* IntTCStatus */
	256	return (s->tc_int & s->tc_mask);
	257	case 3: /* IntErrorStatus */
	258	return (s->err_int & s->err_mask);
	259	case 5: /* RawIntTCStatus */
	260	return s->tc_int;
	261	case 6: /* RawIntErrorStatus */
	262	return s->err_int;
	263	case 7: /* EnbldChns */
	264	mask = 0;
e69954b9	265	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	266	if (s->chan[i].conf & PL080_CCONF_E)
	267	mask \|= 1 << i;
	268	}
	269	return mask;
	270	case 8: /* SoftBReq */
	271	case 9: /* SoftSReq */
	272	case 10: /* SoftLBReq */
	273	case 11: /* SoftLSReq */
	274	/* ??? Implement these. */
	275	return 0;
	276	case 12: /* Configuration */
	277	return s->conf;
	278	case 13: /* Sync */
	279	return s->sync;
	280	default:
	281	bad_offset:
2ac71179	282	hw_error("pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	283	return 0;
	284	}
	285	}
	286
c227f099	287	static void pl080_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	288	uint32_t value)
	289	{
	290	pl080_state s = (pl080_state )opaque;
	291	int i;
	292
cdbdb648 PB	293	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	294	i = (offset & 0xe0) >> 5;
e69954b9 PB	295	if (i >= s->nchannels)
e69954b9 PB	296	goto bad_offset;
cdbdb648 PB	297	switch (offset >> 2) {
	298	case 0: /* SrcAddr */
	299	s->chan[i].src = value;
	300	break;
	301	case 1: /* DestAddr */
	302	s->chan[i].dest = value;
	303	break;
	304	case 2: /* LLI */
	305	s->chan[i].lli = value;
	306	break;
	307	case 3: /* Control */
	308	s->chan[i].ctrl = value;
	309	break;
	310	case 4: /* Configuration */
	311	s->chan[i].conf = value;
	312	pl080_run(s);
	313	break;
	314	}
	315	}
	316	switch (offset >> 2) {
	317	case 2: /* IntTCClear */
	318	s->tc_int &= ~value;
	319	break;
	320	case 4: /* IntErrorClear */
	321	s->err_int &= ~value;
	322	break;
	323	case 8: /* SoftBReq */
	324	case 9: /* SoftSReq */
	325	case 10: /* SoftLBReq */
	326	case 11: /* SoftLSReq */
	327	/* ??? Implement these. */
2ac71179	328	hw_error("pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	329	break;
	330	case 12: /* Configuration */
	331	s->conf = value;
	332	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
2ac71179	333	hw_error("pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	334	}
	335	pl080_run(s);
	336	break;
	337	case 13: /* Sync */
	338	s->sync = value;
	339	break;
	340	default:
e69954b9	341	bad_offset:
2ac71179	342	hw_error("pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	343	}
	344	pl080_update(s);
	345	}
	346
d60efc6b	347	static CPUReadMemoryFunc * const pl080_readfn[] = {
cdbdb648 PB	348	pl080_read,
	349	pl080_read,
	350	pl080_read
	351	};
	352
d60efc6b	353	static CPUWriteMemoryFunc * const pl080_writefn[] = {
cdbdb648 PB	354	pl080_write,
	355	pl080_write,
	356	pl080_write
	357	};
	358
81a322d4	359	static int pl08x_init(SysBusDevice *dev, int nchannels)
cdbdb648 PB	360	{
cdbdb648 PB	361	int iomemtype;
b4496b13	362	pl080_state *s = FROM_SYSBUS(pl080_state, dev);
cdbdb648	363
1eed09cb	364	iomemtype = cpu_register_io_memory(pl080_readfn,
2507c12a AG	365	pl080_writefn, s,
2507c12a AG	366	DEVICE_NATIVE_ENDIAN);
b4496b13 PB	367	sysbus_init_mmio(dev, 0x1000, iomemtype);
b4496b13 PB	368	sysbus_init_irq(dev, &s->irq);
e69954b9	369	s->nchannels = nchannels;
81a322d4	370	return 0;
cdbdb648	371	}
b4496b13	372
81a322d4	373	static int pl080_init(SysBusDevice *dev)
b4496b13	374	{
81a322d4	375	return pl08x_init(dev, 8);
b4496b13 PB	376	}
b4496b13 PB	377
81a322d4	378	static int pl081_init(SysBusDevice *dev)
b4496b13	379	{
81a322d4	380	return pl08x_init(dev, 2);
b4496b13 PB	381	}
b4496b13 PB	382
ff175853 PM	383	static SysBusDeviceInfo pl080_info = {
	384	.init = pl080_init,
	385	.qdev.name = "pl080",
	386	.qdev.size = sizeof(pl080_state),
	387	.qdev.vmsd = &vmstate_pl080,
	388	.qdev.no_user = 1,
	389	};
	390
	391	static SysBusDeviceInfo pl081_info = {
	392	.init = pl081_init,
	393	.qdev.name = "pl081",
	394	.qdev.size = sizeof(pl080_state),
	395	.qdev.vmsd = &vmstate_pl080,
	396	.qdev.no_user = 1,
	397	};
	398
b4496b13 PB	399	/* The PL080 and PL081 are the same except for the number of channels
	400	they implement (8 and 2 respectively). */
	401	static void pl080_register_devices(void)
	402	{
ff175853 PM	403	sysbus_register_withprop(&pl080_info);
ff175853 PM	404	sysbus_register_withprop(&pl081_info);
b4496b13 PB	405	}
	406
	407	device_init(pl080_register_devices)