[qemu.git] / hw / pl110.c

/* 
 * Arm PrimeCell PL110 Color LCD Controller
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GNU LGPL
 */

#include "vl.h"

#define PL110_CR_EN   0x001
#define PL110_CR_BEBO 0x200
#define PL110_CR_BEPO 0x400
#define PL110_CR_PWR  0x800

enum pl110_bppmode
{
    BPP_1,
    BPP_2,
    BPP_4,
    BPP_8,
    BPP_16,
    BPP_32
};

typedef struct {
    uint32_t base;
    DisplayState *ds;
    /* The Versatile/PB uses a slightly modified PL110 controller.  */
    int versatile;
    void *pic;
    uint32_t timing[4];
    uint32_t cr;
    uint32_t upbase;
    uint32_t lpbase;
    uint32_t int_status;
    uint32_t int_mask;
    int cols;
    int rows;
    enum pl110_bppmode bpp;
    int invalidate;
    uint32_t pallette[256];
    uint32_t raw_pallette[128];
    int irq;
} pl110_state;

static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
   has a different ID.  However Linux only looks for the normal ID.  */
#if 0
static const unsigned char pl110_versatile_id[] =
{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#else
#define pl110_versatile_id pl110_id
#endif

static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
}

static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
}

static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);

#define BITS 8
#include "pl110_template.h"
#define BITS 15
#include "pl110_template.h"
#define BITS 16
#include "pl110_template.h"
#define BITS 24
#include "pl110_template.h"
#define BITS 32
#include "pl110_template.h"

static int pl110_enabled(pl110_state *s)
{
  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}

static void pl110_update_display(void *opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    drawfn* fntable;
    drawfn fn;
    uint32_t *pallette;
    uint32_t addr;
    uint32_t base;
    int dest_width;
    int src_width;
    uint8_t *dest;
    uint8_t *src;
    int first, last = 0;
    int dirty, new_dirty;
    int i;

    if (!pl110_enabled(s))
        return;
    
    switch (s->ds->depth) {
    case 0:
        return;
    case 8:
        fntable = pl110_draw_fn_8;
        dest_width = 1;
        break;
    case 15:
        fntable = pl110_draw_fn_15;
        dest_width = 2;
        break;
    case 16:
        fntable = pl110_draw_fn_16;
        dest_width = 2;
        break;
    case 24:
        fntable = pl110_draw_fn_24;
        dest_width = 3;
        break;
    case 32:
        fntable = pl110_draw_fn_32;
        dest_width = 4;
        break;
    default:
        fprintf(stderr, "pl110: Bad color depth\n");
        exit(1);
    }
    if (s->cr & PL110_CR_BEBO)
      fn = fntable[s->bpp + 6];
    else if (s->cr & PL110_CR_BEPO)
      fn = fntable[s->bpp + 12];
    else
      fn = fntable[s->bpp];
    
    src_width = s->cols;
    switch (s->bpp) {
    case BPP_1:
        src_width >>= 3;
        break;
    case BPP_2:
        src_width >>= 2;
        break;
    case BPP_4:
        src_width >>= 1;
        break;
    case BPP_8:
        break;
    case BPP_16:
        src_width <<= 1;
        break;
    case BPP_32:
        src_width <<= 2;
        break;
    }
    dest_width *= s->cols;
    pallette = s->pallette;
    base = s->upbase;
    /* HACK: Arm aliases physical memory at 0x80000000.  */
    if (base > 0x80000000)
        base -= 0x80000000;
    src = phys_ram_base + base;
    dest = s->ds->data;
    first = -1;
    addr = base;

    dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
    new_dirty = dirty;
    for (i = 0; i < s->rows; i++) {
        if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
            uint32_t tmp;
            new_dirty = 0;
            for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
                new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
                                                           VGA_DIRTY_FLAG);
            }
        }

        if (dirty || new_dirty || s->invalidate) {
            fn(pallette, dest, src, s->cols);
            if (first == -1)
                first = i;
            last = i;
        }
        dirty = new_dirty;
        addr += src_width;
        dest += dest_width;
        src += src_width;
    }
    if (first < 0)
      return;

    s->invalidate = 0;
    cpu_physical_memory_reset_dirty(base + first * src_width,
                                    base + (last + 1) * src_width,
                                    VGA_DIRTY_FLAG);
    dpy_update(s->ds, 0, first, s->cols, last - first + 1);
}

static void pl110_invalidate_display(void * opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    s->invalidate = 1;
}

static void pl110_update_pallette(pl110_state *s, int n)
{
    int i;
    uint32_t raw;
    unsigned int r, g, b;

    raw = s->raw_pallette[n];
    n <<= 1;
    for (i = 0; i < 2; i++) {
        r = (raw & 0x1f) << 3;
        raw >>= 5;
        g = (raw & 0x1f) << 3;
        raw >>= 5;
        b = (raw & 0x1f) << 3;
        /* The I bit is ignored.  */
        raw >>= 6;
        switch (s->ds->depth) {
        case 8:
            s->pallette[n] = rgb_to_pixel8(r, g, b);
            break;
        case 15:
            s->pallette[n] = rgb_to_pixel15(r, g, b);
            break;
        case 16:
            s->pallette[n] = rgb_to_pixel16(r, g, b);
            break;
        case 24:
        case 32:
            s->pallette[n] = rgb_to_pixel32(r, g, b);
            break;
        }
        n++;
    }
}

static void pl110_resize(pl110_state *s, int width, int height)
{
    if (width != s->cols || height != s->rows) {
        if (pl110_enabled(s)) {
            dpy_resize(s->ds, width, height);
        }
    }
    s->cols = width;
    s->rows = height;
}

/* Update interrupts.  */
static void pl110_update(pl110_state *s)
{
  /* TODO: Implement interrupts.  */
}

static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
{
    pl110_state *s = (pl110_state *)opaque;

    offset -= s->base;
    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->versatile)
            return pl110_versatile_id[(offset - 0xfe0) >> 2];
        else
            return pl110_id[(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x200 && offset < 0x400) {
        return s->raw_pallette[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        return s->timing[0];
    case 1: /* LCDTiming1 */
        return s->timing[1];
    case 2: /* LCDTiming2 */
        return s->timing[2];
    case 3: /* LCDTiming3 */
        return s->timing[3];
    case 4: /* LCDUPBASE */
        return s->upbase;
    case 5: /* LCDLPBASE */
        return s->lpbase;
    case 6: /* LCDIMSC */
        return s->int_mask;
    case 7: /* LCDControl */
        return s->cr;
    case 8: /* LCDRIS */
        return s->int_status;
    case 9: /* LCDMIS */
        return s->int_status & s->int_mask;
    case 11: /* LCDUPCURR */
        /* TODO: Implement vertical refresh.  */
        return s->upbase;
    case 12: /* LCDLPCURR */
        return s->lpbase;
    default:
        cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
        return 0;
    }
}

static void pl110_write(void *opaque, target_phys_addr_t offset,
                        uint32_t val)
{
    pl110_state *s = (pl110_state *)opaque;
    int n;

    /* For simplicity invalidate the display whenever a control register
       is writen to.  */
    s->invalidate = 1;
    offset -= s->base;
    if (offset >= 0x200 && offset < 0x400) {
        /* Pallette.  */
        n = (offset - 0x200) >> 2;
        s->raw_pallette[(offset - 0x200) >> 2] = val;
        pl110_update_pallette(s, n);
        return;
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        s->timing[0] = val;
        n = ((val & 0xfc) + 4) * 4;
        pl110_resize(s, n, s->rows);
        break;
    case 1: /* LCDTiming1 */
        s->timing[1] = val;
        n = (val & 0x3ff) + 1;
        pl110_resize(s, s->cols, n);
        break;
    case 2: /* LCDTiming2 */
        s->timing[2] = val;
        break;
    case 3: /* LCDTiming3 */
        s->timing[3] = val;
        break;
    case 4: /* LCDUPBASE */
        s->upbase = val;
        break;
    case 5: /* LCDLPBASE */
        s->lpbase = val;
        break;
    case 6: /* LCDIMSC */
        if (s->versatile)
            goto control;
    imsc:
        s->int_mask = val;
        pl110_update(s);
        break;
    case 7: /* LCDControl */
        if (s->versatile)
            goto imsc;
    control:
        s->cr = val;
        s->bpp = (val >> 1) & 7;
        if (pl110_enabled(s)) {
            dpy_resize(s->ds, s->cols, s->rows);
        }
        break;
    case 10: /* LCDICR */
        s->int_status &= ~val;
        pl110_update(s);
        break;
    default:
        cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
    }
}

static CPUReadMemoryFunc *pl110_readfn[] = {
   pl110_read,
   pl110_read,
   pl110_read
};

static CPUWriteMemoryFunc *pl110_writefn[] = {
   pl110_write,
   pl110_write,
   pl110_write
};

void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq,
                 int versatile)
{
    pl110_state *s;
    int iomemtype;

    s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
    iomemtype = cpu_register_io_memory(0, pl110_readfn,
                                       pl110_writefn, s);
    cpu_register_physical_memory(base, 0x00000fff, iomemtype);
    s->base = base;
    s->ds = ds;
    s->versatile = versatile;
    s->pic = pic;
    s->irq = irq;
    graphic_console_init(ds, pl110_update_display, pl110_invalidate_display,
                         NULL, s);
    /* ??? Save/restore.  */
    return s;
}
Commit	Line	Data
bdd5003a PB	1	/*
	2	* Arm PrimeCell PL110 Color LCD Controller
	3	*
cdbdb648	4	* Copyright (c) 2005-2006 CodeSourcery.
bdd5003a PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GNU LGPL
	8	*/
	9
	10	#include "vl.h"
	11
	12	#define PL110_CR_EN 0x001
	13	#define PL110_CR_BEBO 0x200
	14	#define PL110_CR_BEPO 0x400
	15	#define PL110_CR_PWR 0x800
	16
	17	enum pl110_bppmode
	18	{
	19	BPP_1,
	20	BPP_2,
	21	BPP_4,
	22	BPP_8,
	23	BPP_16,
	24	BPP_32
	25	};
	26
	27	typedef struct {
	28	uint32_t base;
	29	DisplayState *ds;
cdbdb648 PB	30	/* The Versatile/PB uses a slightly modified PL110 controller. */
cdbdb648 PB	31	int versatile;
bdd5003a PB	32	void *pic;
	33	uint32_t timing[4];
	34	uint32_t cr;
	35	uint32_t upbase;
	36	uint32_t lpbase;
	37	uint32_t int_status;
	38	uint32_t int_mask;
	39	int cols;
	40	int rows;
	41	enum pl110_bppmode bpp;
	42	int invalidate;
	43	uint32_t pallette[256];
	44	uint32_t raw_pallette[128];
	45	int irq;
	46	} pl110_state;
	47
	48	static const unsigned char pl110_id[] =
	49	{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	50
cdbdb648 PB	51	/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
	52	has a different ID. However Linux only looks for the normal ID. */
	53	#if 0
	54	static const unsigned char pl110_versatile_id[] =
	55	{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	56	#else
	57	#define pl110_versatile_id pl110_id
	58	#endif
	59
bdd5003a PB	60	static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
	61	{
	62	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
	63	}
	64
	65	static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
	66	{
	67	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
	68	}
	69
	70	static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
	71	{
	72	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
	73	}
	74
	75	static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
	76	{
	77	return (r << 16) \| (g << 8) \| b;
	78	}
	79
	80	static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
	81	{
	82	return (r << 16) \| (g << 8) \| b;
	83	}
	84
	85	typedef void (drawfn)(uint32_t , uint8_t , const uint8_t , int);
	86
	87	#define BITS 8
	88	#include "pl110_template.h"
	89	#define BITS 15
	90	#include "pl110_template.h"
	91	#define BITS 16
	92	#include "pl110_template.h"
	93	#define BITS 24
	94	#include "pl110_template.h"
	95	#define BITS 32
	96	#include "pl110_template.h"
	97
	98	static int pl110_enabled(pl110_state *s)
	99	{
	100	return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
	101	}
	102
95219897	103	static void pl110_update_display(void *opaque)
bdd5003a PB	104	{
	105	pl110_state s = (pl110_state )opaque;
	106	drawfn* fntable;
	107	drawfn fn;
	108	uint32_t *pallette;
	109	uint32_t addr;
	110	uint32_t base;
	111	int dest_width;
	112	int src_width;
	113	uint8_t *dest;
	114	uint8_t *src;
cdbdb648	115	int first, last = 0;
bdd5003a PB	116	int dirty, new_dirty;
	117	int i;
	118
	119	if (!pl110_enabled(s))
	120	return;
	121
	122	switch (s->ds->depth) {
af2f6733 PB	123	case 0:
af2f6733 PB	124	return;
bdd5003a PB	125	case 8:
	126	fntable = pl110_draw_fn_8;
	127	dest_width = 1;
	128	break;
	129	case 15:
	130	fntable = pl110_draw_fn_15;
	131	dest_width = 2;
	132	break;
	133	case 16:
	134	fntable = pl110_draw_fn_16;
	135	dest_width = 2;
	136	break;
	137	case 24:
	138	fntable = pl110_draw_fn_24;
	139	dest_width = 3;
	140	break;
	141	case 32:
	142	fntable = pl110_draw_fn_32;
	143	dest_width = 4;
	144	break;
	145	default:
af2f6733	146	fprintf(stderr, "pl110: Bad color depth\n");
bdd5003a PB	147	exit(1);
	148	}
	149	if (s->cr & PL110_CR_BEBO)
	150	fn = fntable[s->bpp + 6];
	151	else if (s->cr & PL110_CR_BEPO)
	152	fn = fntable[s->bpp + 12];
	153	else
	154	fn = fntable[s->bpp];
	155
	156	src_width = s->cols;
	157	switch (s->bpp) {
	158	case BPP_1:
	159	src_width >>= 3;
	160	break;
	161	case BPP_2:
	162	src_width >>= 2;
	163	break;
	164	case BPP_4:
	165	src_width >>= 1;
	166	break;
	167	case BPP_8:
	168	break;
	169	case BPP_16:
	170	src_width <<= 1;
	171	break;
	172	case BPP_32:
	173	src_width <<= 2;
	174	break;
	175	}
	176	dest_width *= s->cols;
	177	pallette = s->pallette;
	178	base = s->upbase;
	179	/* HACK: Arm aliases physical memory at 0x80000000. */
	180	if (base > 0x80000000)
	181	base -= 0x80000000;
	182	src = phys_ram_base + base;
	183	dest = s->ds->data;
	184	first = -1;
	185	addr = base;
	186
	187	dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
e6e5906b	188	new_dirty = dirty;
bdd5003a	189	for (i = 0; i < s->rows; i++) {
e6e5906b	190	if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
bdd5003a	191	uint32_t tmp;
e6e5906b	192	new_dirty = 0;
bdd5003a PB	193	for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
	194	new_dirty \|= cpu_physical_memory_get_dirty(addr + tmp,
	195	VGA_DIRTY_FLAG);
	196	}
	197	}
	198
	199	if (dirty \|\| new_dirty \|\| s->invalidate) {
	200	fn(pallette, dest, src, s->cols);
	201	if (first == -1)
	202	first = i;
	203	last = i;
	204	}
	205	dirty = new_dirty;
	206	addr += src_width;
	207	dest += dest_width;
	208	src += src_width;
	209	}
	210	if (first < 0)
	211	return;
	212
	213	s->invalidate = 0;
	214	cpu_physical_memory_reset_dirty(base + first * src_width,
	215	base + (last + 1) * src_width,
	216	VGA_DIRTY_FLAG);
	217	dpy_update(s->ds, 0, first, s->cols, last - first + 1);
	218	}
	219
95219897	220	static void pl110_invalidate_display(void * opaque)
bdd5003a PB	221	{
	222	pl110_state s = (pl110_state )opaque;
	223	s->invalidate = 1;
	224	}
	225
	226	static void pl110_update_pallette(pl110_state *s, int n)
	227	{
	228	int i;
	229	uint32_t raw;
	230	unsigned int r, g, b;
	231
	232	raw = s->raw_pallette[n];
	233	n <<= 1;
	234	for (i = 0; i < 2; i++) {
	235	r = (raw & 0x1f) << 3;
	236	raw >>= 5;
	237	g = (raw & 0x1f) << 3;
	238	raw >>= 5;
	239	b = (raw & 0x1f) << 3;
	240	/* The I bit is ignored. */
	241	raw >>= 6;
	242	switch (s->ds->depth) {
	243	case 8:
	244	s->pallette[n] = rgb_to_pixel8(r, g, b);
	245	break;
	246	case 15:
	247	s->pallette[n] = rgb_to_pixel15(r, g, b);
	248	break;
	249	case 16:
	250	s->pallette[n] = rgb_to_pixel16(r, g, b);
	251	break;
	252	case 24:
	253	case 32:
	254	s->pallette[n] = rgb_to_pixel32(r, g, b);
	255	break;
	256	}
	257	n++;
	258	}
	259	}
	260
	261	static void pl110_resize(pl110_state *s, int width, int height)
	262	{
	263	if (width != s->cols \|\| height != s->rows) {
	264	if (pl110_enabled(s)) {
132ea32f	265	dpy_resize(s->ds, width, height);
bdd5003a PB	266	}
	267	}
	268	s->cols = width;
	269	s->rows = height;
	270	}
	271
	272	/* Update interrupts. */
	273	static void pl110_update(pl110_state *s)
	274	{
	275	/* TODO: Implement interrupts. */
	276	}
	277
	278	static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
	279	{
	280	pl110_state s = (pl110_state )opaque;
	281
	282	offset -= s->base;
	283	if (offset >= 0xfe0 && offset < 0x1000) {
cdbdb648 PB	284	if (s->versatile)
	285	return pl110_versatile_id[(offset - 0xfe0) >> 2];
	286	else
	287	return pl110_id[(offset - 0xfe0) >> 2];
bdd5003a PB	288	}
	289	if (offset >= 0x200 && offset < 0x400) {
	290	return s->raw_pallette[(offset - 0x200) >> 2];
	291	}
	292	switch (offset >> 2) {
	293	case 0: /* LCDTiming0 */
	294	return s->timing[0];
	295	case 1: /* LCDTiming1 */
	296	return s->timing[1];
	297	case 2: /* LCDTiming2 */
	298	return s->timing[2];
	299	case 3: /* LCDTiming3 */
	300	return s->timing[3];
	301	case 4: /* LCDUPBASE */
	302	return s->upbase;
	303	case 5: /* LCDLPBASE */
	304	return s->lpbase;
	305	case 6: /* LCDIMSC */
	306	return s->int_mask;
	307	case 7: /* LCDControl */
	308	return s->cr;
	309	case 8: /* LCDRIS */
	310	return s->int_status;
	311	case 9: /* LCDMIS */
	312	return s->int_status & s->int_mask;
	313	case 11: /* LCDUPCURR */
	314	/* TODO: Implement vertical refresh. */
	315	return s->upbase;
	316	case 12: /* LCDLPCURR */
	317	return s->lpbase;
	318	default:
	319	cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
	320	return 0;
	321	}
	322	}
	323
	324	static void pl110_write(void *opaque, target_phys_addr_t offset,
	325	uint32_t val)
	326	{
	327	pl110_state s = (pl110_state )opaque;
	328	int n;
	329
	330	/* For simplicity invalidate the display whenever a control register
	331	is writen to. */
	332	s->invalidate = 1;
	333	offset -= s->base;
	334	if (offset >= 0x200 && offset < 0x400) {
	335	/* Pallette. */
	336	n = (offset - 0x200) >> 2;
	337	s->raw_pallette[(offset - 0x200) >> 2] = val;
	338	pl110_update_pallette(s, n);
e10c2bfb	339	return;
bdd5003a PB	340	}
	341	switch (offset >> 2) {
	342	case 0: /* LCDTiming0 */
	343	s->timing[0] = val;
	344	n = ((val & 0xfc) + 4) * 4;
	345	pl110_resize(s, n, s->rows);
	346	break;
	347	case 1: /* LCDTiming1 */
	348	s->timing[1] = val;
	349	n = (val & 0x3ff) + 1;
	350	pl110_resize(s, s->cols, n);
	351	break;
	352	case 2: /* LCDTiming2 */
	353	s->timing[2] = val;
	354	break;
	355	case 3: /* LCDTiming3 */
	356	s->timing[3] = val;
	357	break;
	358	case 4: /* LCDUPBASE */
	359	s->upbase = val;
	360	break;
	361	case 5: /* LCDLPBASE */
	362	s->lpbase = val;
	363	break;
	364	case 6: /* LCDIMSC */
cdbdb648 PB	365	if (s->versatile)
	366	goto control;
	367	imsc:
bdd5003a PB	368	s->int_mask = val;
	369	pl110_update(s);
	370	break;
	371	case 7: /* LCDControl */
cdbdb648 PB	372	if (s->versatile)
	373	goto imsc;
	374	control:
bdd5003a PB	375	s->cr = val;
	376	s->bpp = (val >> 1) & 7;
	377	if (pl110_enabled(s)) {
	378	dpy_resize(s->ds, s->cols, s->rows);
	379	}
	380	break;
	381	case 10: /* LCDICR */
	382	s->int_status &= ~val;
	383	pl110_update(s);
	384	break;
	385	default:
	386	cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
	387	}
	388	}
	389
	390	static CPUReadMemoryFunc *pl110_readfn[] = {
	391	pl110_read,
	392	pl110_read,
	393	pl110_read
	394	};
	395
	396	static CPUWriteMemoryFunc *pl110_writefn[] = {
	397	pl110_write,
	398	pl110_write,
	399	pl110_write
	400	};
	401
95219897 PB	402	void pl110_init(DisplayState ds, uint32_t base, void *pic, int irq,
95219897 PB	403	int versatile)
bdd5003a PB	404	{
	405	pl110_state *s;
	406	int iomemtype;
	407
	408	s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
	409	iomemtype = cpu_register_io_memory(0, pl110_readfn,
	410	pl110_writefn, s);
95219897	411	cpu_register_physical_memory(base, 0x00000fff, iomemtype);
bdd5003a PB	412	s->base = base;
bdd5003a PB	413	s->ds = ds;
cdbdb648	414	s->versatile = versatile;
bdd5003a PB	415	s->pic = pic;
bdd5003a PB	416	s->irq = irq;
95219897 PB	417	graphic_console_init(ds, pl110_update_display, pl110_invalidate_display,
95219897 PB	418	NULL, s);
bdd5003a PB	419	/* ??? Save/restore. */
	420	return s;
	421	}