[qemu.git] / hw / pl110.c

/*
 * Arm PrimeCell PL110 Color LCD Controller
 *
 * Copyright (c) 2005-2009 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GNU LGPL
 */

#include "sysbus.h"
#include "console.h"
#include "framebuffer.h"

#define PL110_CR_EN   0x001
#define PL110_CR_BGR  0x100
#define PL110_CR_BEBO 0x200
#define PL110_CR_BEPO 0x400
#define PL110_CR_PWR  0x800

enum pl110_bppmode
{
    BPP_1,
    BPP_2,
    BPP_4,
    BPP_8,
    BPP_16,
    BPP_32,
    BPP_16_565, /* PL111 only */
    BPP_12      /* PL111 only */
};


/* The Versatile/PB uses a slightly modified PL110 controller.  */
enum pl110_version
{
    PL110,
    PL110_VERSATILE,
    PL111
};

typedef struct {
    SysBusDevice busdev;
    DisplayState *ds;

    int version;
    uint32_t timing[4];
    uint32_t cr;
    uint32_t upbase;
    uint32_t lpbase;
    uint32_t int_status;
    uint32_t int_mask;
    int cols;
    int rows;
    enum pl110_bppmode bpp;
    int invalidate;
    uint32_t pallette[256];
    uint32_t raw_pallette[128];
    qemu_irq irq;
} pl110_state;

static const VMStateDescription vmstate_pl110 = {
    .name = "pl110",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(version, pl110_state),
        VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
        VMSTATE_UINT32(cr, pl110_state),
        VMSTATE_UINT32(upbase, pl110_state),
        VMSTATE_UINT32(lpbase, pl110_state),
        VMSTATE_UINT32(int_status, pl110_state),
        VMSTATE_UINT32(int_mask, pl110_state),
        VMSTATE_INT32(cols, pl110_state),
        VMSTATE_INT32(rows, pl110_state),
        VMSTATE_UINT32(bpp, pl110_state),
        VMSTATE_INT32(invalidate, pl110_state),
        VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
        VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl110_id[] =
{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
   has a different ID.  However Linux only looks for the normal ID.  */
#if 0
static const unsigned char pl110_versatile_id[] =
{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
#else
#define pl110_versatile_id pl110_id
#endif

static const unsigned char pl111_id[] = {
    0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};

/* Indexed by pl110_version */
static const unsigned char *idregs[] = {
    pl110_id,
    pl110_versatile_id,
    pl111_id
};

#include "pixel_ops.h"

#define BITS 8
#include "pl110_template.h"
#define BITS 15
#include "pl110_template.h"
#define BITS 16
#include "pl110_template.h"
#define BITS 24
#include "pl110_template.h"
#define BITS 32
#include "pl110_template.h"

static int pl110_enabled(pl110_state *s)
{
  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}

static void pl110_update_display(void *opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    drawfn* fntable;
    drawfn fn;
    int dest_width;
    int src_width;
    int bpp_offset;
    int first;
    int last;

    if (!pl110_enabled(s))
        return;

    switch (ds_get_bits_per_pixel(s->ds)) {
    case 0:
        return;
    case 8:
        fntable = pl110_draw_fn_8;
        dest_width = 1;
        break;
    case 15:
        fntable = pl110_draw_fn_15;
        dest_width = 2;
        break;
    case 16:
        fntable = pl110_draw_fn_16;
        dest_width = 2;
        break;
    case 24:
        fntable = pl110_draw_fn_24;
        dest_width = 3;
        break;
    case 32:
        fntable = pl110_draw_fn_32;
        dest_width = 4;
        break;
    default:
        fprintf(stderr, "pl110: Bad color depth\n");
        exit(1);
    }
    if (s->cr & PL110_CR_BGR)
        bpp_offset = 0;
    else
        bpp_offset = 24;

    if ((s->version != PL111) && (s->bpp == BPP_16)) {
        /* The PL110's native 16 bit mode is 5551; however
         * most boards with a PL110 implement an external
         * mux which allows bits to be reshuffled to give
         * 565 format. The mux is typically controlled by
         * an external system register.
         * This should be controlled by a GPIO input pin
         * so boards can wire it up to their register.
         * For now, force 16 bit to be 565, to match
         * previous QEMU PL110 model behaviour.
         *
         * The PL111 straightforwardly implements both
         * 5551 and 565 under control of the bpp field
         * in the LCDControl register.
         */
        bpp_offset += (BPP_16_565 - BPP_16);
    }

    if (s->cr & PL110_CR_BEBO)
        fn = fntable[s->bpp + 8 + bpp_offset];
    else if (s->cr & PL110_CR_BEPO)
        fn = fntable[s->bpp + 16 + bpp_offset];
    else
        fn = fntable[s->bpp + bpp_offset];

    src_width = s->cols;
    switch (s->bpp) {
    case BPP_1:
        src_width >>= 3;
        break;
    case BPP_2:
        src_width >>= 2;
        break;
    case BPP_4:
        src_width >>= 1;
        break;
    case BPP_8:
        break;
    case BPP_16:
    case BPP_16_565:
    case BPP_12:
        src_width <<= 1;
        break;
    case BPP_32:
        src_width <<= 2;
        break;
    }
    dest_width *= s->cols;
    first = 0;
    framebuffer_update_display(s->ds,
                               s->upbase, s->cols, s->rows,
                               src_width, dest_width, 0,
                               s->invalidate,
                               fn, s->pallette,
                               &first, &last);
    if (first >= 0) {
        dpy_update(s->ds, 0, first, s->cols, last - first + 1);
    }
    s->invalidate = 0;
}

static void pl110_invalidate_display(void * opaque)
{
    pl110_state *s = (pl110_state *)opaque;
    s->invalidate = 1;
    if (pl110_enabled(s)) {
        qemu_console_resize(s->ds, s->cols, s->rows);
    }
}

static void pl110_update_pallette(pl110_state *s, int n)
{
    int i;
    uint32_t raw;
    unsigned int r, g, b;

    raw = s->raw_pallette[n];
    n <<= 1;
    for (i = 0; i < 2; i++) {
        r = (raw & 0x1f) << 3;
        raw >>= 5;
        g = (raw & 0x1f) << 3;
        raw >>= 5;
        b = (raw & 0x1f) << 3;
        /* The I bit is ignored.  */
        raw >>= 6;
        switch (ds_get_bits_per_pixel(s->ds)) {
        case 8:
            s->pallette[n] = rgb_to_pixel8(r, g, b);
            break;
        case 15:
            s->pallette[n] = rgb_to_pixel15(r, g, b);
            break;
        case 16:
            s->pallette[n] = rgb_to_pixel16(r, g, b);
            break;
        case 24:
        case 32:
            s->pallette[n] = rgb_to_pixel32(r, g, b);
            break;
        }
        n++;
    }
}

static void pl110_resize(pl110_state *s, int width, int height)
{
    if (width != s->cols || height != s->rows) {
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, width, height);
        }
    }
    s->cols = width;
    s->rows = height;
}

/* Update interrupts.  */
static void pl110_update(pl110_state *s)
{
  /* TODO: Implement interrupts.  */
}

static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
{
    pl110_state *s = (pl110_state *)opaque;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return idregs[s->version][(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x200 && offset < 0x400) {
        return s->raw_pallette[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        return s->timing[0];
    case 1: /* LCDTiming1 */
        return s->timing[1];
    case 2: /* LCDTiming2 */
        return s->timing[2];
    case 3: /* LCDTiming3 */
        return s->timing[3];
    case 4: /* LCDUPBASE */
        return s->upbase;
    case 5: /* LCDLPBASE */
        return s->lpbase;
    case 6: /* LCDIMSC */
        if (s->version != PL110) {
            return s->cr;
        }
        return s->int_mask;
    case 7: /* LCDControl */
        if (s->version != PL110) {
            return s->int_mask;
        }
        return s->cr;
    case 8: /* LCDRIS */
        return s->int_status;
    case 9: /* LCDMIS */
        return s->int_status & s->int_mask;
    case 11: /* LCDUPCURR */
        /* TODO: Implement vertical refresh.  */
        return s->upbase;
    case 12: /* LCDLPCURR */
        return s->lpbase;
    default:
        hw_error("pl110_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl110_write(void *opaque, target_phys_addr_t offset,
                        uint32_t val)
{
    pl110_state *s = (pl110_state *)opaque;
    int n;

    /* For simplicity invalidate the display whenever a control register
       is writen to.  */
    s->invalidate = 1;
    if (offset >= 0x200 && offset < 0x400) {
        /* Pallette.  */
        n = (offset - 0x200) >> 2;
        s->raw_pallette[(offset - 0x200) >> 2] = val;
        pl110_update_pallette(s, n);
        return;
    }
    switch (offset >> 2) {
    case 0: /* LCDTiming0 */
        s->timing[0] = val;
        n = ((val & 0xfc) + 4) * 4;
        pl110_resize(s, n, s->rows);
        break;
    case 1: /* LCDTiming1 */
        s->timing[1] = val;
        n = (val & 0x3ff) + 1;
        pl110_resize(s, s->cols, n);
        break;
    case 2: /* LCDTiming2 */
        s->timing[2] = val;
        break;
    case 3: /* LCDTiming3 */
        s->timing[3] = val;
        break;
    case 4: /* LCDUPBASE */
        s->upbase = val;
        break;
    case 5: /* LCDLPBASE */
        s->lpbase = val;
        break;
    case 6: /* LCDIMSC */
        if (s->version != PL110) {
            goto control;
        }
    imsc:
        s->int_mask = val;
        pl110_update(s);
        break;
    case 7: /* LCDControl */
        if (s->version != PL110) {
            goto imsc;
        }
    control:
        s->cr = val;
        s->bpp = (val >> 1) & 7;
        if (pl110_enabled(s)) {
            qemu_console_resize(s->ds, s->cols, s->rows);
        }
        break;
    case 10: /* LCDICR */
        s->int_status &= ~val;
        pl110_update(s);
        break;
    default:
        hw_error("pl110_write: Bad offset %x\n", (int)offset);
    }
}

static CPUReadMemoryFunc * const pl110_readfn[] = {
   pl110_read,
   pl110_read,
   pl110_read
};

static CPUWriteMemoryFunc * const pl110_writefn[] = {
   pl110_write,
   pl110_write,
   pl110_write
};

static int pl110_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
    int iomemtype;

    iomemtype = cpu_register_io_memory(pl110_readfn,
                                       pl110_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq);
    s->ds = graphic_console_init(pl110_update_display,
                                 pl110_invalidate_display,
                                 NULL, NULL, s);
    return 0;
}

static int pl110_versatile_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
    s->version = PL110_VERSATILE;
    return pl110_init(dev);
}

static int pl111_init(SysBusDevice *dev)
{
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
    s->version = PL111;
    return pl110_init(dev);
}

static SysBusDeviceInfo pl110_info = {
    .init = pl110_init,
    .qdev.name = "pl110",
    .qdev.size = sizeof(pl110_state),
    .qdev.vmsd = &vmstate_pl110,
    .qdev.no_user = 1,
};

static SysBusDeviceInfo pl110_versatile_info = {
    .init = pl110_versatile_init,
    .qdev.name = "pl110_versatile",
    .qdev.size = sizeof(pl110_state),
    .qdev.vmsd = &vmstate_pl110,
    .qdev.no_user = 1,
};

static SysBusDeviceInfo pl111_info = {
    .init = pl111_init,
    .qdev.name = "pl111",
    .qdev.size = sizeof(pl110_state),
    .qdev.vmsd = &vmstate_pl110,
    .qdev.no_user = 1,
};

static void pl110_register_devices(void)
{
    sysbus_register_withprop(&pl110_info);
    sysbus_register_withprop(&pl110_versatile_info);
    sysbus_register_withprop(&pl111_info);
}

device_init(pl110_register_devices)
Commit	Line	Data
5fafdf24	1	/*
bdd5003a PB	2	* Arm PrimeCell PL110 Color LCD Controller
bdd5003a PB	3	*
2e9bdce5	4	* Copyright (c) 2005-2009 CodeSourcery.
bdd5003a PB	5	* Written by Paul Brook
bdd5003a PB	6	*
8e31bf38	7	* This code is licensed under the GNU LGPL
bdd5003a PB	8	*/
bdd5003a PB	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b	11	#include "console.h"
714fa308	12	#include "framebuffer.h"
bdd5003a PB	13
bdd5003a PB	14	#define PL110_CR_EN 0x001
e9c05b42	15	#define PL110_CR_BGR 0x100
bdd5003a PB	16	#define PL110_CR_BEBO 0x200
	17	#define PL110_CR_BEPO 0x400
	18	#define PL110_CR_PWR 0x800
	19
	20	enum pl110_bppmode
	21	{
	22	BPP_1,
	23	BPP_2,
	24	BPP_4,
	25	BPP_8,
	26	BPP_16,
4fbf5556 PM	27	BPP_32,
	28	BPP_16_565, /* PL111 only */
	29	BPP_12 /* PL111 only */
	30	};
	31
	32
	33	/* The Versatile/PB uses a slightly modified PL110 controller. */
	34	enum pl110_version
	35	{
	36	PL110,
	37	PL110_VERSATILE,
	38	PL111
bdd5003a PB	39	};
	40
	41	typedef struct {
2e9bdce5	42	SysBusDevice busdev;
bdd5003a	43	DisplayState *ds;
c60e08d9	44
4fbf5556	45	int version;
bdd5003a PB	46	uint32_t timing[4];
	47	uint32_t cr;
	48	uint32_t upbase;
	49	uint32_t lpbase;
	50	uint32_t int_status;
	51	uint32_t int_mask;
	52	int cols;
	53	int rows;
	54	enum pl110_bppmode bpp;
	55	int invalidate;
	56	uint32_t pallette[256];
	57	uint32_t raw_pallette[128];
d537cf6c	58	qemu_irq irq;
bdd5003a PB	59	} pl110_state;
bdd5003a PB	60
8c60d065 PM	61	static const VMStateDescription vmstate_pl110 = {
	62	.name = "pl110",
	63	.version_id = 1,
	64	.minimum_version_id = 1,
	65	.fields = (VMStateField[]) {
4fbf5556	66	VMSTATE_INT32(version, pl110_state),
8c60d065 PM	67	VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
	68	VMSTATE_UINT32(cr, pl110_state),
	69	VMSTATE_UINT32(upbase, pl110_state),
	70	VMSTATE_UINT32(lpbase, pl110_state),
	71	VMSTATE_UINT32(int_status, pl110_state),
	72	VMSTATE_UINT32(int_mask, pl110_state),
	73	VMSTATE_INT32(cols, pl110_state),
	74	VMSTATE_INT32(rows, pl110_state),
	75	VMSTATE_UINT32(bpp, pl110_state),
	76	VMSTATE_INT32(invalidate, pl110_state),
	77	VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
	78	VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
	79	VMSTATE_END_OF_LIST()
	80	}
	81	};
	82
bdd5003a PB	83	static const unsigned char pl110_id[] =
	84	{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	85
cdbdb648 PB	86	/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
	87	has a different ID. However Linux only looks for the normal ID. */
	88	#if 0
	89	static const unsigned char pl110_versatile_id[] =
	90	{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	91	#else
	92	#define pl110_versatile_id pl110_id
	93	#endif
	94
4fbf5556 PM	95	static const unsigned char pl111_id[] = {
	96	0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
	97	};
	98
	99	/* Indexed by pl110_version */
	100	static const unsigned char *idregs[] = {
	101	pl110_id,
	102	pl110_versatile_id,
	103	pl111_id
	104	};
	105
602dafcf	106	#include "pixel_ops.h"
bdd5003a	107
bdd5003a PB	108	#define BITS 8
	109	#include "pl110_template.h"
	110	#define BITS 15
	111	#include "pl110_template.h"
	112	#define BITS 16
	113	#include "pl110_template.h"
	114	#define BITS 24
	115	#include "pl110_template.h"
	116	#define BITS 32
	117	#include "pl110_template.h"
	118
	119	static int pl110_enabled(pl110_state *s)
	120	{
	121	return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
	122	}
	123
95219897	124	static void pl110_update_display(void *opaque)
bdd5003a PB	125	{
	126	pl110_state s = (pl110_state )opaque;
	127	drawfn* fntable;
	128	drawfn fn;
bdd5003a PB	129	int dest_width;
bdd5003a PB	130	int src_width;
e9c05b42	131	int bpp_offset;
714fa308 PB	132	int first;
714fa308 PB	133	int last;
bdd5003a PB	134
	135	if (!pl110_enabled(s))
	136	return;
3b46e624	137
0e1f5a0c	138	switch (ds_get_bits_per_pixel(s->ds)) {
af2f6733 PB	139	case 0:
af2f6733 PB	140	return;
bdd5003a PB	141	case 8:
	142	fntable = pl110_draw_fn_8;
	143	dest_width = 1;
	144	break;
	145	case 15:
	146	fntable = pl110_draw_fn_15;
	147	dest_width = 2;
	148	break;
	149	case 16:
	150	fntable = pl110_draw_fn_16;
	151	dest_width = 2;
	152	break;
	153	case 24:
	154	fntable = pl110_draw_fn_24;
	155	dest_width = 3;
	156	break;
	157	case 32:
	158	fntable = pl110_draw_fn_32;
	159	dest_width = 4;
	160	break;
	161	default:
af2f6733	162	fprintf(stderr, "pl110: Bad color depth\n");
bdd5003a PB	163	exit(1);
bdd5003a PB	164	}
e9c05b42 AZ	165	if (s->cr & PL110_CR_BGR)
	166	bpp_offset = 0;
	167	else
4fbf5556 PM	168	bpp_offset = 24;
	169
	170	if ((s->version != PL111) && (s->bpp == BPP_16)) {
	171	/* The PL110's native 16 bit mode is 5551; however
	172	* most boards with a PL110 implement an external
	173	* mux which allows bits to be reshuffled to give
	174	* 565 format. The mux is typically controlled by
	175	* an external system register.
	176	* This should be controlled by a GPIO input pin
	177	* so boards can wire it up to their register.
	178	* For now, force 16 bit to be 565, to match
	179	* previous QEMU PL110 model behaviour.
	180	*
	181	* The PL111 straightforwardly implements both
	182	* 5551 and 565 under control of the bpp field
	183	* in the LCDControl register.
	184	*/
	185	bpp_offset += (BPP_16_565 - BPP_16);
	186	}
e9c05b42	187
bdd5003a	188	if (s->cr & PL110_CR_BEBO)
4fbf5556	189	fn = fntable[s->bpp + 8 + bpp_offset];
bdd5003a	190	else if (s->cr & PL110_CR_BEPO)
4fbf5556	191	fn = fntable[s->bpp + 16 + bpp_offset];
bdd5003a	192	else
e9c05b42	193	fn = fntable[s->bpp + bpp_offset];
3b46e624	194
bdd5003a PB	195	src_width = s->cols;
	196	switch (s->bpp) {
	197	case BPP_1:
	198	src_width >>= 3;
	199	break;
	200	case BPP_2:
	201	src_width >>= 2;
	202	break;
	203	case BPP_4:
	204	src_width >>= 1;
	205	break;
	206	case BPP_8:
	207	break;
	208	case BPP_16:
4fbf5556 PM	209	case BPP_16_565:
4fbf5556 PM	210	case BPP_12:
bdd5003a PB	211	src_width <<= 1;
	212	break;
	213	case BPP_32:
	214	src_width <<= 2;
	215	break;
	216	}
	217	dest_width *= s->cols;
714fa308 PB	218	first = 0;
	219	framebuffer_update_display(s->ds,
	220	s->upbase, s->cols, s->rows,
	221	src_width, dest_width, 0,
	222	s->invalidate,
	223	fn, s->pallette,
	224	&first, &last);
	225	if (first >= 0) {
	226	dpy_update(s->ds, 0, first, s->cols, last - first + 1);
bdd5003a	227	}
bdd5003a	228	s->invalidate = 0;
bdd5003a PB	229	}
bdd5003a PB	230
95219897	231	static void pl110_invalidate_display(void * opaque)
bdd5003a PB	232	{
	233	pl110_state s = (pl110_state )opaque;
	234	s->invalidate = 1;
bfdb3629 BS	235	if (pl110_enabled(s)) {
	236	qemu_console_resize(s->ds, s->cols, s->rows);
	237	}
bdd5003a PB	238	}
	239
	240	static void pl110_update_pallette(pl110_state *s, int n)
	241	{
	242	int i;
	243	uint32_t raw;
	244	unsigned int r, g, b;
	245
	246	raw = s->raw_pallette[n];
	247	n <<= 1;
	248	for (i = 0; i < 2; i++) {
	249	r = (raw & 0x1f) << 3;
	250	raw >>= 5;
	251	g = (raw & 0x1f) << 3;
	252	raw >>= 5;
	253	b = (raw & 0x1f) << 3;
	254	/* The I bit is ignored. */
	255	raw >>= 6;
0e1f5a0c	256	switch (ds_get_bits_per_pixel(s->ds)) {
bdd5003a PB	257	case 8:
	258	s->pallette[n] = rgb_to_pixel8(r, g, b);
	259	break;
	260	case 15:
	261	s->pallette[n] = rgb_to_pixel15(r, g, b);
	262	break;
	263	case 16:
	264	s->pallette[n] = rgb_to_pixel16(r, g, b);
	265	break;
	266	case 24:
	267	case 32:
	268	s->pallette[n] = rgb_to_pixel32(r, g, b);
	269	break;
	270	}
	271	n++;
	272	}
	273	}
	274
	275	static void pl110_resize(pl110_state *s, int width, int height)
	276	{
	277	if (width != s->cols \|\| height != s->rows) {
	278	if (pl110_enabled(s)) {
3023f332	279	qemu_console_resize(s->ds, width, height);
bdd5003a PB	280	}
	281	}
	282	s->cols = width;
	283	s->rows = height;
	284	}
	285
	286	/* Update interrupts. */
	287	static void pl110_update(pl110_state *s)
	288	{
	289	/* TODO: Implement interrupts. */
	290	}
	291
c227f099	292	static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
bdd5003a PB	293	{
	294	pl110_state s = (pl110_state )opaque;
	295
bdd5003a	296	if (offset >= 0xfe0 && offset < 0x1000) {
4fbf5556	297	return idregs[s->version][(offset - 0xfe0) >> 2];
bdd5003a PB	298	}
	299	if (offset >= 0x200 && offset < 0x400) {
	300	return s->raw_pallette[(offset - 0x200) >> 2];
	301	}
	302	switch (offset >> 2) {
	303	case 0: /* LCDTiming0 */
	304	return s->timing[0];
	305	case 1: /* LCDTiming1 */
	306	return s->timing[1];
	307	case 2: /* LCDTiming2 */
	308	return s->timing[2];
	309	case 3: /* LCDTiming3 */
	310	return s->timing[3];
	311	case 4: /* LCDUPBASE */
	312	return s->upbase;
	313	case 5: /* LCDLPBASE */
	314	return s->lpbase;
	315	case 6: /* LCDIMSC */
4fbf5556 PM	316	if (s->version != PL110) {
	317	return s->cr;
	318	}
bdd5003a PB	319	return s->int_mask;
bdd5003a PB	320	case 7: /* LCDControl */
4fbf5556 PM	321	if (s->version != PL110) {
	322	return s->int_mask;
	323	}
bdd5003a PB	324	return s->cr;
	325	case 8: /* LCDRIS */
	326	return s->int_status;
	327	case 9: /* LCDMIS */
	328	return s->int_status & s->int_mask;
	329	case 11: /* LCDUPCURR */
	330	/* TODO: Implement vertical refresh. */
	331	return s->upbase;
	332	case 12: /* LCDLPCURR */
	333	return s->lpbase;
	334	default:
2ac71179	335	hw_error("pl110_read: Bad offset %x\n", (int)offset);
bdd5003a PB	336	return 0;
	337	}
	338	}
	339
c227f099	340	static void pl110_write(void *opaque, target_phys_addr_t offset,
bdd5003a PB	341	uint32_t val)
	342	{
	343	pl110_state s = (pl110_state )opaque;
	344	int n;
	345
	346	/* For simplicity invalidate the display whenever a control register
	347	is writen to. */
	348	s->invalidate = 1;
bdd5003a PB	349	if (offset >= 0x200 && offset < 0x400) {
	350	/* Pallette. */
	351	n = (offset - 0x200) >> 2;
	352	s->raw_pallette[(offset - 0x200) >> 2] = val;
	353	pl110_update_pallette(s, n);
e10c2bfb	354	return;
bdd5003a PB	355	}
	356	switch (offset >> 2) {
	357	case 0: /* LCDTiming0 */
	358	s->timing[0] = val;
	359	n = ((val & 0xfc) + 4) * 4;
	360	pl110_resize(s, n, s->rows);
	361	break;
	362	case 1: /* LCDTiming1 */
	363	s->timing[1] = val;
	364	n = (val & 0x3ff) + 1;
	365	pl110_resize(s, s->cols, n);
	366	break;
	367	case 2: /* LCDTiming2 */
	368	s->timing[2] = val;
	369	break;
	370	case 3: /* LCDTiming3 */
	371	s->timing[3] = val;
	372	break;
	373	case 4: /* LCDUPBASE */
	374	s->upbase = val;
	375	break;
	376	case 5: /* LCDLPBASE */
	377	s->lpbase = val;
	378	break;
	379	case 6: /* LCDIMSC */
4fbf5556	380	if (s->version != PL110) {
cdbdb648	381	goto control;
4fbf5556	382	}
cdbdb648	383	imsc:
bdd5003a PB	384	s->int_mask = val;
	385	pl110_update(s);
	386	break;
	387	case 7: /* LCDControl */
4fbf5556	388	if (s->version != PL110) {
cdbdb648	389	goto imsc;
4fbf5556	390	}
cdbdb648	391	control:
bdd5003a PB	392	s->cr = val;
	393	s->bpp = (val >> 1) & 7;
	394	if (pl110_enabled(s)) {
3023f332	395	qemu_console_resize(s->ds, s->cols, s->rows);
bdd5003a PB	396	}
	397	break;
	398	case 10: /* LCDICR */
	399	s->int_status &= ~val;
	400	pl110_update(s);
	401	break;
	402	default:
2ac71179	403	hw_error("pl110_write: Bad offset %x\n", (int)offset);
bdd5003a PB	404	}
	405	}
	406
d60efc6b	407	static CPUReadMemoryFunc * const pl110_readfn[] = {
bdd5003a PB	408	pl110_read,
	409	pl110_read,
	410	pl110_read
	411	};
	412
d60efc6b	413	static CPUWriteMemoryFunc * const pl110_writefn[] = {
bdd5003a PB	414	pl110_write,
	415	pl110_write,
	416	pl110_write
	417	};
	418
81a322d4	419	static int pl110_init(SysBusDevice *dev)
bdd5003a	420	{
2e9bdce5	421	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
bdd5003a PB	422	int iomemtype;
bdd5003a PB	423
1eed09cb	424	iomemtype = cpu_register_io_memory(pl110_readfn,
2507c12a AG	425	pl110_writefn, s,
2507c12a AG	426	DEVICE_NATIVE_ENDIAN);
2e9bdce5 PB	427	sysbus_init_mmio(dev, 0x1000, iomemtype);
2e9bdce5 PB	428	sysbus_init_irq(dev, &s->irq);
3023f332 AL	429	s->ds = graphic_console_init(pl110_update_display,
	430	pl110_invalidate_display,
	431	NULL, NULL, s);
81a322d4	432	return 0;
bdd5003a	433	}
2e9bdce5	434
81a322d4	435	static int pl110_versatile_init(SysBusDevice *dev)
2e9bdce5 PB	436	{
2e9bdce5 PB	437	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
4fbf5556 PM	438	s->version = PL110_VERSATILE;
	439	return pl110_init(dev);
	440	}
	441
	442	static int pl111_init(SysBusDevice *dev)
	443	{
	444	pl110_state *s = FROM_SYSBUS(pl110_state, dev);
	445	s->version = PL111;
81a322d4	446	return pl110_init(dev);
2e9bdce5 PB	447	}
2e9bdce5 PB	448
8c60d065 PM	449	static SysBusDeviceInfo pl110_info = {
	450	.init = pl110_init,
	451	.qdev.name = "pl110",
	452	.qdev.size = sizeof(pl110_state),
	453	.qdev.vmsd = &vmstate_pl110,
	454	.qdev.no_user = 1,
	455	};
	456
	457	static SysBusDeviceInfo pl110_versatile_info = {
	458	.init = pl110_versatile_init,
	459	.qdev.name = "pl110_versatile",
	460	.qdev.size = sizeof(pl110_state),
	461	.qdev.vmsd = &vmstate_pl110,
	462	.qdev.no_user = 1,
	463	};
	464
4fbf5556 PM	465	static SysBusDeviceInfo pl111_info = {
	466	.init = pl111_init,
	467	.qdev.name = "pl111",
	468	.qdev.size = sizeof(pl110_state),
	469	.qdev.vmsd = &vmstate_pl110,
	470	.qdev.no_user = 1,
	471	};
	472
2e9bdce5 PB	473	static void pl110_register_devices(void)
2e9bdce5 PB	474	{
8c60d065 PM	475	sysbus_register_withprop(&pl110_info);
8c60d065 PM	476	sysbus_register_withprop(&pl110_versatile_info);
4fbf5556	477	sysbus_register_withprop(&pl111_info);
2e9bdce5 PB	478	}
	479
	480	device_init(pl110_register_devices)