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Commit | Line | Data |
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1db09b84 | 1 | /* |
b3305981 | 2 | * QEMU PowerPC e500-based platforms |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
e6eaabeb | 19 | #include "e500.h" |
3eddc1be | 20 | #include "e500-ccsr.h" |
1db09b84 | 21 | #include "net.h" |
4a18e7c9 | 22 | #include "hw/hw.h" |
488cb996 | 23 | #include "hw/serial.h" |
4a18e7c9 SW |
24 | #include "hw/pci.h" |
25 | #include "hw/boards.h" | |
1db09b84 AJ |
26 | #include "sysemu.h" |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "device_tree.h" | |
4a18e7c9 SW |
30 | #include "hw/openpic.h" |
31 | #include "hw/ppc.h" | |
32 | #include "hw/loader.h" | |
ca20cf32 | 33 | #include "elf.h" |
4a18e7c9 | 34 | #include "hw/sysbus.h" |
39186d8a | 35 | #include "exec-memory.h" |
cba2026a | 36 | #include "host-utils.h" |
1db09b84 AJ |
37 | |
38 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
39 | #define UIMAGE_LOAD_BASE 0 | |
9dd5eba1 | 40 | #define DTC_LOAD_PAD 0x1800000 |
75bb6589 LY |
41 | #define DTC_PAD_MASK 0xFFFFF |
42 | #define INITRD_LOAD_PAD 0x2000000 | |
43 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
44 | |
45 | #define RAM_SIZES_ALIGN (64UL << 20) | |
46 | ||
b3305981 | 47 | /* TODO: parameterize */ |
ed2bc496 AG |
48 | #define MPC8544_CCSRBAR_BASE 0xE0000000ULL |
49 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL | |
dffb1dc2 | 50 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
a911b7a9 | 51 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
dffb1dc2 BB |
52 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
53 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL | |
54 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL | |
55 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ | |
56 | MPC8544_PCI_REGS_OFFSET) | |
ed2bc496 AG |
57 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
58 | #define MPC8544_PCI_IO 0xE1000000ULL | |
dffb1dc2 | 59 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
ed2bc496 | 60 | #define MPC8544_SPIN_BASE 0xEF000000ULL |
1db09b84 | 61 | |
3b989d49 AG |
62 | struct boot_info |
63 | { | |
64 | uint32_t dt_base; | |
cba2026a | 65 | uint32_t dt_size; |
3b989d49 AG |
66 | uint32_t entry; |
67 | }; | |
68 | ||
347dd79d AG |
69 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
70 | int nr_slots, int *len) | |
0dbc0798 | 71 | { |
347dd79d AG |
72 | int i = 0; |
73 | int slot; | |
74 | int pci_irq; | |
75 | int last_slot = first_slot + nr_slots; | |
76 | uint32_t *pci_map; | |
77 | ||
78 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); | |
79 | pci_map = g_malloc(*len); | |
80 | ||
81 | for (slot = first_slot; slot < last_slot; slot++) { | |
82 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { | |
83 | pci_map[i++] = cpu_to_be32(slot << 11); | |
84 | pci_map[i++] = cpu_to_be32(0x0); | |
85 | pci_map[i++] = cpu_to_be32(0x0); | |
86 | pci_map[i++] = cpu_to_be32(pci_irq + 1); | |
87 | pci_map[i++] = cpu_to_be32(mpic); | |
88 | pci_map[i++] = cpu_to_be32(((pci_irq + slot) % 4) + 1); | |
89 | pci_map[i++] = cpu_to_be32(0x1); | |
90 | } | |
0dbc0798 | 91 | } |
347dd79d AG |
92 | |
93 | assert((i * sizeof(uint32_t)) == *len); | |
94 | ||
95 | return pci_map; | |
0dbc0798 AG |
96 | } |
97 | ||
a053a7ce AG |
98 | static void dt_serial_create(void *fdt, unsigned long long offset, |
99 | const char *soc, const char *mpic, | |
100 | const char *alias, int idx, bool defcon) | |
101 | { | |
102 | char ser[128]; | |
103 | ||
104 | snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); | |
105 | qemu_devtree_add_subnode(fdt, ser); | |
106 | qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); | |
107 | qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); | |
108 | qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); | |
109 | qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); | |
110 | qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); | |
7e99826c | 111 | qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); |
a053a7ce AG |
112 | qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); |
113 | qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); | |
114 | ||
115 | if (defcon) { | |
116 | qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); | |
117 | } | |
118 | } | |
119 | ||
b3305981 | 120 | static int ppce500_load_device_tree(CPUPPCState *env, |
e6eaabeb | 121 | PPCE500Params *params, |
a8170e5e AK |
122 | hwaddr addr, |
123 | hwaddr initrd_base, | |
124 | hwaddr initrd_size) | |
1db09b84 | 125 | { |
dbf916d8 | 126 | int ret = -1; |
e6eaabeb | 127 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; |
7ec632b4 | 128 | int fdt_size; |
dbf916d8 | 129 | void *fdt; |
5de6b46d | 130 | uint8_t hypercall[16]; |
911d6e7a AG |
131 | uint32_t clock_freq = 400000000; |
132 | uint32_t tb_freq = 400000000; | |
621d05e3 | 133 | int i; |
e6eaabeb | 134 | const char *toplevel_compat = NULL; /* user override */ |
ebb9518a | 135 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
5da96624 | 136 | char soc[128]; |
19ac9dea AG |
137 | char mpic[128]; |
138 | uint32_t mpic_ph; | |
a911b7a9 | 139 | uint32_t msi_ph; |
f5038483 | 140 | char gutil[128]; |
0dbc0798 | 141 | char pci[128]; |
a911b7a9 | 142 | char msi[128]; |
347dd79d AG |
143 | uint32_t *pci_map = NULL; |
144 | int len; | |
3627757e AG |
145 | uint32_t pci_ranges[14] = |
146 | { | |
147 | 0x2000000, 0x0, 0xc0000000, | |
148 | 0x0, 0xc0000000, | |
149 | 0x0, 0x20000000, | |
150 | ||
151 | 0x1000000, 0x0, 0x0, | |
152 | 0x0, 0xe1000000, | |
153 | 0x0, 0x10000, | |
154 | }; | |
25b42708 | 155 | QemuOpts *machine_opts; |
d1b93565 AG |
156 | const char *dtb_file = NULL; |
157 | ||
158 | machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); | |
159 | if (machine_opts) { | |
d1b93565 | 160 | dtb_file = qemu_opt_get(machine_opts, "dtb"); |
e6eaabeb | 161 | toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); |
d1b93565 AG |
162 | } |
163 | ||
164 | if (dtb_file) { | |
165 | char *filename; | |
166 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); | |
167 | if (!filename) { | |
168 | goto out; | |
169 | } | |
170 | ||
171 | fdt = load_device_tree(filename, &fdt_size); | |
172 | if (!fdt) { | |
173 | goto out; | |
174 | } | |
175 | goto done; | |
176 | } | |
1db09b84 | 177 | |
2636fcb6 | 178 | fdt = create_device_tree(&fdt_size); |
5cea8590 PB |
179 | if (fdt == NULL) { |
180 | goto out; | |
181 | } | |
1db09b84 AJ |
182 | |
183 | /* Manipulate device tree in memory. */ | |
3627757e AG |
184 | qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); |
185 | qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); | |
51b852b7 | 186 | |
dd0bcfca AG |
187 | qemu_devtree_add_subnode(fdt, "/memory"); |
188 | qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); | |
189 | qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
190 | sizeof(mem_reg_property)); | |
1db09b84 | 191 | |
f5231aaf | 192 | qemu_devtree_add_subnode(fdt, "/chosen"); |
3b989d49 AG |
193 | if (initrd_size) { |
194 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
195 | initrd_base); | |
196 | if (ret < 0) { | |
197 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
198 | } | |
1db09b84 | 199 | |
3b989d49 AG |
200 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
201 | (initrd_base + initrd_size)); | |
202 | if (ret < 0) { | |
203 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
204 | } | |
205 | } | |
1db09b84 AJ |
206 | |
207 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
e6eaabeb | 208 | params->kernel_cmdline); |
1db09b84 AJ |
209 | if (ret < 0) |
210 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
211 | ||
212 | if (kvm_enabled()) { | |
911d6e7a AG |
213 | /* Read out host's frequencies */ |
214 | clock_freq = kvmppc_get_clockfreq(); | |
215 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
216 | |
217 | /* indicate KVM hypercall interface */ | |
d50f71a5 | 218 | qemu_devtree_add_subnode(fdt, "/hypervisor"); |
5de6b46d AG |
219 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
220 | "linux,kvm"); | |
221 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
222 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
223 | hypercall, sizeof(hypercall)); | |
1db09b84 | 224 | } |
3b989d49 | 225 | |
625e665b AG |
226 | /* Create CPU nodes */ |
227 | qemu_devtree_add_subnode(fdt, "/cpus"); | |
228 | qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
229 | qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
230 | ||
1e3debf0 AG |
231 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
232 | the first node as boot node and be happy */ | |
233 | for (i = smp_cpus - 1; i >= 0; i--) { | |
621d05e3 | 234 | char cpu_name[128]; |
1d2e5c52 | 235 | uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); |
10f25a46 | 236 | |
1e3debf0 AG |
237 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
238 | if (env->cpu_index == i) { | |
239 | break; | |
240 | } | |
241 | } | |
242 | ||
243 | if (!env) { | |
244 | continue; | |
245 | } | |
246 | ||
247 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); | |
248 | qemu_devtree_add_subnode(fdt, cpu_name); | |
621d05e3 AG |
249 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
250 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 AG |
251 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
252 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); | |
253 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", | |
254 | env->dcache_line_size); | |
255 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
256 | env->icache_line_size); | |
257 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
258 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
259 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
260 | if (env->cpu_index) { | |
261 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); | |
262 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
1d2e5c52 AG |
263 | qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", |
264 | cpu_release_addr); | |
1e3debf0 AG |
265 | } else { |
266 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
267 | } | |
1db09b84 AJ |
268 | } |
269 | ||
0cfc6e8d | 270 | qemu_devtree_add_subnode(fdt, "/aliases"); |
5da96624 | 271 | /* XXX These should go into their respective devices' code */ |
ed2bc496 | 272 | snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); |
5da96624 AG |
273 | qemu_devtree_add_subnode(fdt, soc); |
274 | qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); | |
ebb9518a AG |
275 | qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, |
276 | sizeof(compatible_sb)); | |
5da96624 AG |
277 | qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); |
278 | qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); | |
3627757e AG |
279 | qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, |
280 | MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, | |
5da96624 | 281 | MPC8544_CCSRBAR_SIZE); |
5da96624 AG |
282 | /* XXX should contain a reasonable value */ |
283 | qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); | |
284 | ||
dffb1dc2 | 285 | snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
19ac9dea AG |
286 | qemu_devtree_add_subnode(fdt, mpic); |
287 | qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); | |
7e99826c | 288 | qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic"); |
dffb1dc2 BB |
289 | qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, |
290 | 0x40000); | |
19ac9dea | 291 | qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); |
7e99826c | 292 | qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); |
19ac9dea AG |
293 | mpic_ph = qemu_devtree_alloc_phandle(fdt); |
294 | qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); | |
295 | qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); | |
296 | qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); | |
297 | ||
0cfc6e8d AG |
298 | /* |
299 | * We have to generate ser1 first, because Linux takes the first | |
300 | * device it finds in the dt as serial output device. And we generate | |
301 | * devices in reverse order to the dt. | |
302 | */ | |
dffb1dc2 | 303 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
a053a7ce | 304 | soc, mpic, "serial1", 1, false); |
dffb1dc2 | 305 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
a053a7ce | 306 | soc, mpic, "serial0", 0, true); |
0cfc6e8d | 307 | |
ed2bc496 | 308 | snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, |
dffb1dc2 | 309 | MPC8544_UTIL_OFFSET); |
f5038483 AG |
310 | qemu_devtree_add_subnode(fdt, gutil); |
311 | qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); | |
dffb1dc2 | 312 | qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); |
f5038483 AG |
313 | qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); |
314 | ||
a911b7a9 AG |
315 | snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
316 | qemu_devtree_add_subnode(fdt, msi); | |
317 | qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); | |
318 | qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); | |
319 | msi_ph = qemu_devtree_alloc_phandle(fdt); | |
320 | qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); | |
321 | qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); | |
322 | qemu_devtree_setprop_cells(fdt, msi, "interrupts", | |
323 | 0xe0, 0x0, | |
324 | 0xe1, 0x0, | |
325 | 0xe2, 0x0, | |
326 | 0xe3, 0x0, | |
327 | 0xe4, 0x0, | |
328 | 0xe5, 0x0, | |
329 | 0xe6, 0x0, | |
330 | 0xe7, 0x0); | |
331 | qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); | |
332 | qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); | |
333 | ||
ed2bc496 | 334 | snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); |
0dbc0798 AG |
335 | qemu_devtree_add_subnode(fdt, pci); |
336 | qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); | |
337 | qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); | |
338 | qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); | |
339 | qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, | |
340 | 0x0, 0x7); | |
347dd79d | 341 | pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), |
492ec48d AG |
342 | params->pci_first_slot, params->pci_nr_slots, |
343 | &len); | |
347dd79d | 344 | qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); |
0dbc0798 | 345 | qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); |
7e99826c | 346 | qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); |
0dbc0798 | 347 | qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); |
3627757e | 348 | for (i = 0; i < 14; i++) { |
0dbc0798 AG |
349 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
350 | } | |
a911b7a9 | 351 | qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
0dbc0798 | 352 | qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); |
3627757e AG |
353 | qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, |
354 | MPC8544_PCI_REGS_BASE, 0, 0x1000); | |
0dbc0798 AG |
355 | qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
356 | qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); | |
357 | qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); | |
358 | qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); | |
359 | qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); | |
360 | ||
e6eaabeb SW |
361 | params->fixup_devtree(params, fdt); |
362 | ||
363 | if (toplevel_compat) { | |
364 | qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, | |
365 | strlen(toplevel_compat) + 1); | |
366 | } | |
367 | ||
d1b93565 | 368 | done: |
71193433 | 369 | qemu_devtree_dumpdtb(fdt, fdt_size); |
04088adb | 370 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
cba2026a AG |
371 | if (ret < 0) { |
372 | goto out; | |
373 | } | |
7267c094 | 374 | g_free(fdt); |
cba2026a | 375 | ret = fdt_size; |
7ec632b4 | 376 | |
1db09b84 | 377 | out: |
347dd79d | 378 | g_free(pci_map); |
1db09b84 | 379 | |
04088adb | 380 | return ret; |
1db09b84 AJ |
381 | } |
382 | ||
cba2026a | 383 | /* Create -kernel TLB entries for BookE. */ |
a8170e5e | 384 | static inline hwaddr booke206_page_size_to_tlb(uint64_t size) |
d1e256fe | 385 | { |
cba2026a | 386 | return 63 - clz64(size >> 10); |
d1e256fe AG |
387 | } |
388 | ||
cba2026a | 389 | static void mmubooke_create_initial_mapping(CPUPPCState *env) |
3b989d49 | 390 | { |
cba2026a | 391 | struct boot_info *bi = env->load_info; |
d1e256fe | 392 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
a8170e5e | 393 | hwaddr size, dt_end; |
cba2026a AG |
394 | int ps; |
395 | ||
396 | /* Our initial TLB entry needs to cover everything from 0 to | |
397 | the device tree top */ | |
398 | dt_end = bi->dt_base + bi->dt_size; | |
399 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
fb37c302 AG |
400 | if (ps & 1) { |
401 | /* e500v2 can only do even TLB size bits */ | |
402 | ps++; | |
403 | } | |
cba2026a | 404 | size = (ps << MAS1_TSIZE_SHIFT); |
d1e256fe | 405 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
406 | tlb->mas2 = 0; |
407 | tlb->mas7_3 = 0; | |
d1e256fe | 408 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
409 | |
410 | env->tlb_dirty = true; | |
3b989d49 AG |
411 | } |
412 | ||
b3305981 | 413 | static void ppce500_cpu_reset_sec(void *opaque) |
5c145dac | 414 | { |
38f92da6 AF |
415 | PowerPCCPU *cpu = opaque; |
416 | CPUPPCState *env = &cpu->env; | |
5c145dac | 417 | |
38f92da6 | 418 | cpu_reset(CPU(cpu)); |
5c145dac AG |
419 | |
420 | /* Secondary CPU starts in halted state for now. Needs to change when | |
421 | implementing non-kernel boot. */ | |
422 | env->halted = 1; | |
423 | env->exception_index = EXCP_HLT; | |
3b989d49 AG |
424 | } |
425 | ||
b3305981 | 426 | static void ppce500_cpu_reset(void *opaque) |
3b989d49 | 427 | { |
38f92da6 AF |
428 | PowerPCCPU *cpu = opaque; |
429 | CPUPPCState *env = &cpu->env; | |
3b989d49 AG |
430 | struct boot_info *bi = env->load_info; |
431 | ||
38f92da6 | 432 | cpu_reset(CPU(cpu)); |
3b989d49 AG |
433 | |
434 | /* Set initial guest state. */ | |
5c145dac | 435 | env->halted = 0; |
3b989d49 AG |
436 | env->gpr[1] = (16<<20) - 8; |
437 | env->gpr[3] = bi->dt_base; | |
438 | env->nip = bi->entry; | |
cba2026a | 439 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
440 | } |
441 | ||
e6eaabeb | 442 | void ppce500_init(PPCE500Params *params) |
1db09b84 | 443 | { |
39186d8a | 444 | MemoryRegion *address_space_mem = get_system_memory(); |
2646c133 | 445 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
1db09b84 | 446 | PCIBus *pci_bus; |
e2684c0b | 447 | CPUPPCState *env = NULL; |
1db09b84 AJ |
448 | uint64_t elf_entry; |
449 | uint64_t elf_lowaddr; | |
a8170e5e AK |
450 | hwaddr entry=0; |
451 | hwaddr loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 452 | target_long kernel_size=0; |
75bb6589 LY |
453 | target_ulong dt_base = 0; |
454 | target_ulong initrd_base = 0; | |
1db09b84 | 455 | target_long initrd_size=0; |
d0b72631 | 456 | int i = 0, j, k; |
1db09b84 | 457 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
a915249f | 458 | qemu_irq **irqs, *mpic; |
be13cc7a | 459 | DeviceState *dev; |
e2684c0b | 460 | CPUPPCState *firstenv = NULL; |
3eddc1be | 461 | MemoryRegion *ccsr_addr_space; |
dffb1dc2 | 462 | SysBusDevice *s; |
3eddc1be | 463 | PPCE500CCSRState *ccsr; |
1db09b84 | 464 | |
e61c36d5 | 465 | /* Setup CPUs */ |
e6eaabeb SW |
466 | if (params->cpu_model == NULL) { |
467 | params->cpu_model = "e500v2_v30"; | |
ef250db6 AG |
468 | } |
469 | ||
a915249f AG |
470 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
471 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 | 472 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 473 | PowerPCCPU *cpu; |
e61c36d5 | 474 | qemu_irq *input; |
397b457d | 475 | |
e6eaabeb | 476 | cpu = cpu_ppc_init(params->cpu_model); |
397b457d | 477 | if (cpu == NULL) { |
e61c36d5 AG |
478 | fprintf(stderr, "Unable to initialize CPU!\n"); |
479 | exit(1); | |
480 | } | |
397b457d | 481 | env = &cpu->env; |
1db09b84 | 482 | |
e61c36d5 AG |
483 | if (!firstenv) { |
484 | firstenv = env; | |
485 | } | |
1db09b84 | 486 | |
a915249f AG |
487 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
488 | input = (qemu_irq *)env->irq_inputs; | |
489 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
490 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
e61c36d5 | 491 | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
dffb1dc2 BB |
492 | env->mpic_cpu_base = MPC8544_CCSRBAR_BASE + |
493 | MPC8544_MPIC_REGS_OFFSET + 0x20000; | |
3b989d49 | 494 | |
ddd1055b | 495 | ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
496 | |
497 | /* Register reset handler */ | |
5c145dac AG |
498 | if (!i) { |
499 | /* Primary CPU */ | |
500 | struct boot_info *boot_info; | |
501 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
b3305981 | 502 | qemu_register_reset(ppce500_cpu_reset, cpu); |
5c145dac AG |
503 | env->load_info = boot_info; |
504 | } else { | |
505 | /* Secondary CPUs */ | |
b3305981 | 506 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
5c145dac | 507 | } |
e61c36d5 | 508 | } |
3b989d49 | 509 | |
e61c36d5 | 510 | env = firstenv; |
3b989d49 | 511 | |
1db09b84 AJ |
512 | /* Fixup Memory size on a alignment boundary */ |
513 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
514 | ||
515 | /* Register Memory */ | |
c5705a77 AK |
516 | memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); |
517 | vmstate_register_ram_global(ram); | |
2646c133 | 518 | memory_region_add_subregion(address_space_mem, 0, ram); |
1db09b84 | 519 | |
3eddc1be BB |
520 | dev = qdev_create(NULL, "e500-ccsr"); |
521 | object_property_add_child(qdev_get_machine(), "e500-ccsr", | |
522 | OBJECT(dev), NULL); | |
523 | qdev_init_nofail(dev); | |
524 | ccsr = CCSR(dev); | |
525 | ccsr_addr_space = &ccsr->ccsr_space; | |
526 | memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, | |
527 | ccsr_addr_space); | |
dffb1dc2 | 528 | |
1db09b84 | 529 | /* MPIC */ |
d0b72631 AG |
530 | mpic = g_new(qemu_irq, 256); |
531 | dev = qdev_create(NULL, "openpic"); | |
532 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); | |
533 | qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20); | |
534 | qdev_init_nofail(dev); | |
535 | s = sysbus_from_qdev(dev); | |
536 | ||
537 | k = 0; | |
538 | for (i = 0; i < smp_cpus; i++) { | |
539 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
540 | sysbus_connect_irq(s, k++, irqs[i][j]); | |
541 | } | |
542 | } | |
a915249f | 543 | |
d0b72631 AG |
544 | for (i = 0; i < 256; i++) { |
545 | mpic[i] = qdev_get_gpio_in(dev, i); | |
a915249f | 546 | } |
1db09b84 | 547 | |
d0b72631 AG |
548 | memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET, |
549 | s->mmio[0].memory); | |
550 | ||
1db09b84 | 551 | /* Serial */ |
2d48377a | 552 | if (serial_hds[0]) { |
3eddc1be | 553 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
cdbb912a | 554 | 0, mpic[42], 399193, |
2ff0c7c3 | 555 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 556 | } |
1db09b84 | 557 | |
2d48377a | 558 | if (serial_hds[1]) { |
3eddc1be | 559 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
cdbb912a | 560 | 0, mpic[42], 399193, |
59de4f98 | 561 | serial_hds[1], DEVICE_BIG_ENDIAN); |
2d48377a | 562 | } |
1db09b84 | 563 | |
b0fb8423 | 564 | /* General Utility device */ |
dffb1dc2 BB |
565 | dev = qdev_create(NULL, "mpc8544-guts"); |
566 | qdev_init_nofail(dev); | |
567 | s = SYS_BUS_DEVICE(dev); | |
3eddc1be | 568 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
dffb1dc2 | 569 | sysbus_mmio_get_region(s, 0)); |
b0fb8423 | 570 | |
1db09b84 | 571 | /* PCI */ |
dffb1dc2 | 572 | dev = qdev_create(NULL, "e500-pcihost"); |
492ec48d | 573 | qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); |
dffb1dc2 BB |
574 | qdev_init_nofail(dev); |
575 | s = SYS_BUS_DEVICE(dev); | |
576 | sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); | |
577 | sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); | |
578 | sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); | |
579 | sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); | |
3eddc1be | 580 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
dffb1dc2 BB |
581 | sysbus_mmio_get_region(s, 0)); |
582 | ||
d461e3b9 | 583 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
584 | if (!pci_bus) |
585 | printf("couldn't create PCI controller!\n"); | |
586 | ||
a1bc20df | 587 | sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO); |
1db09b84 AJ |
588 | |
589 | if (pci_bus) { | |
1db09b84 AJ |
590 | /* Register network interfaces. */ |
591 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 592 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
593 | } |
594 | } | |
595 | ||
5c145dac AG |
596 | /* Register spinning region */ |
597 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
598 | ||
1db09b84 | 599 | /* Load kernel. */ |
e6eaabeb SW |
600 | if (params->kernel_filename) { |
601 | kernel_size = load_uimage(params->kernel_filename, &entry, | |
602 | &loadaddr, NULL); | |
1db09b84 | 603 | if (kernel_size < 0) { |
e6eaabeb SW |
604 | kernel_size = load_elf(params->kernel_filename, NULL, NULL, |
605 | &elf_entry, &elf_lowaddr, NULL, 1, | |
606 | ELF_MACHINE, 0); | |
1db09b84 AJ |
607 | entry = elf_entry; |
608 | loadaddr = elf_lowaddr; | |
609 | } | |
610 | /* XXX try again as binary */ | |
611 | if (kernel_size < 0) { | |
612 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
e6eaabeb | 613 | params->kernel_filename); |
1db09b84 AJ |
614 | exit(1); |
615 | } | |
616 | } | |
617 | ||
618 | /* Load initrd. */ | |
e6eaabeb | 619 | if (params->initrd_filename) { |
7e7ec2d2 SW |
620 | initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) & |
621 | ~INITRD_PAD_MASK; | |
e6eaabeb | 622 | initrd_size = load_image_targphys(params->initrd_filename, initrd_base, |
d7585251 | 623 | ram_size - initrd_base); |
1db09b84 AJ |
624 | |
625 | if (initrd_size < 0) { | |
626 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
e6eaabeb | 627 | params->initrd_filename); |
1db09b84 AJ |
628 | exit(1); |
629 | } | |
630 | } | |
631 | ||
632 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
e6eaabeb | 633 | if (params->kernel_filename) { |
5c145dac | 634 | struct boot_info *boot_info; |
cba2026a | 635 | int dt_size; |
5c145dac | 636 | |
cba2026a | 637 | dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
e6eaabeb SW |
638 | dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, |
639 | initrd_size); | |
cba2026a | 640 | if (dt_size < 0) { |
1db09b84 AJ |
641 | fprintf(stderr, "couldn't load device tree\n"); |
642 | exit(1); | |
643 | } | |
644 | ||
e61c36d5 | 645 | boot_info = env->load_info; |
3b989d49 AG |
646 | boot_info->entry = entry; |
647 | boot_info->dt_base = dt_base; | |
cba2026a | 648 | boot_info->dt_size = dt_size; |
1db09b84 AJ |
649 | } |
650 | ||
3b989d49 | 651 | if (kvm_enabled()) { |
1db09b84 | 652 | kvmppc_init(); |
3b989d49 | 653 | } |
1db09b84 | 654 | } |
3eddc1be BB |
655 | |
656 | static int e500_ccsr_initfn(SysBusDevice *dev) | |
657 | { | |
658 | PPCE500CCSRState *ccsr; | |
659 | ||
660 | ccsr = CCSR(dev); | |
661 | memory_region_init(&ccsr->ccsr_space, "e500-ccsr", | |
662 | MPC8544_CCSRBAR_SIZE); | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static void e500_ccsr_class_init(ObjectClass *klass, void *data) | |
667 | { | |
668 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
669 | k->init = e500_ccsr_initfn; | |
670 | } | |
671 | ||
672 | static const TypeInfo e500_ccsr_info = { | |
673 | .name = TYPE_CCSR, | |
674 | .parent = TYPE_SYS_BUS_DEVICE, | |
675 | .instance_size = sizeof(PPCE500CCSRState), | |
676 | .class_init = e500_ccsr_class_init, | |
677 | }; | |
678 | ||
679 | static void e500_register_types(void) | |
680 | { | |
681 | type_register_static(&e500_ccsr_info); | |
682 | } | |
683 | ||
684 | type_init(e500_register_types) |