]>
Commit | Line | Data |
---|---|---|
1db09b84 | 1 | /* |
b3305981 | 2 | * QEMU PowerPC e500-based platforms |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
e6eaabeb | 19 | #include "e500.h" |
3eddc1be | 20 | #include "e500-ccsr.h" |
1db09b84 | 21 | #include "net.h" |
4a18e7c9 | 22 | #include "hw/hw.h" |
488cb996 | 23 | #include "hw/serial.h" |
4a18e7c9 SW |
24 | #include "hw/pci.h" |
25 | #include "hw/boards.h" | |
1db09b84 AJ |
26 | #include "sysemu.h" |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "device_tree.h" | |
4a18e7c9 SW |
30 | #include "hw/openpic.h" |
31 | #include "hw/ppc.h" | |
32 | #include "hw/loader.h" | |
ca20cf32 | 33 | #include "elf.h" |
4a18e7c9 | 34 | #include "hw/sysbus.h" |
39186d8a | 35 | #include "exec-memory.h" |
cba2026a | 36 | #include "host-utils.h" |
9e2c1298 | 37 | #include "hw/ppce500_pci.h" |
1db09b84 AJ |
38 | |
39 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
40 | #define UIMAGE_LOAD_BASE 0 | |
9dd5eba1 | 41 | #define DTC_LOAD_PAD 0x1800000 |
75bb6589 LY |
42 | #define DTC_PAD_MASK 0xFFFFF |
43 | #define INITRD_LOAD_PAD 0x2000000 | |
44 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
45 | |
46 | #define RAM_SIZES_ALIGN (64UL << 20) | |
47 | ||
b3305981 | 48 | /* TODO: parameterize */ |
ed2bc496 AG |
49 | #define MPC8544_CCSRBAR_BASE 0xE0000000ULL |
50 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL | |
dffb1dc2 | 51 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
a911b7a9 | 52 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
dffb1dc2 BB |
53 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
54 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL | |
55 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL | |
56 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ | |
57 | MPC8544_PCI_REGS_OFFSET) | |
ed2bc496 AG |
58 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
59 | #define MPC8544_PCI_IO 0xE1000000ULL | |
dffb1dc2 | 60 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
ed2bc496 | 61 | #define MPC8544_SPIN_BASE 0xEF000000ULL |
1db09b84 | 62 | |
3b989d49 AG |
63 | struct boot_info |
64 | { | |
65 | uint32_t dt_base; | |
cba2026a | 66 | uint32_t dt_size; |
3b989d49 AG |
67 | uint32_t entry; |
68 | }; | |
69 | ||
347dd79d AG |
70 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
71 | int nr_slots, int *len) | |
0dbc0798 | 72 | { |
347dd79d AG |
73 | int i = 0; |
74 | int slot; | |
75 | int pci_irq; | |
9e2c1298 | 76 | int host_irq; |
347dd79d AG |
77 | int last_slot = first_slot + nr_slots; |
78 | uint32_t *pci_map; | |
79 | ||
80 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); | |
81 | pci_map = g_malloc(*len); | |
82 | ||
83 | for (slot = first_slot; slot < last_slot; slot++) { | |
84 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { | |
85 | pci_map[i++] = cpu_to_be32(slot << 11); | |
86 | pci_map[i++] = cpu_to_be32(0x0); | |
87 | pci_map[i++] = cpu_to_be32(0x0); | |
88 | pci_map[i++] = cpu_to_be32(pci_irq + 1); | |
89 | pci_map[i++] = cpu_to_be32(mpic); | |
9e2c1298 AG |
90 | host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
91 | pci_map[i++] = cpu_to_be32(host_irq + 1); | |
347dd79d AG |
92 | pci_map[i++] = cpu_to_be32(0x1); |
93 | } | |
0dbc0798 | 94 | } |
347dd79d AG |
95 | |
96 | assert((i * sizeof(uint32_t)) == *len); | |
97 | ||
98 | return pci_map; | |
0dbc0798 AG |
99 | } |
100 | ||
a053a7ce AG |
101 | static void dt_serial_create(void *fdt, unsigned long long offset, |
102 | const char *soc, const char *mpic, | |
103 | const char *alias, int idx, bool defcon) | |
104 | { | |
105 | char ser[128]; | |
106 | ||
107 | snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); | |
108 | qemu_devtree_add_subnode(fdt, ser); | |
109 | qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); | |
110 | qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); | |
111 | qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); | |
112 | qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); | |
113 | qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); | |
7e99826c | 114 | qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); |
a053a7ce AG |
115 | qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); |
116 | qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); | |
117 | ||
118 | if (defcon) { | |
119 | qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); | |
120 | } | |
121 | } | |
122 | ||
b3305981 | 123 | static int ppce500_load_device_tree(CPUPPCState *env, |
e6eaabeb | 124 | PPCE500Params *params, |
a8170e5e AK |
125 | hwaddr addr, |
126 | hwaddr initrd_base, | |
127 | hwaddr initrd_size) | |
1db09b84 | 128 | { |
dbf916d8 | 129 | int ret = -1; |
e6eaabeb | 130 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; |
7ec632b4 | 131 | int fdt_size; |
dbf916d8 | 132 | void *fdt; |
5de6b46d | 133 | uint8_t hypercall[16]; |
911d6e7a AG |
134 | uint32_t clock_freq = 400000000; |
135 | uint32_t tb_freq = 400000000; | |
621d05e3 | 136 | int i; |
e6eaabeb | 137 | const char *toplevel_compat = NULL; /* user override */ |
ebb9518a | 138 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
5da96624 | 139 | char soc[128]; |
19ac9dea AG |
140 | char mpic[128]; |
141 | uint32_t mpic_ph; | |
a911b7a9 | 142 | uint32_t msi_ph; |
f5038483 | 143 | char gutil[128]; |
0dbc0798 | 144 | char pci[128]; |
a911b7a9 | 145 | char msi[128]; |
347dd79d AG |
146 | uint32_t *pci_map = NULL; |
147 | int len; | |
3627757e AG |
148 | uint32_t pci_ranges[14] = |
149 | { | |
150 | 0x2000000, 0x0, 0xc0000000, | |
151 | 0x0, 0xc0000000, | |
152 | 0x0, 0x20000000, | |
153 | ||
154 | 0x1000000, 0x0, 0x0, | |
155 | 0x0, 0xe1000000, | |
156 | 0x0, 0x10000, | |
157 | }; | |
25b42708 | 158 | QemuOpts *machine_opts; |
d1b93565 AG |
159 | const char *dtb_file = NULL; |
160 | ||
161 | machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); | |
162 | if (machine_opts) { | |
d1b93565 | 163 | dtb_file = qemu_opt_get(machine_opts, "dtb"); |
e6eaabeb | 164 | toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); |
d1b93565 AG |
165 | } |
166 | ||
167 | if (dtb_file) { | |
168 | char *filename; | |
169 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); | |
170 | if (!filename) { | |
171 | goto out; | |
172 | } | |
173 | ||
174 | fdt = load_device_tree(filename, &fdt_size); | |
175 | if (!fdt) { | |
176 | goto out; | |
177 | } | |
178 | goto done; | |
179 | } | |
1db09b84 | 180 | |
2636fcb6 | 181 | fdt = create_device_tree(&fdt_size); |
5cea8590 PB |
182 | if (fdt == NULL) { |
183 | goto out; | |
184 | } | |
1db09b84 AJ |
185 | |
186 | /* Manipulate device tree in memory. */ | |
3627757e AG |
187 | qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); |
188 | qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); | |
51b852b7 | 189 | |
dd0bcfca AG |
190 | qemu_devtree_add_subnode(fdt, "/memory"); |
191 | qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); | |
192 | qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
193 | sizeof(mem_reg_property)); | |
1db09b84 | 194 | |
f5231aaf | 195 | qemu_devtree_add_subnode(fdt, "/chosen"); |
3b989d49 AG |
196 | if (initrd_size) { |
197 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
198 | initrd_base); | |
199 | if (ret < 0) { | |
200 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
201 | } | |
1db09b84 | 202 | |
3b989d49 AG |
203 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
204 | (initrd_base + initrd_size)); | |
205 | if (ret < 0) { | |
206 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
207 | } | |
208 | } | |
1db09b84 AJ |
209 | |
210 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
e6eaabeb | 211 | params->kernel_cmdline); |
1db09b84 AJ |
212 | if (ret < 0) |
213 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
214 | ||
215 | if (kvm_enabled()) { | |
911d6e7a AG |
216 | /* Read out host's frequencies */ |
217 | clock_freq = kvmppc_get_clockfreq(); | |
218 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
219 | |
220 | /* indicate KVM hypercall interface */ | |
d50f71a5 | 221 | qemu_devtree_add_subnode(fdt, "/hypervisor"); |
5de6b46d AG |
222 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
223 | "linux,kvm"); | |
224 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
225 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
226 | hypercall, sizeof(hypercall)); | |
1db09b84 | 227 | } |
3b989d49 | 228 | |
625e665b AG |
229 | /* Create CPU nodes */ |
230 | qemu_devtree_add_subnode(fdt, "/cpus"); | |
231 | qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
232 | qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
233 | ||
1e3debf0 AG |
234 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
235 | the first node as boot node and be happy */ | |
236 | for (i = smp_cpus - 1; i >= 0; i--) { | |
621d05e3 | 237 | char cpu_name[128]; |
1d2e5c52 | 238 | uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); |
10f25a46 | 239 | |
1e3debf0 AG |
240 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
241 | if (env->cpu_index == i) { | |
242 | break; | |
243 | } | |
244 | } | |
245 | ||
246 | if (!env) { | |
247 | continue; | |
248 | } | |
249 | ||
250 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); | |
251 | qemu_devtree_add_subnode(fdt, cpu_name); | |
621d05e3 AG |
252 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
253 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 AG |
254 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
255 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); | |
256 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", | |
257 | env->dcache_line_size); | |
258 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
259 | env->icache_line_size); | |
260 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
261 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
262 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
263 | if (env->cpu_index) { | |
264 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); | |
265 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
1d2e5c52 AG |
266 | qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", |
267 | cpu_release_addr); | |
1e3debf0 AG |
268 | } else { |
269 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
270 | } | |
1db09b84 AJ |
271 | } |
272 | ||
0cfc6e8d | 273 | qemu_devtree_add_subnode(fdt, "/aliases"); |
5da96624 | 274 | /* XXX These should go into their respective devices' code */ |
ed2bc496 | 275 | snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); |
5da96624 AG |
276 | qemu_devtree_add_subnode(fdt, soc); |
277 | qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); | |
ebb9518a AG |
278 | qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, |
279 | sizeof(compatible_sb)); | |
5da96624 AG |
280 | qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); |
281 | qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); | |
3627757e AG |
282 | qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, |
283 | MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, | |
5da96624 | 284 | MPC8544_CCSRBAR_SIZE); |
5da96624 AG |
285 | /* XXX should contain a reasonable value */ |
286 | qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); | |
287 | ||
dffb1dc2 | 288 | snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
19ac9dea AG |
289 | qemu_devtree_add_subnode(fdt, mpic); |
290 | qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); | |
7e99826c | 291 | qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic"); |
dffb1dc2 BB |
292 | qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, |
293 | 0x40000); | |
19ac9dea | 294 | qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); |
7e99826c | 295 | qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); |
19ac9dea AG |
296 | mpic_ph = qemu_devtree_alloc_phandle(fdt); |
297 | qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); | |
298 | qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); | |
299 | qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); | |
300 | ||
0cfc6e8d AG |
301 | /* |
302 | * We have to generate ser1 first, because Linux takes the first | |
303 | * device it finds in the dt as serial output device. And we generate | |
304 | * devices in reverse order to the dt. | |
305 | */ | |
dffb1dc2 | 306 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
a053a7ce | 307 | soc, mpic, "serial1", 1, false); |
dffb1dc2 | 308 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
a053a7ce | 309 | soc, mpic, "serial0", 0, true); |
0cfc6e8d | 310 | |
ed2bc496 | 311 | snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, |
dffb1dc2 | 312 | MPC8544_UTIL_OFFSET); |
f5038483 AG |
313 | qemu_devtree_add_subnode(fdt, gutil); |
314 | qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); | |
dffb1dc2 | 315 | qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); |
f5038483 AG |
316 | qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); |
317 | ||
a911b7a9 AG |
318 | snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
319 | qemu_devtree_add_subnode(fdt, msi); | |
320 | qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); | |
321 | qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); | |
322 | msi_ph = qemu_devtree_alloc_phandle(fdt); | |
323 | qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); | |
324 | qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); | |
325 | qemu_devtree_setprop_cells(fdt, msi, "interrupts", | |
326 | 0xe0, 0x0, | |
327 | 0xe1, 0x0, | |
328 | 0xe2, 0x0, | |
329 | 0xe3, 0x0, | |
330 | 0xe4, 0x0, | |
331 | 0xe5, 0x0, | |
332 | 0xe6, 0x0, | |
333 | 0xe7, 0x0); | |
334 | qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); | |
335 | qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); | |
336 | ||
ed2bc496 | 337 | snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); |
0dbc0798 AG |
338 | qemu_devtree_add_subnode(fdt, pci); |
339 | qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); | |
340 | qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); | |
341 | qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); | |
342 | qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, | |
343 | 0x0, 0x7); | |
347dd79d | 344 | pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), |
492ec48d AG |
345 | params->pci_first_slot, params->pci_nr_slots, |
346 | &len); | |
347dd79d | 347 | qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); |
0dbc0798 | 348 | qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); |
7e99826c | 349 | qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); |
0dbc0798 | 350 | qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); |
3627757e | 351 | for (i = 0; i < 14; i++) { |
0dbc0798 AG |
352 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
353 | } | |
a911b7a9 | 354 | qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
0dbc0798 | 355 | qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); |
3627757e AG |
356 | qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, |
357 | MPC8544_PCI_REGS_BASE, 0, 0x1000); | |
0dbc0798 AG |
358 | qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
359 | qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); | |
360 | qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); | |
361 | qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); | |
362 | qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); | |
363 | ||
e6eaabeb SW |
364 | params->fixup_devtree(params, fdt); |
365 | ||
366 | if (toplevel_compat) { | |
367 | qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, | |
368 | strlen(toplevel_compat) + 1); | |
369 | } | |
370 | ||
d1b93565 | 371 | done: |
71193433 | 372 | qemu_devtree_dumpdtb(fdt, fdt_size); |
04088adb | 373 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
cba2026a AG |
374 | if (ret < 0) { |
375 | goto out; | |
376 | } | |
7267c094 | 377 | g_free(fdt); |
cba2026a | 378 | ret = fdt_size; |
7ec632b4 | 379 | |
1db09b84 | 380 | out: |
347dd79d | 381 | g_free(pci_map); |
1db09b84 | 382 | |
04088adb | 383 | return ret; |
1db09b84 AJ |
384 | } |
385 | ||
cba2026a | 386 | /* Create -kernel TLB entries for BookE. */ |
a8170e5e | 387 | static inline hwaddr booke206_page_size_to_tlb(uint64_t size) |
d1e256fe | 388 | { |
cba2026a | 389 | return 63 - clz64(size >> 10); |
d1e256fe AG |
390 | } |
391 | ||
cba2026a | 392 | static void mmubooke_create_initial_mapping(CPUPPCState *env) |
3b989d49 | 393 | { |
cba2026a | 394 | struct boot_info *bi = env->load_info; |
d1e256fe | 395 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
a8170e5e | 396 | hwaddr size, dt_end; |
cba2026a AG |
397 | int ps; |
398 | ||
399 | /* Our initial TLB entry needs to cover everything from 0 to | |
400 | the device tree top */ | |
401 | dt_end = bi->dt_base + bi->dt_size; | |
402 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
fb37c302 AG |
403 | if (ps & 1) { |
404 | /* e500v2 can only do even TLB size bits */ | |
405 | ps++; | |
406 | } | |
cba2026a | 407 | size = (ps << MAS1_TSIZE_SHIFT); |
d1e256fe | 408 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
409 | tlb->mas2 = 0; |
410 | tlb->mas7_3 = 0; | |
d1e256fe | 411 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
412 | |
413 | env->tlb_dirty = true; | |
3b989d49 AG |
414 | } |
415 | ||
b3305981 | 416 | static void ppce500_cpu_reset_sec(void *opaque) |
5c145dac | 417 | { |
38f92da6 AF |
418 | PowerPCCPU *cpu = opaque; |
419 | CPUPPCState *env = &cpu->env; | |
5c145dac | 420 | |
38f92da6 | 421 | cpu_reset(CPU(cpu)); |
5c145dac AG |
422 | |
423 | /* Secondary CPU starts in halted state for now. Needs to change when | |
424 | implementing non-kernel boot. */ | |
425 | env->halted = 1; | |
426 | env->exception_index = EXCP_HLT; | |
3b989d49 AG |
427 | } |
428 | ||
b3305981 | 429 | static void ppce500_cpu_reset(void *opaque) |
3b989d49 | 430 | { |
38f92da6 AF |
431 | PowerPCCPU *cpu = opaque; |
432 | CPUPPCState *env = &cpu->env; | |
3b989d49 AG |
433 | struct boot_info *bi = env->load_info; |
434 | ||
38f92da6 | 435 | cpu_reset(CPU(cpu)); |
3b989d49 AG |
436 | |
437 | /* Set initial guest state. */ | |
5c145dac | 438 | env->halted = 0; |
3b989d49 AG |
439 | env->gpr[1] = (16<<20) - 8; |
440 | env->gpr[3] = bi->dt_base; | |
441 | env->nip = bi->entry; | |
cba2026a | 442 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
443 | } |
444 | ||
e6eaabeb | 445 | void ppce500_init(PPCE500Params *params) |
1db09b84 | 446 | { |
39186d8a | 447 | MemoryRegion *address_space_mem = get_system_memory(); |
2646c133 | 448 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
1db09b84 | 449 | PCIBus *pci_bus; |
e2684c0b | 450 | CPUPPCState *env = NULL; |
1db09b84 AJ |
451 | uint64_t elf_entry; |
452 | uint64_t elf_lowaddr; | |
a8170e5e AK |
453 | hwaddr entry=0; |
454 | hwaddr loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 455 | target_long kernel_size=0; |
75bb6589 LY |
456 | target_ulong dt_base = 0; |
457 | target_ulong initrd_base = 0; | |
1db09b84 | 458 | target_long initrd_size=0; |
d0b72631 | 459 | int i = 0, j, k; |
1db09b84 | 460 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
a915249f | 461 | qemu_irq **irqs, *mpic; |
be13cc7a | 462 | DeviceState *dev; |
e2684c0b | 463 | CPUPPCState *firstenv = NULL; |
3eddc1be | 464 | MemoryRegion *ccsr_addr_space; |
dffb1dc2 | 465 | SysBusDevice *s; |
3eddc1be | 466 | PPCE500CCSRState *ccsr; |
1db09b84 | 467 | |
e61c36d5 | 468 | /* Setup CPUs */ |
e6eaabeb SW |
469 | if (params->cpu_model == NULL) { |
470 | params->cpu_model = "e500v2_v30"; | |
ef250db6 AG |
471 | } |
472 | ||
a915249f AG |
473 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
474 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 | 475 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 476 | PowerPCCPU *cpu; |
e61c36d5 | 477 | qemu_irq *input; |
397b457d | 478 | |
e6eaabeb | 479 | cpu = cpu_ppc_init(params->cpu_model); |
397b457d | 480 | if (cpu == NULL) { |
e61c36d5 AG |
481 | fprintf(stderr, "Unable to initialize CPU!\n"); |
482 | exit(1); | |
483 | } | |
397b457d | 484 | env = &cpu->env; |
1db09b84 | 485 | |
e61c36d5 AG |
486 | if (!firstenv) { |
487 | firstenv = env; | |
488 | } | |
1db09b84 | 489 | |
a915249f AG |
490 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
491 | input = (qemu_irq *)env->irq_inputs; | |
492 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
493 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
e61c36d5 | 494 | env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; |
dffb1dc2 BB |
495 | env->mpic_cpu_base = MPC8544_CCSRBAR_BASE + |
496 | MPC8544_MPIC_REGS_OFFSET + 0x20000; | |
3b989d49 | 497 | |
ddd1055b | 498 | ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
499 | |
500 | /* Register reset handler */ | |
5c145dac AG |
501 | if (!i) { |
502 | /* Primary CPU */ | |
503 | struct boot_info *boot_info; | |
504 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
b3305981 | 505 | qemu_register_reset(ppce500_cpu_reset, cpu); |
5c145dac AG |
506 | env->load_info = boot_info; |
507 | } else { | |
508 | /* Secondary CPUs */ | |
b3305981 | 509 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
5c145dac | 510 | } |
e61c36d5 | 511 | } |
3b989d49 | 512 | |
e61c36d5 | 513 | env = firstenv; |
3b989d49 | 514 | |
1db09b84 AJ |
515 | /* Fixup Memory size on a alignment boundary */ |
516 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
517 | ||
518 | /* Register Memory */ | |
c5705a77 AK |
519 | memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); |
520 | vmstate_register_ram_global(ram); | |
2646c133 | 521 | memory_region_add_subregion(address_space_mem, 0, ram); |
1db09b84 | 522 | |
3eddc1be BB |
523 | dev = qdev_create(NULL, "e500-ccsr"); |
524 | object_property_add_child(qdev_get_machine(), "e500-ccsr", | |
525 | OBJECT(dev), NULL); | |
526 | qdev_init_nofail(dev); | |
527 | ccsr = CCSR(dev); | |
528 | ccsr_addr_space = &ccsr->ccsr_space; | |
529 | memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, | |
530 | ccsr_addr_space); | |
dffb1dc2 | 531 | |
1db09b84 | 532 | /* MPIC */ |
d0b72631 AG |
533 | mpic = g_new(qemu_irq, 256); |
534 | dev = qdev_create(NULL, "openpic"); | |
535 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); | |
536 | qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20); | |
537 | qdev_init_nofail(dev); | |
538 | s = sysbus_from_qdev(dev); | |
539 | ||
540 | k = 0; | |
541 | for (i = 0; i < smp_cpus; i++) { | |
542 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
543 | sysbus_connect_irq(s, k++, irqs[i][j]); | |
544 | } | |
545 | } | |
a915249f | 546 | |
d0b72631 AG |
547 | for (i = 0; i < 256; i++) { |
548 | mpic[i] = qdev_get_gpio_in(dev, i); | |
a915249f | 549 | } |
1db09b84 | 550 | |
d0b72631 AG |
551 | memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET, |
552 | s->mmio[0].memory); | |
553 | ||
1db09b84 | 554 | /* Serial */ |
2d48377a | 555 | if (serial_hds[0]) { |
3eddc1be | 556 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
cdbb912a | 557 | 0, mpic[42], 399193, |
2ff0c7c3 | 558 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 559 | } |
1db09b84 | 560 | |
2d48377a | 561 | if (serial_hds[1]) { |
3eddc1be | 562 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
cdbb912a | 563 | 0, mpic[42], 399193, |
59de4f98 | 564 | serial_hds[1], DEVICE_BIG_ENDIAN); |
2d48377a | 565 | } |
1db09b84 | 566 | |
b0fb8423 | 567 | /* General Utility device */ |
dffb1dc2 BB |
568 | dev = qdev_create(NULL, "mpc8544-guts"); |
569 | qdev_init_nofail(dev); | |
570 | s = SYS_BUS_DEVICE(dev); | |
3eddc1be | 571 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
dffb1dc2 | 572 | sysbus_mmio_get_region(s, 0)); |
b0fb8423 | 573 | |
1db09b84 | 574 | /* PCI */ |
dffb1dc2 | 575 | dev = qdev_create(NULL, "e500-pcihost"); |
492ec48d | 576 | qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); |
dffb1dc2 BB |
577 | qdev_init_nofail(dev); |
578 | s = SYS_BUS_DEVICE(dev); | |
579 | sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); | |
580 | sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); | |
581 | sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); | |
582 | sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); | |
3eddc1be | 583 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
dffb1dc2 BB |
584 | sysbus_mmio_get_region(s, 0)); |
585 | ||
d461e3b9 | 586 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
587 | if (!pci_bus) |
588 | printf("couldn't create PCI controller!\n"); | |
589 | ||
a1bc20df | 590 | sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO); |
1db09b84 AJ |
591 | |
592 | if (pci_bus) { | |
1db09b84 AJ |
593 | /* Register network interfaces. */ |
594 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 595 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
596 | } |
597 | } | |
598 | ||
5c145dac AG |
599 | /* Register spinning region */ |
600 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
601 | ||
1db09b84 | 602 | /* Load kernel. */ |
e6eaabeb SW |
603 | if (params->kernel_filename) { |
604 | kernel_size = load_uimage(params->kernel_filename, &entry, | |
605 | &loadaddr, NULL); | |
1db09b84 | 606 | if (kernel_size < 0) { |
e6eaabeb SW |
607 | kernel_size = load_elf(params->kernel_filename, NULL, NULL, |
608 | &elf_entry, &elf_lowaddr, NULL, 1, | |
609 | ELF_MACHINE, 0); | |
1db09b84 AJ |
610 | entry = elf_entry; |
611 | loadaddr = elf_lowaddr; | |
612 | } | |
613 | /* XXX try again as binary */ | |
614 | if (kernel_size < 0) { | |
615 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
e6eaabeb | 616 | params->kernel_filename); |
1db09b84 AJ |
617 | exit(1); |
618 | } | |
619 | } | |
620 | ||
621 | /* Load initrd. */ | |
e6eaabeb | 622 | if (params->initrd_filename) { |
7e7ec2d2 SW |
623 | initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) & |
624 | ~INITRD_PAD_MASK; | |
e6eaabeb | 625 | initrd_size = load_image_targphys(params->initrd_filename, initrd_base, |
d7585251 | 626 | ram_size - initrd_base); |
1db09b84 AJ |
627 | |
628 | if (initrd_size < 0) { | |
629 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
e6eaabeb | 630 | params->initrd_filename); |
1db09b84 AJ |
631 | exit(1); |
632 | } | |
633 | } | |
634 | ||
635 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
e6eaabeb | 636 | if (params->kernel_filename) { |
5c145dac | 637 | struct boot_info *boot_info; |
cba2026a | 638 | int dt_size; |
5c145dac | 639 | |
cba2026a | 640 | dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
e6eaabeb SW |
641 | dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, |
642 | initrd_size); | |
cba2026a | 643 | if (dt_size < 0) { |
1db09b84 AJ |
644 | fprintf(stderr, "couldn't load device tree\n"); |
645 | exit(1); | |
646 | } | |
647 | ||
e61c36d5 | 648 | boot_info = env->load_info; |
3b989d49 AG |
649 | boot_info->entry = entry; |
650 | boot_info->dt_base = dt_base; | |
cba2026a | 651 | boot_info->dt_size = dt_size; |
1db09b84 AJ |
652 | } |
653 | ||
3b989d49 | 654 | if (kvm_enabled()) { |
1db09b84 | 655 | kvmppc_init(); |
3b989d49 | 656 | } |
1db09b84 | 657 | } |
3eddc1be BB |
658 | |
659 | static int e500_ccsr_initfn(SysBusDevice *dev) | |
660 | { | |
661 | PPCE500CCSRState *ccsr; | |
662 | ||
663 | ccsr = CCSR(dev); | |
664 | memory_region_init(&ccsr->ccsr_space, "e500-ccsr", | |
665 | MPC8544_CCSRBAR_SIZE); | |
666 | return 0; | |
667 | } | |
668 | ||
669 | static void e500_ccsr_class_init(ObjectClass *klass, void *data) | |
670 | { | |
671 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
672 | k->init = e500_ccsr_initfn; | |
673 | } | |
674 | ||
675 | static const TypeInfo e500_ccsr_info = { | |
676 | .name = TYPE_CCSR, | |
677 | .parent = TYPE_SYS_BUS_DEVICE, | |
678 | .instance_size = sizeof(PPCE500CCSRState), | |
679 | .class_init = e500_ccsr_class_init, | |
680 | }; | |
681 | ||
682 | static void e500_register_types(void) | |
683 | { | |
684 | type_register_static(&e500_ccsr_info); | |
685 | } | |
686 | ||
687 | type_init(e500_register_types) |