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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
9fdf0c29 | 25 | */ |
a8d25326 | 26 | |
0d75590d | 27 | #include "qemu/osdep.h" |
a8d25326 | 28 | #include "qemu-common.h" |
da34e65c | 29 | #include "qapi/error.h" |
fa98fbfc | 30 | #include "qapi/visitor.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
b58c5c2d | 32 | #include "sysemu/hostmem.h" |
e35704ba | 33 | #include "sysemu/numa.h" |
23ff81bd | 34 | #include "sysemu/qtest.h" |
71e8a915 | 35 | #include "sysemu/reset.h" |
54d31236 | 36 | #include "sysemu/runstate.h" |
03dd024f | 37 | #include "qemu/log.h" |
71461b0f | 38 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 39 | #include "elf.h" |
1422e32d | 40 | #include "net/net.h" |
ad440b4a | 41 | #include "sysemu/device_tree.h" |
9c17d615 | 42 | #include "sysemu/cpus.h" |
b3946626 | 43 | #include "sysemu/hw_accel.h" |
e97c3636 | 44 | #include "kvm_ppc.h" |
c4b63b7c | 45 | #include "migration/misc.h" |
ca77ee28 | 46 | #include "migration/qemu-file-types.h" |
84a899de | 47 | #include "migration/global_state.h" |
f2a8f0a6 | 48 | #include "migration/register.h" |
2500fb42 | 49 | #include "migration/blocker.h" |
4be21d56 | 50 | #include "mmu-hash64.h" |
b4db5413 | 51 | #include "mmu-book3s-v3.h" |
7abd43ba | 52 | #include "cpu-models.h" |
2e5b09fd | 53 | #include "hw/core/cpu.h" |
9fdf0c29 DG |
54 | |
55 | #include "hw/boards.h" | |
0d09e41a | 56 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
57 | #include "hw/loader.h" |
58 | ||
7804c353 | 59 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
60 | #include "hw/ppc/spapr.h" |
61 | #include "hw/ppc/spapr_vio.h" | |
a27bd6c7 | 62 | #include "hw/qdev-properties.h" |
0d09e41a | 63 | #include "hw/pci-host/spapr.h" |
a2cb15b0 | 64 | #include "hw/pci/msi.h" |
9fdf0c29 | 65 | |
83c9f4ca | 66 | #include "hw/pci/pci.h" |
71461b0f AK |
67 | #include "hw/scsi/scsi.h" |
68 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 69 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 70 | |
022c62cb | 71 | #include "exec/address-spaces.h" |
2309832a | 72 | #include "exec/ram_addr.h" |
35139a59 | 73 | #include "hw/usb.h" |
1de7afc9 | 74 | #include "qemu/config-file.h" |
135a129a | 75 | #include "qemu/error-report.h" |
2a6593cb | 76 | #include "trace.h" |
34316482 | 77 | #include "hw/nmi.h" |
6449da45 | 78 | #include "hw/intc/intc.h" |
890c2b77 | 79 | |
94a94e4c | 80 | #include "hw/ppc/spapr_cpu_core.h" |
2cc0e2e8 | 81 | #include "hw/mem/memory-device.h" |
0fb6bd07 | 82 | #include "hw/ppc/spapr_tpm_proxy.h" |
ee3a71e3 | 83 | #include "hw/ppc/spapr_nvdimm.h" |
68a27b20 | 84 | |
f041d6af GK |
85 | #include "monitor/monitor.h" |
86 | ||
9fdf0c29 DG |
87 | #include <libfdt.h> |
88 | ||
4d8d5467 BH |
89 | /* SLOF memory layout: |
90 | * | |
91 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
92 | * device-tree, then position SLOF itself 31M below that | |
93 | * | |
94 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
95 | * and more | |
96 | * | |
97 | * We load our kernel at 4M, leaving space for SLOF initial image | |
98 | */ | |
b7d1f77a | 99 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
100 | #define FW_MAX_SIZE 0x400000 |
101 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
102 | #define FW_OVERHEAD 0x2800000 |
103 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 104 | |
9943266e | 105 | #define MIN_RMA_SLOF (128 * MiB) |
9fdf0c29 | 106 | |
5c7adcf4 | 107 | #define PHANDLE_INTC 0x00001111 |
0c103f8e | 108 | |
5d0fb150 GK |
109 | /* These two functions implement the VCPU id numbering: one to compute them |
110 | * all and one to identify thread 0 of a VCORE. Any change to the first one | |
111 | * is likely to have an impact on the second one, so let's keep them close. | |
112 | */ | |
ce2918cb | 113 | static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) |
5d0fb150 | 114 | { |
fe6b6346 LX |
115 | MachineState *ms = MACHINE(spapr); |
116 | unsigned int smp_threads = ms->smp.threads; | |
117 | ||
1a5008fc | 118 | assert(spapr->vsmt); |
5d0fb150 GK |
119 | return |
120 | (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; | |
121 | } | |
ce2918cb | 122 | static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, |
5d0fb150 GK |
123 | PowerPCCPU *cpu) |
124 | { | |
1a5008fc | 125 | assert(spapr->vsmt); |
5d0fb150 GK |
126 | return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; |
127 | } | |
128 | ||
46f7afa3 GK |
129 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
130 | { | |
131 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
132 | * and newer QEMUs don't even have them. In both cases, we don't want | |
133 | * to send anything on the wire. | |
134 | */ | |
135 | return false; | |
136 | } | |
137 | ||
138 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
139 | .name = "icp/server", | |
140 | .version_id = 1, | |
141 | .minimum_version_id = 1, | |
142 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
143 | .fields = (VMStateField[]) { | |
144 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
145 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
146 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
147 | VMSTATE_END_OF_LIST() | |
148 | }, | |
149 | }; | |
150 | ||
151 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
152 | { | |
153 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
154 | (void *)(uintptr_t) i); | |
155 | } | |
156 | ||
157 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
158 | { | |
159 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
160 | (void *)(uintptr_t) i); | |
161 | } | |
162 | ||
ce2918cb | 163 | int spapr_max_server_number(SpaprMachineState *spapr) |
46f7afa3 | 164 | { |
fe6b6346 LX |
165 | MachineState *ms = MACHINE(spapr); |
166 | ||
1a5008fc | 167 | assert(spapr->vsmt); |
fe6b6346 | 168 | return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); |
46f7afa3 GK |
169 | } |
170 | ||
833d4668 AK |
171 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
172 | int smt_threads) | |
173 | { | |
174 | int i, ret = 0; | |
175 | uint32_t servers_prop[smt_threads]; | |
176 | uint32_t gservers_prop[smt_threads * 2]; | |
14bb4486 | 177 | int index = spapr_get_vcpu_id(cpu); |
833d4668 | 178 | |
d6e166c0 DG |
179 | if (cpu->compat_pvr) { |
180 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
181 | if (ret < 0) { |
182 | return ret; | |
183 | } | |
184 | } | |
185 | ||
833d4668 AK |
186 | /* Build interrupt servers and gservers properties */ |
187 | for (i = 0; i < smt_threads; i++) { | |
188 | servers_prop[i] = cpu_to_be32(index + i); | |
189 | /* Hack, direct the group queues back to cpu 0 */ | |
190 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
191 | gservers_prop[i*2 + 1] = 0; | |
192 | } | |
193 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
194 | servers_prop, sizeof(servers_prop)); | |
195 | if (ret < 0) { | |
196 | return ret; | |
197 | } | |
198 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
199 | gservers_prop, sizeof(gservers_prop)); | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
99861ecb | 204 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 205 | { |
14bb4486 | 206 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
207 | uint32_t associativity[] = {cpu_to_be32(0x5), |
208 | cpu_to_be32(0x0), | |
209 | cpu_to_be32(0x0), | |
210 | cpu_to_be32(0x0), | |
15f8b142 | 211 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
212 | cpu_to_be32(index)}; |
213 | ||
214 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 215 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 216 | sizeof(associativity)); |
0da6f3fe BR |
217 | } |
218 | ||
91335a5e DG |
219 | static void spapr_dt_pa_features(SpaprMachineState *spapr, |
220 | PowerPCCPU *cpu, | |
221 | void *fdt, int offset) | |
86d5771a SB |
222 | { |
223 | uint8_t pa_features_206[] = { 6, 0, | |
224 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
225 | uint8_t pa_features_207[] = { 24, 0, | |
226 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
227 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
228 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
229 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
230 | uint8_t pa_features_300[] = { 66, 0, |
231 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
232 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
233 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
234 | /* 6: DS207 */ | |
235 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
236 | /* 16: Vector */ | |
86d5771a | 237 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 238 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 239 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
240 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
241 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
242 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
243 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
244 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
245 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
246 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
247 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
248 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
249 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
250 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
251 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
252 | /* 60: NM atomic, 62: RNG */ | |
253 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
254 | }; | |
7abd43ba | 255 | uint8_t *pa_features = NULL; |
86d5771a SB |
256 | size_t pa_size; |
257 | ||
7abd43ba | 258 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
259 | pa_features = pa_features_206; |
260 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
261 | } |
262 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
263 | pa_features = pa_features_207; |
264 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
265 | } |
266 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
267 | pa_features = pa_features_300; |
268 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
269 | } |
270 | if (!pa_features) { | |
86d5771a SB |
271 | return; |
272 | } | |
273 | ||
26cd35b8 | 274 | if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { |
86d5771a SB |
275 | /* |
276 | * Note: we keep CI large pages off by default because a 64K capable | |
277 | * guest provisioned with large pages might otherwise try to map a qemu | |
278 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
279 | * even if that qemu runs on a 4k host. | |
280 | * We dd this bit back here if we are confident this is not an issue | |
281 | */ | |
282 | pa_features[3] |= 0x20; | |
283 | } | |
4e5fe368 | 284 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
86d5771a SB |
285 | pa_features[24] |= 0x80; /* Transactional memory support */ |
286 | } | |
daa36379 | 287 | if (spapr->cas_pre_isa3_guest && pa_size > 40) { |
e957f6a9 SB |
288 | /* Workaround for broken kernels that attempt (guest) radix |
289 | * mode when they can't handle it, if they see the radix bit set | |
290 | * in pa-features. So hide it from them. */ | |
291 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
292 | } | |
86d5771a SB |
293 | |
294 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
295 | } | |
296 | ||
c86c1aff | 297 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a | 298 | { |
aa570207 | 299 | if (machine->numa_state->num_nodes) { |
b082d65a | 300 | int i; |
aa570207 | 301 | for (i = 0; i < machine->numa_state->num_nodes; ++i) { |
7e721e7b TX |
302 | if (machine->numa_state->nodes[i].node_mem) { |
303 | return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), | |
fb164994 | 304 | machine->ram_size); |
b082d65a AK |
305 | } |
306 | } | |
307 | } | |
fb164994 | 308 | return machine->ram_size; |
b082d65a AK |
309 | } |
310 | ||
a1d59c0f AK |
311 | static void add_str(GString *s, const gchar *s1) |
312 | { | |
313 | g_string_append_len(s, s1, strlen(s1) + 1); | |
314 | } | |
7f763a5d | 315 | |
91335a5e DG |
316 | static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, |
317 | hwaddr size) | |
26a8c353 AK |
318 | { |
319 | uint32_t associativity[] = { | |
320 | cpu_to_be32(0x4), /* length */ | |
321 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 322 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
323 | }; |
324 | char mem_name[32]; | |
325 | uint64_t mem_reg_property[2]; | |
326 | int off; | |
327 | ||
328 | mem_reg_property[0] = cpu_to_be64(start); | |
329 | mem_reg_property[1] = cpu_to_be64(size); | |
330 | ||
3a17e38f | 331 | sprintf(mem_name, "memory@%" HWADDR_PRIx, start); |
26a8c353 AK |
332 | off = fdt_add_subnode(fdt, 0, mem_name); |
333 | _FDT(off); | |
334 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
335 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
336 | sizeof(mem_reg_property)))); | |
337 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
338 | sizeof(associativity)))); | |
03d196b7 | 339 | return off; |
26a8c353 AK |
340 | } |
341 | ||
f47bd1c8 IM |
342 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
343 | { | |
344 | MemoryDeviceInfoList *info; | |
345 | ||
346 | for (info = list; info; info = info->next) { | |
347 | MemoryDeviceInfo *value = info->value; | |
348 | ||
349 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
350 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
351 | ||
ccc2cef8 | 352 | if (addr >= pcdimm_info->addr && |
f47bd1c8 IM |
353 | addr < (pcdimm_info->addr + pcdimm_info->size)) { |
354 | return pcdimm_info->node; | |
355 | } | |
356 | } | |
357 | } | |
358 | ||
359 | return -1; | |
360 | } | |
361 | ||
a324d6f1 BR |
362 | struct sPAPRDrconfCellV2 { |
363 | uint32_t seq_lmbs; | |
364 | uint64_t base_addr; | |
365 | uint32_t drc_index; | |
366 | uint32_t aa_index; | |
367 | uint32_t flags; | |
368 | } QEMU_PACKED; | |
369 | ||
370 | typedef struct DrconfCellQueue { | |
371 | struct sPAPRDrconfCellV2 cell; | |
372 | QSIMPLEQ_ENTRY(DrconfCellQueue) entry; | |
373 | } DrconfCellQueue; | |
374 | ||
375 | static DrconfCellQueue * | |
376 | spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, | |
377 | uint32_t drc_index, uint32_t aa_index, | |
378 | uint32_t flags) | |
03d196b7 | 379 | { |
a324d6f1 BR |
380 | DrconfCellQueue *elem; |
381 | ||
382 | elem = g_malloc0(sizeof(*elem)); | |
383 | elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); | |
384 | elem->cell.base_addr = cpu_to_be64(base_addr); | |
385 | elem->cell.drc_index = cpu_to_be32(drc_index); | |
386 | elem->cell.aa_index = cpu_to_be32(aa_index); | |
387 | elem->cell.flags = cpu_to_be32(flags); | |
388 | ||
389 | return elem; | |
390 | } | |
391 | ||
91335a5e DG |
392 | static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, |
393 | int offset, MemoryDeviceInfoList *dimms) | |
a324d6f1 | 394 | { |
b0c14ec4 | 395 | MachineState *machine = MACHINE(spapr); |
cc941111 | 396 | uint8_t *int_buf, *cur_index; |
a324d6f1 BR |
397 | int ret; |
398 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
399 | uint64_t addr, cur_addr, size; | |
b0c14ec4 DH |
400 | uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); |
401 | uint64_t mem_end = machine->device_memory->base + | |
402 | memory_region_size(&machine->device_memory->mr); | |
cc941111 | 403 | uint32_t node, buf_len, nr_entries = 0; |
ce2918cb | 404 | SpaprDrc *drc; |
a324d6f1 BR |
405 | DrconfCellQueue *elem, *next; |
406 | MemoryDeviceInfoList *info; | |
407 | QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue | |
408 | = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); | |
409 | ||
410 | /* Entry to cover RAM and the gap area */ | |
411 | elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, | |
412 | SPAPR_LMB_FLAGS_RESERVED | | |
413 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
414 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
415 | nr_entries++; | |
416 | ||
b0c14ec4 | 417 | cur_addr = machine->device_memory->base; |
a324d6f1 BR |
418 | for (info = dimms; info; info = info->next) { |
419 | PCDIMMDeviceInfo *di = info->value->u.dimm.data; | |
420 | ||
421 | addr = di->addr; | |
422 | size = di->size; | |
423 | node = di->node; | |
424 | ||
ee3a71e3 SB |
425 | /* |
426 | * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The | |
427 | * area is marked hotpluggable in the next iteration for the bigger | |
428 | * chunk including the NVDIMM occupied area. | |
429 | */ | |
430 | if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) | |
431 | continue; | |
432 | ||
a324d6f1 BR |
433 | /* Entry for hot-pluggable area */ |
434 | if (cur_addr < addr) { | |
435 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
436 | g_assert(drc); | |
437 | elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, | |
438 | cur_addr, spapr_drc_index(drc), -1, 0); | |
439 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
440 | nr_entries++; | |
441 | } | |
442 | ||
443 | /* Entry for DIMM */ | |
444 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); | |
445 | g_assert(drc); | |
446 | elem = spapr_get_drconf_cell(size / lmb_size, addr, | |
447 | spapr_drc_index(drc), node, | |
0911a60c LB |
448 | (SPAPR_LMB_FLAGS_ASSIGNED | |
449 | SPAPR_LMB_FLAGS_HOTREMOVABLE)); | |
a324d6f1 BR |
450 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); |
451 | nr_entries++; | |
452 | cur_addr = addr + size; | |
453 | } | |
454 | ||
455 | /* Entry for remaining hotpluggable area */ | |
456 | if (cur_addr < mem_end) { | |
457 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
458 | g_assert(drc); | |
459 | elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, | |
460 | cur_addr, spapr_drc_index(drc), -1, 0); | |
461 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
462 | nr_entries++; | |
463 | } | |
464 | ||
465 | buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); | |
466 | int_buf = cur_index = g_malloc0(buf_len); | |
467 | *(uint32_t *)int_buf = cpu_to_be32(nr_entries); | |
468 | cur_index += sizeof(nr_entries); | |
469 | ||
470 | QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { | |
471 | memcpy(cur_index, &elem->cell, sizeof(elem->cell)); | |
472 | cur_index += sizeof(elem->cell); | |
473 | QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); | |
474 | g_free(elem); | |
475 | } | |
476 | ||
477 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); | |
478 | g_free(int_buf); | |
479 | if (ret < 0) { | |
480 | return -1; | |
481 | } | |
482 | return 0; | |
483 | } | |
484 | ||
91335a5e | 485 | static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, |
a324d6f1 BR |
486 | int offset, MemoryDeviceInfoList *dimms) |
487 | { | |
b0c14ec4 | 488 | MachineState *machine = MACHINE(spapr); |
a324d6f1 | 489 | int i, ret; |
03d196b7 | 490 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
0c9269a5 | 491 | uint32_t device_lmb_start = machine->device_memory->base / lmb_size; |
b0c14ec4 DH |
492 | uint32_t nr_lmbs = (machine->device_memory->base + |
493 | memory_region_size(&machine->device_memory->mr)) / | |
d0e5a8f2 | 494 | lmb_size; |
03d196b7 | 495 | uint32_t *int_buf, *cur_index, buf_len; |
16c25aef | 496 | |
ef001f06 TH |
497 | /* |
498 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
ef001f06 | 499 | */ |
a324d6f1 | 500 | buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); |
03d196b7 | 501 | cur_index = int_buf = g_malloc0(buf_len); |
03d196b7 BR |
502 | int_buf[0] = cpu_to_be32(nr_lmbs); |
503 | cur_index++; | |
504 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 505 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
506 | uint32_t *dynamic_memory = cur_index; |
507 | ||
0c9269a5 | 508 | if (i >= device_lmb_start) { |
ce2918cb | 509 | SpaprDrc *drc; |
d0e5a8f2 | 510 | |
fbf55397 | 511 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 512 | g_assert(drc); |
d0e5a8f2 BR |
513 | |
514 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
515 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 516 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 517 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 518 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
519 | if (memory_region_present(get_system_memory(), addr)) { |
520 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
521 | } else { | |
522 | dynamic_memory[5] = cpu_to_be32(0); | |
523 | } | |
03d196b7 | 524 | } else { |
d0e5a8f2 BR |
525 | /* |
526 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
0c9269a5 | 527 | * device memory region -- all these are marked as reserved |
d0e5a8f2 BR |
528 | * and as having no valid DRC. |
529 | */ | |
530 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
531 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
532 | dynamic_memory[2] = cpu_to_be32(0); | |
533 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
534 | dynamic_memory[4] = cpu_to_be32(-1); | |
535 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
536 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
537 | } |
538 | ||
539 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
540 | } | |
541 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
a324d6f1 | 542 | g_free(int_buf); |
03d196b7 | 543 | if (ret < 0) { |
a324d6f1 BR |
544 | return -1; |
545 | } | |
546 | return 0; | |
547 | } | |
548 | ||
549 | /* | |
550 | * Adds ibm,dynamic-reconfiguration-memory node. | |
551 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
552 | * of this device tree node. | |
553 | */ | |
91335a5e DG |
554 | static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, |
555 | void *fdt) | |
a324d6f1 BR |
556 | { |
557 | MachineState *machine = MACHINE(spapr); | |
aa570207 | 558 | int nb_numa_nodes = machine->numa_state->num_nodes; |
a324d6f1 BR |
559 | int ret, i, offset; |
560 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
561 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
562 | uint32_t *int_buf, *cur_index, buf_len; | |
563 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; | |
564 | MemoryDeviceInfoList *dimms = NULL; | |
565 | ||
566 | /* | |
0c9269a5 | 567 | * Don't create the node if there is no device memory |
a324d6f1 BR |
568 | */ |
569 | if (machine->ram_size == machine->maxram_size) { | |
570 | return 0; | |
571 | } | |
572 | ||
573 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
574 | ||
575 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
576 | sizeof(prop_lmb_size)); | |
577 | if (ret < 0) { | |
578 | return ret; | |
579 | } | |
580 | ||
581 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
582 | if (ret < 0) { | |
583 | return ret; | |
584 | } | |
585 | ||
586 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
587 | if (ret < 0) { | |
588 | return ret; | |
589 | } | |
590 | ||
591 | /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ | |
2cc0e2e8 | 592 | dimms = qmp_memory_device_list(); |
a324d6f1 | 593 | if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { |
91335a5e | 594 | ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); |
a324d6f1 | 595 | } else { |
91335a5e | 596 | ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); |
a324d6f1 BR |
597 | } |
598 | qapi_free_MemoryDeviceInfoList(dimms); | |
599 | ||
600 | if (ret < 0) { | |
601 | return ret; | |
03d196b7 BR |
602 | } |
603 | ||
604 | /* ibm,associativity-lookup-arrays */ | |
a324d6f1 BR |
605 | buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); |
606 | cur_index = int_buf = g_malloc0(buf_len); | |
6663864e | 607 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
608 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
609 | cur_index += 2; | |
6663864e | 610 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
611 | uint32_t associativity[] = { |
612 | cpu_to_be32(0x0), | |
613 | cpu_to_be32(0x0), | |
614 | cpu_to_be32(0x0), | |
615 | cpu_to_be32(i) | |
616 | }; | |
617 | memcpy(cur_index, associativity, sizeof(associativity)); | |
618 | cur_index += 4; | |
619 | } | |
620 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
621 | (cur_index - int_buf) * sizeof(uint32_t)); | |
03d196b7 | 622 | g_free(int_buf); |
a324d6f1 | 623 | |
03d196b7 BR |
624 | return ret; |
625 | } | |
626 | ||
91335a5e | 627 | static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) |
6787d27b | 628 | { |
fa523f0d | 629 | MachineState *machine = MACHINE(spapr); |
ce2918cb | 630 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
fa523f0d DG |
631 | hwaddr mem_start, node_size; |
632 | int i, nb_nodes = machine->numa_state->num_nodes; | |
633 | NodeInfo *nodes = machine->numa_state->nodes; | |
634 | ||
635 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { | |
636 | if (!nodes[i].node_mem) { | |
637 | continue; | |
638 | } | |
639 | if (mem_start >= machine->ram_size) { | |
640 | node_size = 0; | |
641 | } else { | |
642 | node_size = nodes[i].node_mem; | |
643 | if (node_size > machine->ram_size - mem_start) { | |
644 | node_size = machine->ram_size - mem_start; | |
645 | } | |
646 | } | |
647 | if (!mem_start) { | |
648 | /* spapr_machine_init() checks for rma_size <= node0_size | |
649 | * already */ | |
91335a5e | 650 | spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); |
fa523f0d DG |
651 | mem_start += spapr->rma_size; |
652 | node_size -= spapr->rma_size; | |
653 | } | |
654 | for ( ; node_size; ) { | |
655 | hwaddr sizetmp = pow2floor(node_size); | |
656 | ||
657 | /* mem_start != 0 here */ | |
658 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
659 | sizetmp = 1ULL << ctzl(mem_start); | |
660 | } | |
661 | ||
91335a5e | 662 | spapr_dt_memory_node(fdt, i, mem_start, sizetmp); |
fa523f0d DG |
663 | node_size -= sizetmp; |
664 | mem_start += sizetmp; | |
665 | } | |
666 | } | |
6787d27b MR |
667 | |
668 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
fa523f0d DG |
669 | if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { |
670 | int ret; | |
671 | ||
6787d27b | 672 | g_assert(smc->dr_lmb_enabled); |
91335a5e | 673 | ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); |
417ece33 | 674 | if (ret) { |
9b6c1da5 | 675 | return ret; |
417ece33 | 676 | } |
6787d27b MR |
677 | } |
678 | ||
fa523f0d DG |
679 | return 0; |
680 | } | |
681 | ||
91335a5e DG |
682 | static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, |
683 | SpaprMachineState *spapr) | |
fa523f0d DG |
684 | { |
685 | MachineState *ms = MACHINE(spapr); | |
686 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
687 | CPUPPCState *env = &cpu->env; | |
688 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
689 | int index = spapr_get_vcpu_id(cpu); | |
690 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
691 | 0xffffffff, 0xffffffff}; | |
692 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() | |
693 | : SPAPR_TIMEBASE_FREQ; | |
694 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; | |
695 | uint32_t page_sizes_prop[64]; | |
696 | size_t page_sizes_prop_size; | |
697 | unsigned int smp_threads = ms->smp.threads; | |
698 | uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; | |
699 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; | |
700 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); | |
701 | SpaprDrc *drc; | |
702 | int drc_index; | |
703 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; | |
704 | int i; | |
705 | ||
706 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); | |
707 | if (drc) { | |
708 | drc_index = spapr_drc_index(drc); | |
709 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); | |
710 | } | |
711 | ||
712 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
713 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
714 | ||
715 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
716 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
717 | env->dcache_line_size))); | |
718 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
719 | env->dcache_line_size))); | |
720 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
721 | env->icache_line_size))); | |
722 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
723 | env->icache_line_size))); | |
724 | ||
725 | if (pcc->l1_dcache_size) { | |
726 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
727 | pcc->l1_dcache_size))); | |
728 | } else { | |
729 | warn_report("Unknown L1 dcache size for cpu"); | |
730 | } | |
731 | if (pcc->l1_icache_size) { | |
732 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
733 | pcc->l1_icache_size))); | |
734 | } else { | |
735 | warn_report("Unknown L1 icache size for cpu"); | |
736 | } | |
737 | ||
738 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
739 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
740 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); | |
741 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); | |
742 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
743 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
744 | ||
745 | if (env->spr_cb[SPR_PURR].oea_read) { | |
746 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); | |
747 | } | |
748 | if (env->spr_cb[SPR_SPURR].oea_read) { | |
749 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); | |
750 | } | |
a324d6f1 | 751 | |
fa523f0d DG |
752 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
753 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
754 | segs, sizeof(segs)))); | |
a324d6f1 BR |
755 | } |
756 | ||
fa523f0d DG |
757 | /* Advertise VSX (vector extensions) if available |
758 | * 1 == VMX / Altivec available | |
759 | * 2 == VSX available | |
760 | * | |
761 | * Only CPUs for which we create core types in spapr_cpu_core.c | |
762 | * are possible, and all of those have VMX */ | |
763 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { | |
764 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); | |
765 | } else { | |
766 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); | |
767 | } | |
a324d6f1 | 768 | |
fa523f0d DG |
769 | /* Advertise DFP (Decimal Floating Point) if available |
770 | * 0 / no property == no DFP | |
771 | * 1 == DFP available */ | |
772 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { | |
773 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
a324d6f1 BR |
774 | } |
775 | ||
fa523f0d DG |
776 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
777 | sizeof(page_sizes_prop)); | |
778 | if (page_sizes_prop_size) { | |
779 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
780 | page_sizes_prop, page_sizes_prop_size))); | |
a324d6f1 BR |
781 | } |
782 | ||
91335a5e | 783 | spapr_dt_pa_features(spapr, cpu, fdt, offset); |
fa523f0d DG |
784 | |
785 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", | |
786 | cs->cpu_index / vcpus_per_socket))); | |
787 | ||
788 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
789 | pft_size_prop, sizeof(pft_size_prop)))); | |
790 | ||
791 | if (ms->numa_state->num_nodes > 1) { | |
792 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
a324d6f1 BR |
793 | } |
794 | ||
fa523f0d DG |
795 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
796 | ||
797 | if (pcc->radix_page_info) { | |
798 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
799 | radix_AP_encodings[i] = | |
800 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
801 | } | |
802 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
803 | radix_AP_encodings, | |
804 | pcc->radix_page_info->count * | |
805 | sizeof(radix_AP_encodings[0])))); | |
a324d6f1 | 806 | } |
a324d6f1 | 807 | |
fa523f0d DG |
808 | /* |
809 | * We set this property to let the guest know that it can use the large | |
810 | * decrementer and its width in bits. | |
811 | */ | |
812 | if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) | |
813 | _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", | |
814 | pcc->lrg_decr_bits))); | |
815 | } | |
816 | ||
91335a5e | 817 | static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) |
fa523f0d DG |
818 | { |
819 | CPUState **rev; | |
820 | CPUState *cs; | |
821 | int n_cpus; | |
822 | int cpus_offset; | |
823 | char *nodename; | |
824 | int i; | |
825 | ||
826 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
827 | _FDT(cpus_offset); | |
828 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
829 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
830 | ||
831 | /* | |
832 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
833 | * created by fdt_add_subnode() end up in the right order in FDT | |
834 | * for the guest kernel the enumerate the CPUs correctly. | |
835 | * | |
836 | * The CPU list cannot be traversed in reverse order, so we need | |
837 | * to do extra work. | |
838 | */ | |
839 | n_cpus = 0; | |
840 | rev = NULL; | |
841 | CPU_FOREACH(cs) { | |
842 | rev = g_renew(CPUState *, rev, n_cpus + 1); | |
843 | rev[n_cpus++] = cs; | |
03d196b7 BR |
844 | } |
845 | ||
fa523f0d DG |
846 | for (i = n_cpus - 1; i >= 0; i--) { |
847 | CPUState *cs = rev[i]; | |
848 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
849 | int index = spapr_get_vcpu_id(cpu); | |
850 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
851 | int offset; | |
852 | ||
853 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { | |
854 | continue; | |
855 | } | |
856 | ||
857 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
858 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
859 | g_free(nodename); | |
860 | _FDT(offset); | |
91335a5e | 861 | spapr_dt_cpu(cs, fdt, offset, spapr); |
03d196b7 | 862 | } |
a324d6f1 | 863 | |
fa523f0d | 864 | g_free(rev); |
03d196b7 BR |
865 | } |
866 | ||
91335a5e | 867 | static int spapr_dt_rng(void *fdt) |
6787d27b | 868 | { |
fa523f0d DG |
869 | int node; |
870 | int ret; | |
6787d27b | 871 | |
fa523f0d DG |
872 | node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); |
873 | if (node <= 0) { | |
874 | return -1; | |
6787d27b | 875 | } |
fa523f0d DG |
876 | ret = fdt_setprop_string(fdt, node, "device_type", |
877 | "ibm,platform-facilities"); | |
878 | ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); | |
879 | ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); | |
6787d27b | 880 | |
fa523f0d DG |
881 | node = fdt_add_subnode(fdt, node, "ibm,random-v1"); |
882 | if (node <= 0) { | |
883 | return -1; | |
417ece33 | 884 | } |
fa523f0d DG |
885 | ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); |
886 | ||
887 | return ret ? -1 : 0; | |
6787d27b MR |
888 | } |
889 | ||
ce2918cb | 890 | static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) |
3f5dabce | 891 | { |
fe6b6346 | 892 | MachineState *ms = MACHINE(spapr); |
3f5dabce DG |
893 | int rtas; |
894 | GString *hypertas = g_string_sized_new(256); | |
895 | GString *qemu_hypertas = g_string_sized_new(256); | |
896 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
0c9269a5 | 897 | uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + |
b0c14ec4 | 898 | memory_region_size(&MACHINE(spapr)->device_memory->mr); |
3f5dabce | 899 | uint32_t lrdr_capacity[] = { |
0c9269a5 DH |
900 | cpu_to_be32(max_device_addr >> 32), |
901 | cpu_to_be32(max_device_addr & 0xffffffff), | |
3f5dabce | 902 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), |
fe6b6346 | 903 | cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), |
3f5dabce | 904 | }; |
ec132efa | 905 | uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); |
da9f80fb SP |
906 | uint32_t maxdomains[] = { |
907 | cpu_to_be32(4), | |
ec132efa AK |
908 | maxdomain, |
909 | maxdomain, | |
910 | maxdomain, | |
911 | cpu_to_be32(spapr->gpu_numa_id), | |
da9f80fb | 912 | }; |
3f5dabce DG |
913 | |
914 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
915 | ||
916 | /* hypertas */ | |
917 | add_str(hypertas, "hcall-pft"); | |
918 | add_str(hypertas, "hcall-term"); | |
919 | add_str(hypertas, "hcall-dabr"); | |
920 | add_str(hypertas, "hcall-interrupt"); | |
921 | add_str(hypertas, "hcall-tce"); | |
922 | add_str(hypertas, "hcall-vio"); | |
923 | add_str(hypertas, "hcall-splpar"); | |
10741314 | 924 | add_str(hypertas, "hcall-join"); |
3f5dabce DG |
925 | add_str(hypertas, "hcall-bulk"); |
926 | add_str(hypertas, "hcall-set-mode"); | |
927 | add_str(hypertas, "hcall-sprg0"); | |
928 | add_str(hypertas, "hcall-copy"); | |
929 | add_str(hypertas, "hcall-debug"); | |
c24ba3d0 | 930 | add_str(hypertas, "hcall-vphn"); |
3f5dabce DG |
931 | add_str(qemu_hypertas, "hcall-memop1"); |
932 | ||
933 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
934 | add_str(hypertas, "hcall-multi-tce"); | |
935 | } | |
30f4b05b DG |
936 | |
937 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
938 | add_str(hypertas, "hcall-hpt-resize"); | |
939 | } | |
940 | ||
3f5dabce DG |
941 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
942 | hypertas->str, hypertas->len)); | |
943 | g_string_free(hypertas, TRUE); | |
944 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
945 | qemu_hypertas->str, qemu_hypertas->len)); | |
946 | g_string_free(qemu_hypertas, TRUE); | |
947 | ||
948 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
949 | refpoints, sizeof(refpoints))); | |
950 | ||
da9f80fb SP |
951 | _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", |
952 | maxdomains, sizeof(maxdomains))); | |
953 | ||
0e236d34 NP |
954 | /* |
955 | * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, | |
956 | * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. | |
957 | * | |
958 | * The system reset requirements are driven by existing Linux and PowerVM | |
959 | * implementation which (contrary to PAPR) saves r3 in the error log | |
960 | * structure like machine check, so Linux expects to find the saved r3 | |
961 | * value at the address in r3 upon FWNMI-enabled sreset interrupt (and | |
962 | * does not look at the error value). | |
963 | * | |
964 | * System reset interrupts are not subject to interlock like machine | |
965 | * check, so this memory area could be corrupted if the sreset is | |
966 | * interrupted by a machine check (or vice versa) if it was shared. To | |
967 | * prevent this, system reset uses per-CPU areas for the sreset save | |
968 | * area. A system reset that interrupts a system reset handler could | |
969 | * still overwrite this area, but Linux doesn't try to recover in that | |
970 | * case anyway. | |
971 | * | |
972 | * The extra 8 bytes is required because Linux's FWNMI error log check | |
973 | * is off-by-one. | |
974 | */ | |
975 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + | |
976 | ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); | |
3f5dabce DG |
977 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", |
978 | RTAS_ERROR_LOG_MAX)); | |
979 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
980 | RTAS_EVENT_SCAN_RATE)); | |
981 | ||
4f441474 DG |
982 | g_assert(msi_nonbroken); |
983 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
984 | |
985 | /* | |
986 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
987 | * back to the guest cpu. | |
988 | * | |
989 | * While an additional ibm,extended-os-term property indicates | |
990 | * that rtas call return will always occur. Set this property. | |
991 | */ | |
992 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
993 | ||
994 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
995 | lrdr_capacity, sizeof(lrdr_capacity))); | |
996 | ||
997 | spapr_dt_rtas_tokens(fdt, rtas); | |
998 | } | |
999 | ||
db592b5b CLG |
1000 | /* |
1001 | * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU | |
1002 | * and the XIVE features that the guest may request and thus the valid | |
1003 | * values for bytes 23..26 of option vector 5: | |
1004 | */ | |
ce2918cb | 1005 | static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, |
db592b5b | 1006 | int chosen) |
9fb4541f | 1007 | { |
545d6e2b SJS |
1008 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
1009 | ||
f2b14e3a | 1010 | char val[2 * 4] = { |
ca62823b | 1011 | 23, 0x00, /* XICS / XIVE mode */ |
9fb4541f SB |
1012 | 24, 0x00, /* Hash/Radix, filled in below. */ |
1013 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
1014 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
1015 | }; | |
1016 | ||
ca62823b DG |
1017 | if (spapr->irq->xics && spapr->irq->xive) { |
1018 | val[1] = SPAPR_OV5_XIVE_BOTH; | |
1019 | } else if (spapr->irq->xive) { | |
1020 | val[1] = SPAPR_OV5_XIVE_EXPLOIT; | |
1021 | } else { | |
1022 | assert(spapr->irq->xics); | |
1023 | val[1] = SPAPR_OV5_XIVE_LEGACY; | |
1024 | } | |
1025 | ||
7abd43ba SJS |
1026 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
1027 | first_ppc_cpu->compat_pvr)) { | |
db592b5b CLG |
1028 | /* |
1029 | * If we're in a pre POWER9 compat mode then the guest should | |
1030 | * do hash and use the legacy interrupt mode | |
1031 | */ | |
ca62823b | 1032 | val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ |
7abd43ba SJS |
1033 | val[3] = 0x00; /* Hash */ |
1034 | } else if (kvm_enabled()) { | |
9fb4541f | 1035 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 1036 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 1037 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 1038 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 1039 | } else { |
f2b14e3a | 1040 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
1041 | } |
1042 | } else { | |
7abd43ba SJS |
1043 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
1044 | val[3] = 0xC0; | |
9fb4541f SB |
1045 | } |
1046 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
1047 | val, sizeof(val))); | |
1048 | } | |
1049 | ||
1e0e1108 | 1050 | static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) |
7c866c6a DG |
1051 | { |
1052 | MachineState *machine = MACHINE(spapr); | |
6c3829a2 | 1053 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1054 | int chosen; |
7c866c6a DG |
1055 | |
1056 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1057 | ||
1e0e1108 DG |
1058 | if (reset) { |
1059 | const char *boot_device = machine->boot_order; | |
1060 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1061 | size_t cb = 0; | |
1062 | char *bootlist = get_boot_devices_list(&cb); | |
1063 | ||
1064 | if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { | |
1065 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", | |
1066 | machine->kernel_cmdline)); | |
1067 | } | |
7c866c6a | 1068 | |
1e0e1108 DG |
1069 | if (spapr->initrd_size) { |
1070 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1071 | spapr->initrd_base)); | |
1072 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1073 | spapr->initrd_base + spapr->initrd_size)); | |
1074 | } | |
7c866c6a | 1075 | |
1e0e1108 DG |
1076 | if (spapr->kernel_size) { |
1077 | uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), | |
1078 | cpu_to_be64(spapr->kernel_size) }; | |
7c866c6a | 1079 | |
1e0e1108 | 1080 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", |
7c866c6a | 1081 | &kprop, sizeof(kprop))); |
1e0e1108 DG |
1082 | if (spapr->kernel_le) { |
1083 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1084 | } | |
7c866c6a | 1085 | } |
1e0e1108 DG |
1086 | if (boot_menu) { |
1087 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1088 | } | |
1089 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1090 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1091 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
7c866c6a | 1092 | |
1e0e1108 DG |
1093 | if (cb && bootlist) { |
1094 | int i; | |
7c866c6a | 1095 | |
1e0e1108 DG |
1096 | for (i = 0; i < cb; i++) { |
1097 | if (bootlist[i] == '\n') { | |
1098 | bootlist[i] = ' '; | |
1099 | } | |
7c866c6a | 1100 | } |
1e0e1108 | 1101 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); |
7c866c6a | 1102 | } |
7c866c6a | 1103 | |
1e0e1108 DG |
1104 | if (boot_device && strlen(boot_device)) { |
1105 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1106 | } | |
1107 | ||
1108 | if (!spapr->has_graphics && stdout_path) { | |
1109 | /* | |
1110 | * "linux,stdout-path" and "stdout" properties are | |
1111 | * deprecated by linux kernel. New platforms should only | |
1112 | * use the "stdout-path" property. Set the new property | |
1113 | * and continue using older property to remain compatible | |
1114 | * with the existing firmware. | |
1115 | */ | |
1116 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
1117 | _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); | |
1118 | } | |
7c866c6a | 1119 | |
90ee4e01 | 1120 | /* |
1e0e1108 DG |
1121 | * We can deal with BAR reallocation just fine, advertise it |
1122 | * to the guest | |
90ee4e01 | 1123 | */ |
1e0e1108 DG |
1124 | if (smc->linux_pci_probe) { |
1125 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); | |
1126 | } | |
7c866c6a | 1127 | |
1e0e1108 | 1128 | spapr_dt_ov5_platform_support(spapr, fdt, chosen); |
6c3829a2 | 1129 | |
1e0e1108 DG |
1130 | g_free(stdout_path); |
1131 | g_free(bootlist); | |
1132 | } | |
9fb4541f | 1133 | |
91335a5e | 1134 | _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); |
7c866c6a DG |
1135 | } |
1136 | ||
ce2918cb | 1137 | static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) |
fca5f2dc DG |
1138 | { |
1139 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1140 | * KVM to work under pHyp with some guest co-operation */ | |
1141 | int hypervisor; | |
1142 | uint8_t hypercall[16]; | |
1143 | ||
1144 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1145 | /* indicate KVM hypercall interface */ | |
1146 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1147 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1148 | /* | |
1149 | * Older KVM versions with older guest kernels were broken | |
1150 | * with the magic page, don't allow the guest to map it. | |
1151 | */ | |
1152 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1153 | sizeof(hypercall))) { | |
1154 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1155 | hypercall, sizeof(hypercall))); | |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | ||
0c21e073 | 1160 | void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) |
a3467baa | 1161 | { |
c86c1aff | 1162 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1163 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
ce2918cb | 1164 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1165 | int ret; |
a3467baa | 1166 | void *fdt; |
ce2918cb | 1167 | SpaprPhbState *phb; |
398a0bd5 | 1168 | char *buf; |
a3467baa | 1169 | |
97b32a6a DG |
1170 | fdt = g_malloc0(space); |
1171 | _FDT((fdt_create_empty_tree(fdt, space))); | |
a3467baa | 1172 | |
398a0bd5 DG |
1173 | /* Root node */ |
1174 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1175 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1176 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1177 | ||
0a794529 | 1178 | /* Guest UUID & Name*/ |
398a0bd5 | 1179 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); |
398a0bd5 DG |
1180 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); |
1181 | if (qemu_uuid_set) { | |
1182 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1183 | } | |
1184 | g_free(buf); | |
1185 | ||
1186 | if (qemu_get_vm_name()) { | |
1187 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1188 | qemu_get_vm_name())); | |
1189 | } | |
1190 | ||
0a794529 DG |
1191 | /* Host Model & Serial Number */ |
1192 | if (spapr->host_model) { | |
1193 | _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); | |
1194 | } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { | |
1195 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1196 | g_free(buf); | |
1197 | } | |
1198 | ||
1199 | if (spapr->host_serial) { | |
1200 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); | |
1201 | } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { | |
1202 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1203 | g_free(buf); | |
1204 | } | |
1205 | ||
398a0bd5 DG |
1206 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); |
1207 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1208 | |
fc7e0765 | 1209 | /* /interrupt controller */ |
05289273 | 1210 | spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); |
fc7e0765 | 1211 | |
91335a5e | 1212 | ret = spapr_dt_memory(spapr, fdt); |
e8f986fc | 1213 | if (ret < 0) { |
ce9863b7 | 1214 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1215 | exit(1); |
7f763a5d DG |
1216 | } |
1217 | ||
bf5a6696 DG |
1218 | /* /vdevice */ |
1219 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1220 | |
4d9392be | 1221 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
91335a5e | 1222 | ret = spapr_dt_rng(fdt); |
4d9392be | 1223 | if (ret < 0) { |
ce9863b7 | 1224 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1225 | exit(1); |
1226 | } | |
1227 | } | |
1228 | ||
3384f95c | 1229 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
8cbe71ec | 1230 | ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); |
da34fed7 TH |
1231 | if (ret < 0) { |
1232 | error_report("couldn't setup PCI devices in fdt"); | |
1233 | exit(1); | |
1234 | } | |
3384f95c DG |
1235 | } |
1236 | ||
91335a5e | 1237 | spapr_dt_cpus(fdt, spapr); |
6e806cc3 | 1238 | |
c20d332a | 1239 | if (smc->dr_lmb_enabled) { |
9e7d38e8 | 1240 | _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); |
c20d332a BR |
1241 | } |
1242 | ||
c5514d0e | 1243 | if (mc->has_hotpluggable_cpus) { |
af81cf32 | 1244 | int offset = fdt_path_offset(fdt, "/cpus"); |
9e7d38e8 | 1245 | ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); |
af81cf32 BR |
1246 | if (ret < 0) { |
1247 | error_report("Couldn't set up CPU DR device tree properties"); | |
1248 | exit(1); | |
1249 | } | |
1250 | } | |
1251 | ||
ffb1e275 | 1252 | /* /event-sources */ |
ffbb1705 | 1253 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1254 | |
3f5dabce DG |
1255 | /* /rtas */ |
1256 | spapr_dt_rtas(spapr, fdt); | |
1257 | ||
7c866c6a | 1258 | /* /chosen */ |
1e0e1108 | 1259 | spapr_dt_chosen(spapr, fdt, reset); |
cf6e5223 | 1260 | |
fca5f2dc DG |
1261 | /* /hypervisor */ |
1262 | if (kvm_enabled()) { | |
1263 | spapr_dt_hypervisor(spapr, fdt); | |
1264 | } | |
1265 | ||
cf6e5223 | 1266 | /* Build memory reserve map */ |
a49f62b9 AK |
1267 | if (reset) { |
1268 | if (spapr->kernel_size) { | |
87262806 AK |
1269 | _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, |
1270 | spapr->kernel_size))); | |
a49f62b9 AK |
1271 | } |
1272 | if (spapr->initrd_size) { | |
1273 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, | |
1274 | spapr->initrd_size))); | |
1275 | } | |
cf6e5223 DG |
1276 | } |
1277 | ||
3998ccd0 | 1278 | if (smc->dr_phb_enabled) { |
9e7d38e8 | 1279 | ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); |
3998ccd0 NF |
1280 | if (ret < 0) { |
1281 | error_report("Couldn't set up PHB DR device tree properties"); | |
1282 | exit(1); | |
1283 | } | |
1284 | } | |
1285 | ||
ee3a71e3 SB |
1286 | /* NVDIMM devices */ |
1287 | if (mc->nvdimm_supported) { | |
1288 | spapr_dt_persistent_memory(fdt); | |
1289 | } | |
1290 | ||
997b6cfc | 1291 | return fdt; |
9fdf0c29 DG |
1292 | } |
1293 | ||
1294 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1295 | { | |
87262806 AK |
1296 | SpaprMachineState *spapr = opaque; |
1297 | ||
1298 | return (addr & 0x0fffffff) + spapr->kernel_addr; | |
9fdf0c29 DG |
1299 | } |
1300 | ||
1d1be34d DG |
1301 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1302 | PowerPCCPU *cpu) | |
9fdf0c29 | 1303 | { |
1b14670a AF |
1304 | CPUPPCState *env = &cpu->env; |
1305 | ||
8d04fb55 JK |
1306 | /* The TCG path should also be holding the BQL at this point */ |
1307 | g_assert(qemu_mutex_iothread_locked()); | |
1308 | ||
efcb9383 DG |
1309 | if (msr_pr) { |
1310 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1311 | env->gpr[3] = H_PRIVILEGE; | |
1312 | } else { | |
aa100fa4 | 1313 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1314 | } |
9fdf0c29 DG |
1315 | } |
1316 | ||
00fd075e BH |
1317 | struct LPCRSyncState { |
1318 | target_ulong value; | |
1319 | target_ulong mask; | |
1320 | }; | |
1321 | ||
1322 | static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) | |
1323 | { | |
1324 | struct LPCRSyncState *s = arg.host_ptr; | |
1325 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1326 | CPUPPCState *env = &cpu->env; | |
1327 | target_ulong lpcr; | |
1328 | ||
1329 | cpu_synchronize_state(cs); | |
1330 | lpcr = env->spr[SPR_LPCR]; | |
1331 | lpcr &= ~s->mask; | |
1332 | lpcr |= s->value; | |
1333 | ppc_store_lpcr(cpu, lpcr); | |
1334 | } | |
1335 | ||
1336 | void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) | |
1337 | { | |
1338 | CPUState *cs; | |
1339 | struct LPCRSyncState s = { | |
1340 | .value = value, | |
1341 | .mask = mask | |
1342 | }; | |
1343 | CPU_FOREACH(cs) { | |
1344 | run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); | |
1345 | } | |
1346 | } | |
1347 | ||
79825f4d | 1348 | static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) |
9861bb3e | 1349 | { |
ce2918cb | 1350 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
9861bb3e | 1351 | |
79825f4d BH |
1352 | /* Copy PATE1:GR into PATE0:HR */ |
1353 | entry->dw0 = spapr->patb_entry & PATE0_HR; | |
1354 | entry->dw1 = spapr->patb_entry; | |
9861bb3e SJS |
1355 | } |
1356 | ||
e6b8fd24 SMJ |
1357 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1358 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1359 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1360 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1361 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1362 | ||
715c5407 DG |
1363 | /* |
1364 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1365 | */ | |
ce2918cb | 1366 | static int get_htab_fd(SpaprMachineState *spapr) |
715c5407 | 1367 | { |
14b0d748 GK |
1368 | Error *local_err = NULL; |
1369 | ||
715c5407 DG |
1370 | if (spapr->htab_fd >= 0) { |
1371 | return spapr->htab_fd; | |
1372 | } | |
1373 | ||
14b0d748 | 1374 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1375 | if (spapr->htab_fd < 0) { |
14b0d748 | 1376 | error_report_err(local_err); |
715c5407 DG |
1377 | } |
1378 | ||
1379 | return spapr->htab_fd; | |
1380 | } | |
1381 | ||
ce2918cb | 1382 | void close_htab_fd(SpaprMachineState *spapr) |
715c5407 DG |
1383 | { |
1384 | if (spapr->htab_fd >= 0) { | |
1385 | close(spapr->htab_fd); | |
1386 | } | |
1387 | spapr->htab_fd = -1; | |
1388 | } | |
1389 | ||
e57ca75c DG |
1390 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1391 | { | |
ce2918cb | 1392 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
e57ca75c DG |
1393 | |
1394 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1395 | } | |
1396 | ||
1ec26c75 GK |
1397 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1398 | { | |
ce2918cb | 1399 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
1ec26c75 GK |
1400 | |
1401 | assert(kvm_enabled()); | |
1402 | ||
1403 | if (!spapr->htab) { | |
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1408 | } | |
1409 | ||
e57ca75c DG |
1410 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1411 | hwaddr ptex, int n) | |
1412 | { | |
ce2918cb | 1413 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
e57ca75c DG |
1414 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
1415 | ||
1416 | if (!spapr->htab) { | |
1417 | /* | |
1418 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1419 | */ | |
1420 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1421 | kvmppc_read_hptes(hptes, ptex, n); | |
1422 | return hptes; | |
1423 | } | |
1424 | ||
1425 | /* | |
1426 | * HTAB is controlled by QEMU. Just point to the internally | |
1427 | * accessible PTEG. | |
1428 | */ | |
1429 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1430 | } | |
1431 | ||
1432 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1433 | const ppc_hash_pte64_t *hptes, | |
1434 | hwaddr ptex, int n) | |
1435 | { | |
ce2918cb | 1436 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); |
e57ca75c DG |
1437 | |
1438 | if (!spapr->htab) { | |
1439 | g_free((void *)hptes); | |
1440 | } | |
1441 | ||
1442 | /* Nothing to do for qemu managed HPT */ | |
1443 | } | |
1444 | ||
a2dd4e83 BH |
1445 | void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, |
1446 | uint64_t pte0, uint64_t pte1) | |
e57ca75c | 1447 | { |
a2dd4e83 | 1448 | SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); |
e57ca75c DG |
1449 | hwaddr offset = ptex * HASH_PTE_SIZE_64; |
1450 | ||
1451 | if (!spapr->htab) { | |
1452 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1453 | } else { | |
3054b0ca BH |
1454 | if (pte0 & HPTE64_V_VALID) { |
1455 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1456 | /* | |
1457 | * When setting valid, we write PTE1 first. This ensures | |
1458 | * proper synchronization with the reading code in | |
1459 | * ppc_hash64_pteg_search() | |
1460 | */ | |
1461 | smp_wmb(); | |
1462 | stq_p(spapr->htab + offset, pte0); | |
1463 | } else { | |
1464 | stq_p(spapr->htab + offset, pte0); | |
1465 | /* | |
1466 | * When clearing it we set PTE0 first. This ensures proper | |
1467 | * synchronization with the reading code in | |
1468 | * ppc_hash64_pteg_search() | |
1469 | */ | |
1470 | smp_wmb(); | |
1471 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1472 | } | |
e57ca75c DG |
1473 | } |
1474 | } | |
1475 | ||
a2dd4e83 BH |
1476 | static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, |
1477 | uint64_t pte1) | |
1478 | { | |
1479 | hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; | |
1480 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1481 | ||
1482 | if (!spapr->htab) { | |
1483 | /* There should always be a hash table when this is called */ | |
1484 | error_report("spapr_hpte_set_c called with no hash table !"); | |
1485 | return; | |
1486 | } | |
1487 | ||
1488 | /* The HW performs a non-atomic byte update */ | |
1489 | stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); | |
1490 | } | |
1491 | ||
1492 | static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1493 | uint64_t pte1) | |
1494 | { | |
1495 | hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; | |
1496 | SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1497 | ||
1498 | if (!spapr->htab) { | |
1499 | /* There should always be a hash table when this is called */ | |
1500 | error_report("spapr_hpte_set_r called with no hash table !"); | |
1501 | return; | |
1502 | } | |
1503 | ||
1504 | /* The HW performs a non-atomic byte update */ | |
1505 | stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); | |
1506 | } | |
1507 | ||
0b0b8310 | 1508 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1509 | { |
1510 | int shift; | |
1511 | ||
1512 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1513 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1514 | * that's much more than is needed for Linux guests */ | |
1515 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1516 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1517 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1518 | return shift; | |
1519 | } | |
1520 | ||
ce2918cb | 1521 | void spapr_free_hpt(SpaprMachineState *spapr) |
06ec79e8 BR |
1522 | { |
1523 | g_free(spapr->htab); | |
1524 | spapr->htab = NULL; | |
1525 | spapr->htab_shift = 0; | |
1526 | close_htab_fd(spapr); | |
1527 | } | |
1528 | ||
ce2918cb | 1529 | void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, |
2772cf6b | 1530 | Error **errp) |
7f763a5d | 1531 | { |
c5f54f3e DG |
1532 | long rc; |
1533 | ||
1534 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1535 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1536 | |
1537 | rc = kvmppc_reset_htab(shift); | |
1538 | if (rc < 0) { | |
1539 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1540 | error_setg_errno(errp, errno, | |
1541 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1542 | shift); | |
1543 | /* This is almost certainly fatal, but if the caller really | |
1544 | * wants to carry on with shift == 0, it's welcome to try */ | |
1545 | } else if (rc > 0) { | |
1546 | /* kernel-side HPT allocated */ | |
1547 | if (rc != shift) { | |
1548 | error_setg(errp, | |
1549 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1550 | shift, rc); | |
7735feda BR |
1551 | } |
1552 | ||
7f763a5d | 1553 | spapr->htab_shift = shift; |
c18ad9a5 | 1554 | spapr->htab = NULL; |
b817772a | 1555 | } else { |
c5f54f3e DG |
1556 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1557 | size_t size = 1ULL << shift; | |
1558 | int i; | |
b817772a | 1559 | |
c5f54f3e DG |
1560 | spapr->htab = qemu_memalign(size, size); |
1561 | if (!spapr->htab) { | |
1562 | error_setg_errno(errp, errno, | |
1563 | "Could not allocate HPT of order %d", shift); | |
1564 | return; | |
7735feda BR |
1565 | } |
1566 | ||
c5f54f3e DG |
1567 | memset(spapr->htab, 0, size); |
1568 | spapr->htab_shift = shift; | |
e6b8fd24 | 1569 | |
c5f54f3e DG |
1570 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1571 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1572 | } |
7f763a5d | 1573 | } |
ee4d9ecc | 1574 | /* We're setting up a hash table, so that means we're not radix */ |
176dccee | 1575 | spapr->patb_entry = 0; |
00fd075e | 1576 | spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); |
9fdf0c29 DG |
1577 | } |
1578 | ||
8897ea5a | 1579 | void spapr_setup_hpt(SpaprMachineState *spapr) |
b4db5413 | 1580 | { |
2772cf6b DG |
1581 | int hpt_shift; |
1582 | ||
087820e3 | 1583 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { |
2772cf6b DG |
1584 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); |
1585 | } else { | |
768a20f3 DG |
1586 | uint64_t current_ram_size; |
1587 | ||
1588 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1589 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1590 | } |
1591 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1592 | ||
8897ea5a | 1593 | if (kvm_enabled()) { |
6a84737c DG |
1594 | hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); |
1595 | ||
8897ea5a DG |
1596 | /* Check our RMA fits in the possible VRMA */ |
1597 | if (vrma_limit < spapr->rma_size) { | |
1598 | error_report("Unable to create %" HWADDR_PRIu | |
1599 | "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", | |
1600 | spapr->rma_size / MiB, vrma_limit / MiB); | |
1601 | exit(EXIT_FAILURE); | |
1602 | } | |
b4db5413 | 1603 | } |
b4db5413 SJS |
1604 | } |
1605 | ||
82512483 GK |
1606 | static int spapr_reset_drcs(Object *child, void *opaque) |
1607 | { | |
ce2918cb DG |
1608 | SpaprDrc *drc = |
1609 | (SpaprDrc *) object_dynamic_cast(child, | |
82512483 GK |
1610 | TYPE_SPAPR_DR_CONNECTOR); |
1611 | ||
1612 | if (drc) { | |
1613 | spapr_drc_reset(drc); | |
1614 | } | |
1615 | ||
1616 | return 0; | |
1617 | } | |
1618 | ||
a0628599 | 1619 | static void spapr_machine_reset(MachineState *machine) |
a3467baa | 1620 | { |
ce2918cb | 1621 | SpaprMachineState *spapr = SPAPR_MACHINE(machine); |
182735ef | 1622 | PowerPCCPU *first_ppc_cpu; |
744a928c | 1623 | hwaddr fdt_addr; |
997b6cfc DG |
1624 | void *fdt; |
1625 | int rc; | |
259186a7 | 1626 | |
905db916 | 1627 | kvmppc_svm_off(&error_fatal); |
9f6edd06 | 1628 | spapr_caps_apply(spapr); |
33face6b | 1629 | |
1481fe5f LV |
1630 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1631 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
ad99d04c DG |
1632 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
1633 | spapr->max_compat_pvr)) { | |
79825f4d BH |
1634 | /* |
1635 | * If using KVM with radix mode available, VCPUs can be started | |
b4db5413 | 1636 | * without a HPT because KVM will start them in radix mode. |
79825f4d BH |
1637 | * Set the GR bit in PATE so that we know there is no HPT. |
1638 | */ | |
1639 | spapr->patb_entry = PATE1_GR; | |
00fd075e | 1640 | spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); |
b4db5413 | 1641 | } else { |
8897ea5a | 1642 | spapr_setup_hpt(spapr); |
c5f54f3e | 1643 | } |
a3467baa | 1644 | |
25c9780d DG |
1645 | qemu_devices_reset(); |
1646 | ||
087820e3 GK |
1647 | spapr_ovec_cleanup(spapr->ov5_cas); |
1648 | spapr->ov5_cas = spapr_ovec_new(); | |
9012a53f | 1649 | |
087820e3 | 1650 | ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); |
9012a53f | 1651 | |
b2e22477 CLG |
1652 | /* |
1653 | * This is fixing some of the default configuration of the XIVE | |
1654 | * devices. To be called after the reset of the machine devices. | |
1655 | */ | |
1656 | spapr_irq_reset(spapr, &error_fatal); | |
1657 | ||
23ff81bd GK |
1658 | /* |
1659 | * There is no CAS under qtest. Simulate one to please the code that | |
1660 | * depends on spapr->ov5_cas. This is especially needed to test device | |
1661 | * unplug, so we do that before resetting the DRCs. | |
1662 | */ | |
1663 | if (qtest_enabled()) { | |
1664 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1665 | spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); | |
1666 | } | |
1667 | ||
82512483 GK |
1668 | /* DRC reset may cause a device to be unplugged. This will cause troubles |
1669 | * if this device is used by another device (eg, a running vhost backend | |
1670 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1671 | * situations, we reset DRCs after all devices have been reset. | |
1672 | */ | |
1673 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1674 | ||
56258174 | 1675 | spapr_clear_pending_events(spapr); |
a3467baa | 1676 | |
b7d1f77a BH |
1677 | /* |
1678 | * We place the device tree and RTAS just below either the top of the RMA, | |
df269271 | 1679 | * or just below 2GB, whichever is lower, so that it can be |
b7d1f77a BH |
1680 | * processed with 32-bit real mode code if necessary |
1681 | */ | |
744a928c | 1682 | fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; |
b7d1f77a | 1683 | |
97b32a6a | 1684 | fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); |
a3467baa | 1685 | |
997b6cfc DG |
1686 | rc = fdt_pack(fdt); |
1687 | ||
1688 | /* Should only fail if we've built a corrupted tree */ | |
1689 | assert(rc == 0); | |
1690 | ||
997b6cfc DG |
1691 | /* Load the fdt */ |
1692 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1693 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
fea35ca4 AK |
1694 | g_free(spapr->fdt_blob); |
1695 | spapr->fdt_size = fdt_totalsize(fdt); | |
1696 | spapr->fdt_initial_size = spapr->fdt_size; | |
1697 | spapr->fdt_blob = fdt; | |
997b6cfc | 1698 | |
a3467baa | 1699 | /* Set up the entry state */ |
395a20d3 | 1700 | spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); |
182735ef | 1701 | first_ppc_cpu->env.gpr[5] = 0; |
a3467baa | 1702 | |
edfdbf9c | 1703 | spapr->fwnmi_system_reset_addr = -1; |
8af7e1fe NP |
1704 | spapr->fwnmi_machine_check_addr = -1; |
1705 | spapr->fwnmi_machine_check_interlock = -1; | |
9ac703ac AP |
1706 | |
1707 | /* Signal all vCPUs waiting on this condition */ | |
8af7e1fe | 1708 | qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); |
2500fb42 AP |
1709 | |
1710 | migrate_del_blocker(spapr->fwnmi_migration_blocker); | |
a3467baa DG |
1711 | } |
1712 | ||
ce2918cb | 1713 | static void spapr_create_nvram(SpaprMachineState *spapr) |
639e8102 | 1714 | { |
2ff3de68 | 1715 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1716 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1717 | |
3978b863 | 1718 | if (dinfo) { |
6231a6da MA |
1719 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1720 | &error_fatal); | |
639e8102 DG |
1721 | } |
1722 | ||
1723 | qdev_init_nofail(dev); | |
1724 | ||
ce2918cb | 1725 | spapr->nvram = (struct SpaprNvram *)dev; |
639e8102 DG |
1726 | } |
1727 | ||
ce2918cb | 1728 | static void spapr_rtc_create(SpaprMachineState *spapr) |
28df36a1 | 1729 | { |
f6d4dca8 TH |
1730 | object_initialize_child(OBJECT(spapr), "rtc", |
1731 | &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, | |
1732 | &error_fatal, NULL); | |
147ff807 CLG |
1733 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", |
1734 | &error_fatal); | |
1735 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
d2623129 | 1736 | "date"); |
28df36a1 DG |
1737 | } |
1738 | ||
8c57b867 | 1739 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1740 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1741 | { |
8c57b867 | 1742 | switch (vga_interface_type) { |
8c57b867 | 1743 | case VGA_NONE: |
7effdaa3 MW |
1744 | return false; |
1745 | case VGA_DEVICE: | |
1746 | return true; | |
1ddcae82 | 1747 | case VGA_STD: |
b798c190 | 1748 | case VGA_VIRTIO: |
6e66d0c6 | 1749 | case VGA_CIRRUS: |
1ddcae82 | 1750 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1751 | default: |
14c6a894 DG |
1752 | error_setg(errp, |
1753 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1754 | return false; | |
f28359d8 | 1755 | } |
f28359d8 LZ |
1756 | } |
1757 | ||
4e5fe368 SJS |
1758 | static int spapr_pre_load(void *opaque) |
1759 | { | |
1760 | int rc; | |
1761 | ||
1762 | rc = spapr_caps_pre_load(opaque); | |
1763 | if (rc) { | |
1764 | return rc; | |
1765 | } | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
880ae7de DG |
1770 | static int spapr_post_load(void *opaque, int version_id) |
1771 | { | |
ce2918cb | 1772 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
880ae7de DG |
1773 | int err = 0; |
1774 | ||
be85537d DG |
1775 | err = spapr_caps_post_migration(spapr); |
1776 | if (err) { | |
1777 | return err; | |
1778 | } | |
1779 | ||
e502202c CLG |
1780 | /* |
1781 | * In earlier versions, there was no separate qdev for the PAPR | |
880ae7de DG |
1782 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1783 | * So when migrating from those versions, poke the incoming offset | |
e502202c CLG |
1784 | * value into the RTC device |
1785 | */ | |
880ae7de | 1786 | if (version_id < 3) { |
147ff807 | 1787 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
e502202c CLG |
1788 | if (err) { |
1789 | return err; | |
1790 | } | |
880ae7de DG |
1791 | } |
1792 | ||
0c86b2df | 1793 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 | 1794 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
79825f4d | 1795 | bool radix = !!(spapr->patb_entry & PATE1_GR); |
d39c90f5 | 1796 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); |
00fd075e BH |
1797 | |
1798 | /* | |
1799 | * Update LPCR:HR and UPRT as they may not be set properly in | |
1800 | * the stream | |
1801 | */ | |
1802 | spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, | |
1803 | LPCR_HR | LPCR_UPRT); | |
d39c90f5 BR |
1804 | |
1805 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1806 | if (err) { | |
1807 | error_report("Process table config unsupported by the host"); | |
1808 | return -EINVAL; | |
1809 | } | |
1810 | } | |
1811 | ||
1c53b06c CLG |
1812 | err = spapr_irq_post_load(spapr, version_id); |
1813 | if (err) { | |
1814 | return err; | |
1815 | } | |
1816 | ||
880ae7de DG |
1817 | return err; |
1818 | } | |
1819 | ||
4e5fe368 SJS |
1820 | static int spapr_pre_save(void *opaque) |
1821 | { | |
1822 | int rc; | |
1823 | ||
1824 | rc = spapr_caps_pre_save(opaque); | |
1825 | if (rc) { | |
1826 | return rc; | |
1827 | } | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
880ae7de DG |
1832 | static bool version_before_3(void *opaque, int version_id) |
1833 | { | |
1834 | return version_id < 3; | |
1835 | } | |
1836 | ||
fd38804b DHB |
1837 | static bool spapr_pending_events_needed(void *opaque) |
1838 | { | |
ce2918cb | 1839 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
fd38804b DHB |
1840 | return !QTAILQ_EMPTY(&spapr->pending_events); |
1841 | } | |
1842 | ||
1843 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1844 | .name = "spapr_event_log_entry", | |
1845 | .version_id = 1, | |
1846 | .minimum_version_id = 1, | |
1847 | .fields = (VMStateField[]) { | |
ce2918cb DG |
1848 | VMSTATE_UINT32(summary, SpaprEventLogEntry), |
1849 | VMSTATE_UINT32(extended_length, SpaprEventLogEntry), | |
1850 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, | |
5341258e | 1851 | NULL, extended_length), |
fd38804b DHB |
1852 | VMSTATE_END_OF_LIST() |
1853 | }, | |
1854 | }; | |
1855 | ||
1856 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1857 | .name = "spapr_pending_events", | |
1858 | .version_id = 1, | |
1859 | .minimum_version_id = 1, | |
1860 | .needed = spapr_pending_events_needed, | |
1861 | .fields = (VMStateField[]) { | |
ce2918cb DG |
1862 | VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, |
1863 | vmstate_spapr_event_entry, SpaprEventLogEntry, next), | |
fd38804b DHB |
1864 | VMSTATE_END_OF_LIST() |
1865 | }, | |
1866 | }; | |
1867 | ||
62ef3760 MR |
1868 | static bool spapr_ov5_cas_needed(void *opaque) |
1869 | { | |
ce2918cb DG |
1870 | SpaprMachineState *spapr = opaque; |
1871 | SpaprOptionVector *ov5_mask = spapr_ovec_new(); | |
62ef3760 MR |
1872 | bool cas_needed; |
1873 | ||
ce2918cb | 1874 | /* Prior to the introduction of SpaprOptionVector, we had two option |
62ef3760 MR |
1875 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. |
1876 | * Both of these options encode machine topology into the device-tree | |
1877 | * in such a way that the now-booted OS should still be able to interact | |
1878 | * appropriately with QEMU regardless of what options were actually | |
1879 | * negotiatied on the source side. | |
1880 | * | |
1881 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1882 | * are the only options available on the current machine/platform. | |
1883 | * Since these are the only options available for pseries-2.7 and | |
1884 | * earlier, this allows us to maintain old->new/new->old migration | |
1885 | * compatibility. | |
1886 | * | |
1887 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1888 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1889 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1890 | * of the actual CAS-negotiated values to continue working properly. For | |
1891 | * example, availability of memory unplug depends on knowing whether | |
1892 | * OV5_HP_EVT was negotiated via CAS. | |
1893 | * | |
1894 | * Thus, for any cases where the set of available CAS-negotiatable | |
1895 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
aef19c04 GK |
1896 | * include the CAS-negotiated options in the migration stream, unless |
1897 | * if they affect boot time behaviour only. | |
62ef3760 MR |
1898 | */ |
1899 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1900 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
aef19c04 | 1901 | spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); |
62ef3760 | 1902 | |
d1d32d62 DG |
1903 | /* We need extra information if we have any bits outside the mask |
1904 | * defined above */ | |
1905 | cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); | |
62ef3760 MR |
1906 | |
1907 | spapr_ovec_cleanup(ov5_mask); | |
62ef3760 MR |
1908 | |
1909 | return cas_needed; | |
1910 | } | |
1911 | ||
1912 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1913 | .name = "spapr_option_vector_ov5_cas", | |
1914 | .version_id = 1, | |
1915 | .minimum_version_id = 1, | |
1916 | .needed = spapr_ov5_cas_needed, | |
1917 | .fields = (VMStateField[]) { | |
ce2918cb DG |
1918 | VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, |
1919 | vmstate_spapr_ovec, SpaprOptionVector), | |
62ef3760 MR |
1920 | VMSTATE_END_OF_LIST() |
1921 | }, | |
1922 | }; | |
1923 | ||
9861bb3e SJS |
1924 | static bool spapr_patb_entry_needed(void *opaque) |
1925 | { | |
ce2918cb | 1926 | SpaprMachineState *spapr = opaque; |
9861bb3e SJS |
1927 | |
1928 | return !!spapr->patb_entry; | |
1929 | } | |
1930 | ||
1931 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1932 | .name = "spapr_patb_entry", | |
1933 | .version_id = 1, | |
1934 | .minimum_version_id = 1, | |
1935 | .needed = spapr_patb_entry_needed, | |
1936 | .fields = (VMStateField[]) { | |
ce2918cb | 1937 | VMSTATE_UINT64(patb_entry, SpaprMachineState), |
9861bb3e SJS |
1938 | VMSTATE_END_OF_LIST() |
1939 | }, | |
1940 | }; | |
1941 | ||
82cffa2e CLG |
1942 | static bool spapr_irq_map_needed(void *opaque) |
1943 | { | |
ce2918cb | 1944 | SpaprMachineState *spapr = opaque; |
82cffa2e CLG |
1945 | |
1946 | return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); | |
1947 | } | |
1948 | ||
1949 | static const VMStateDescription vmstate_spapr_irq_map = { | |
1950 | .name = "spapr_irq_map", | |
1951 | .version_id = 1, | |
1952 | .minimum_version_id = 1, | |
1953 | .needed = spapr_irq_map_needed, | |
1954 | .fields = (VMStateField[]) { | |
ce2918cb | 1955 | VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), |
82cffa2e CLG |
1956 | VMSTATE_END_OF_LIST() |
1957 | }, | |
1958 | }; | |
1959 | ||
fea35ca4 AK |
1960 | static bool spapr_dtb_needed(void *opaque) |
1961 | { | |
ce2918cb | 1962 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); |
fea35ca4 AK |
1963 | |
1964 | return smc->update_dt_enabled; | |
1965 | } | |
1966 | ||
1967 | static int spapr_dtb_pre_load(void *opaque) | |
1968 | { | |
ce2918cb | 1969 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; |
fea35ca4 AK |
1970 | |
1971 | g_free(spapr->fdt_blob); | |
1972 | spapr->fdt_blob = NULL; | |
1973 | spapr->fdt_size = 0; | |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | static const VMStateDescription vmstate_spapr_dtb = { | |
1979 | .name = "spapr_dtb", | |
1980 | .version_id = 1, | |
1981 | .minimum_version_id = 1, | |
1982 | .needed = spapr_dtb_needed, | |
1983 | .pre_load = spapr_dtb_pre_load, | |
1984 | .fields = (VMStateField[]) { | |
ce2918cb DG |
1985 | VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), |
1986 | VMSTATE_UINT32(fdt_size, SpaprMachineState), | |
1987 | VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, | |
fea35ca4 AK |
1988 | fdt_size), |
1989 | VMSTATE_END_OF_LIST() | |
1990 | }, | |
1991 | }; | |
1992 | ||
2500fb42 AP |
1993 | static bool spapr_fwnmi_needed(void *opaque) |
1994 | { | |
1995 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; | |
1996 | ||
8af7e1fe | 1997 | return spapr->fwnmi_machine_check_addr != -1; |
2500fb42 AP |
1998 | } |
1999 | ||
2000 | static int spapr_fwnmi_pre_save(void *opaque) | |
2001 | { | |
2002 | SpaprMachineState *spapr = (SpaprMachineState *)opaque; | |
2003 | ||
2004 | /* | |
2005 | * Check if machine check handling is in progress and print a | |
2006 | * warning message. | |
2007 | */ | |
8af7e1fe | 2008 | if (spapr->fwnmi_machine_check_interlock != -1) { |
2500fb42 AP |
2009 | warn_report("A machine check is being handled during migration. The" |
2010 | "handler may run and log hardware error on the destination"); | |
2011 | } | |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
8af7e1fe NP |
2016 | static const VMStateDescription vmstate_spapr_fwnmi = { |
2017 | .name = "spapr_fwnmi", | |
2500fb42 AP |
2018 | .version_id = 1, |
2019 | .minimum_version_id = 1, | |
2020 | .needed = spapr_fwnmi_needed, | |
2021 | .pre_save = spapr_fwnmi_pre_save, | |
2022 | .fields = (VMStateField[]) { | |
edfdbf9c | 2023 | VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), |
8af7e1fe NP |
2024 | VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), |
2025 | VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), | |
2500fb42 AP |
2026 | VMSTATE_END_OF_LIST() |
2027 | }, | |
2028 | }; | |
2029 | ||
4be21d56 DG |
2030 | static const VMStateDescription vmstate_spapr = { |
2031 | .name = "spapr", | |
880ae7de | 2032 | .version_id = 3, |
4be21d56 | 2033 | .minimum_version_id = 1, |
4e5fe368 | 2034 | .pre_load = spapr_pre_load, |
880ae7de | 2035 | .post_load = spapr_post_load, |
4e5fe368 | 2036 | .pre_save = spapr_pre_save, |
3aff6c2f | 2037 | .fields = (VMStateField[]) { |
880ae7de DG |
2038 | /* used to be @next_irq */ |
2039 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
2040 | |
2041 | /* RTC offset */ | |
ce2918cb | 2042 | VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), |
880ae7de | 2043 | |
ce2918cb | 2044 | VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), |
4be21d56 DG |
2045 | VMSTATE_END_OF_LIST() |
2046 | }, | |
62ef3760 MR |
2047 | .subsections = (const VMStateDescription*[]) { |
2048 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 2049 | &vmstate_spapr_patb_entry, |
fd38804b | 2050 | &vmstate_spapr_pending_events, |
4e5fe368 SJS |
2051 | &vmstate_spapr_cap_htm, |
2052 | &vmstate_spapr_cap_vsx, | |
2053 | &vmstate_spapr_cap_dfp, | |
8f38eaf8 | 2054 | &vmstate_spapr_cap_cfpc, |
09114fd8 | 2055 | &vmstate_spapr_cap_sbbc, |
4be8d4e7 | 2056 | &vmstate_spapr_cap_ibs, |
64d4a534 | 2057 | &vmstate_spapr_cap_hpt_maxpagesize, |
82cffa2e | 2058 | &vmstate_spapr_irq_map, |
b9a477b7 | 2059 | &vmstate_spapr_cap_nested_kvm_hv, |
fea35ca4 | 2060 | &vmstate_spapr_dtb, |
c982f5cf | 2061 | &vmstate_spapr_cap_large_decr, |
8ff43ee4 | 2062 | &vmstate_spapr_cap_ccf_assist, |
9d953ce4 | 2063 | &vmstate_spapr_cap_fwnmi, |
8af7e1fe | 2064 | &vmstate_spapr_fwnmi, |
62ef3760 MR |
2065 | NULL |
2066 | } | |
4be21d56 DG |
2067 | }; |
2068 | ||
4be21d56 DG |
2069 | static int htab_save_setup(QEMUFile *f, void *opaque) |
2070 | { | |
ce2918cb | 2071 | SpaprMachineState *spapr = opaque; |
4be21d56 | 2072 | |
4be21d56 | 2073 | /* "Iteration" header */ |
3a384297 BR |
2074 | if (!spapr->htab_shift) { |
2075 | qemu_put_be32(f, -1); | |
2076 | } else { | |
2077 | qemu_put_be32(f, spapr->htab_shift); | |
2078 | } | |
4be21d56 | 2079 | |
e68cb8b4 AK |
2080 | if (spapr->htab) { |
2081 | spapr->htab_save_index = 0; | |
2082 | spapr->htab_first_pass = true; | |
2083 | } else { | |
3a384297 BR |
2084 | if (spapr->htab_shift) { |
2085 | assert(kvm_enabled()); | |
2086 | } | |
e68cb8b4 AK |
2087 | } |
2088 | ||
2089 | ||
4be21d56 DG |
2090 | return 0; |
2091 | } | |
2092 | ||
ce2918cb | 2093 | static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, |
332f7721 GK |
2094 | int chunkstart, int n_valid, int n_invalid) |
2095 | { | |
2096 | qemu_put_be32(f, chunkstart); | |
2097 | qemu_put_be16(f, n_valid); | |
2098 | qemu_put_be16(f, n_invalid); | |
2099 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
2100 | HASH_PTE_SIZE_64 * n_valid); | |
2101 | } | |
2102 | ||
2103 | static void htab_save_end_marker(QEMUFile *f) | |
2104 | { | |
2105 | qemu_put_be32(f, 0); | |
2106 | qemu_put_be16(f, 0); | |
2107 | qemu_put_be16(f, 0); | |
2108 | } | |
2109 | ||
ce2918cb | 2110 | static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, |
4be21d56 DG |
2111 | int64_t max_ns) |
2112 | { | |
378bc217 | 2113 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
2114 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
2115 | int index = spapr->htab_save_index; | |
bc72ad67 | 2116 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
2117 | |
2118 | assert(spapr->htab_first_pass); | |
2119 | ||
2120 | do { | |
2121 | int chunkstart; | |
2122 | ||
2123 | /* Consume invalid HPTEs */ | |
2124 | while ((index < htabslots) | |
2125 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 2126 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2127 | index++; |
4be21d56 DG |
2128 | } |
2129 | ||
2130 | /* Consume valid HPTEs */ | |
2131 | chunkstart = index; | |
338c25b6 | 2132 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 2133 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 2134 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2135 | index++; |
4be21d56 DG |
2136 | } |
2137 | ||
2138 | if (index > chunkstart) { | |
2139 | int n_valid = index - chunkstart; | |
2140 | ||
332f7721 | 2141 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 2142 | |
378bc217 DG |
2143 | if (has_timeout && |
2144 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
2145 | break; |
2146 | } | |
2147 | } | |
2148 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
2149 | ||
2150 | if (index >= htabslots) { | |
2151 | assert(index == htabslots); | |
2152 | index = 0; | |
2153 | spapr->htab_first_pass = false; | |
2154 | } | |
2155 | spapr->htab_save_index = index; | |
2156 | } | |
2157 | ||
ce2918cb | 2158 | static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, |
e68cb8b4 | 2159 | int64_t max_ns) |
4be21d56 DG |
2160 | { |
2161 | bool final = max_ns < 0; | |
2162 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
2163 | int examined = 0, sent = 0; | |
2164 | int index = spapr->htab_save_index; | |
bc72ad67 | 2165 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
2166 | |
2167 | assert(!spapr->htab_first_pass); | |
2168 | ||
2169 | do { | |
2170 | int chunkstart, invalidstart; | |
2171 | ||
2172 | /* Consume non-dirty HPTEs */ | |
2173 | while ((index < htabslots) | |
2174 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
2175 | index++; | |
2176 | examined++; | |
2177 | } | |
2178 | ||
2179 | chunkstart = index; | |
2180 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 2181 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
2182 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2183 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
2184 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2185 | index++; | |
2186 | examined++; | |
2187 | } | |
2188 | ||
2189 | invalidstart = index; | |
2190 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 2191 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
2192 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2193 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
2194 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2195 | index++; | |
2196 | examined++; | |
2197 | } | |
2198 | ||
2199 | if (index > chunkstart) { | |
2200 | int n_valid = invalidstart - chunkstart; | |
2201 | int n_invalid = index - invalidstart; | |
2202 | ||
332f7721 | 2203 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
2204 | sent += index - chunkstart; |
2205 | ||
bc72ad67 | 2206 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
2207 | break; |
2208 | } | |
2209 | } | |
2210 | ||
2211 | if (examined >= htabslots) { | |
2212 | break; | |
2213 | } | |
2214 | ||
2215 | if (index >= htabslots) { | |
2216 | assert(index == htabslots); | |
2217 | index = 0; | |
2218 | } | |
2219 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
2220 | ||
2221 | if (index >= htabslots) { | |
2222 | assert(index == htabslots); | |
2223 | index = 0; | |
2224 | } | |
2225 | ||
2226 | spapr->htab_save_index = index; | |
2227 | ||
e68cb8b4 | 2228 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
2229 | } |
2230 | ||
e68cb8b4 AK |
2231 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
2232 | #define MAX_KVM_BUF_SIZE 2048 | |
2233 | ||
4be21d56 DG |
2234 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
2235 | { | |
ce2918cb | 2236 | SpaprMachineState *spapr = opaque; |
715c5407 | 2237 | int fd; |
e68cb8b4 | 2238 | int rc = 0; |
4be21d56 DG |
2239 | |
2240 | /* Iteration header */ | |
3a384297 BR |
2241 | if (!spapr->htab_shift) { |
2242 | qemu_put_be32(f, -1); | |
e8cd4247 | 2243 | return 1; |
3a384297 BR |
2244 | } else { |
2245 | qemu_put_be32(f, 0); | |
2246 | } | |
4be21d56 | 2247 | |
e68cb8b4 AK |
2248 | if (!spapr->htab) { |
2249 | assert(kvm_enabled()); | |
2250 | ||
715c5407 DG |
2251 | fd = get_htab_fd(spapr); |
2252 | if (fd < 0) { | |
2253 | return fd; | |
01a57972 SMJ |
2254 | } |
2255 | ||
715c5407 | 2256 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
2257 | if (rc < 0) { |
2258 | return rc; | |
2259 | } | |
2260 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
2261 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
2262 | } else { | |
e68cb8b4 | 2263 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
2264 | } |
2265 | ||
332f7721 | 2266 | htab_save_end_marker(f); |
4be21d56 | 2267 | |
e68cb8b4 | 2268 | return rc; |
4be21d56 DG |
2269 | } |
2270 | ||
2271 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
2272 | { | |
ce2918cb | 2273 | SpaprMachineState *spapr = opaque; |
715c5407 | 2274 | int fd; |
4be21d56 DG |
2275 | |
2276 | /* Iteration header */ | |
3a384297 BR |
2277 | if (!spapr->htab_shift) { |
2278 | qemu_put_be32(f, -1); | |
2279 | return 0; | |
2280 | } else { | |
2281 | qemu_put_be32(f, 0); | |
2282 | } | |
4be21d56 | 2283 | |
e68cb8b4 AK |
2284 | if (!spapr->htab) { |
2285 | int rc; | |
2286 | ||
2287 | assert(kvm_enabled()); | |
2288 | ||
715c5407 DG |
2289 | fd = get_htab_fd(spapr); |
2290 | if (fd < 0) { | |
2291 | return fd; | |
01a57972 SMJ |
2292 | } |
2293 | ||
715c5407 | 2294 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
2295 | if (rc < 0) { |
2296 | return rc; | |
2297 | } | |
e68cb8b4 | 2298 | } else { |
378bc217 DG |
2299 | if (spapr->htab_first_pass) { |
2300 | htab_save_first_pass(f, spapr, -1); | |
2301 | } | |
e68cb8b4 AK |
2302 | htab_save_later_pass(f, spapr, -1); |
2303 | } | |
4be21d56 DG |
2304 | |
2305 | /* End marker */ | |
332f7721 | 2306 | htab_save_end_marker(f); |
4be21d56 DG |
2307 | |
2308 | return 0; | |
2309 | } | |
2310 | ||
2311 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2312 | { | |
ce2918cb | 2313 | SpaprMachineState *spapr = opaque; |
4be21d56 | 2314 | uint32_t section_hdr; |
e68cb8b4 | 2315 | int fd = -1; |
14b0d748 | 2316 | Error *local_err = NULL; |
4be21d56 DG |
2317 | |
2318 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2319 | error_report("htab_load() bad version"); |
4be21d56 DG |
2320 | return -EINVAL; |
2321 | } | |
2322 | ||
2323 | section_hdr = qemu_get_be32(f); | |
2324 | ||
3a384297 BR |
2325 | if (section_hdr == -1) { |
2326 | spapr_free_hpt(spapr); | |
2327 | return 0; | |
2328 | } | |
2329 | ||
4be21d56 | 2330 | if (section_hdr) { |
c5f54f3e DG |
2331 | /* First section gives the htab size */ |
2332 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2333 | if (local_err) { | |
2334 | error_report_err(local_err); | |
4be21d56 DG |
2335 | return -EINVAL; |
2336 | } | |
2337 | return 0; | |
2338 | } | |
2339 | ||
e68cb8b4 AK |
2340 | if (!spapr->htab) { |
2341 | assert(kvm_enabled()); | |
2342 | ||
14b0d748 | 2343 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2344 | if (fd < 0) { |
14b0d748 | 2345 | error_report_err(local_err); |
82be8e73 | 2346 | return fd; |
e68cb8b4 AK |
2347 | } |
2348 | } | |
2349 | ||
4be21d56 DG |
2350 | while (true) { |
2351 | uint32_t index; | |
2352 | uint16_t n_valid, n_invalid; | |
2353 | ||
2354 | index = qemu_get_be32(f); | |
2355 | n_valid = qemu_get_be16(f); | |
2356 | n_invalid = qemu_get_be16(f); | |
2357 | ||
2358 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2359 | /* End of Stream */ | |
2360 | break; | |
2361 | } | |
2362 | ||
e68cb8b4 | 2363 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2364 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2365 | /* Bad index in stream */ | |
98a5d100 DG |
2366 | error_report( |
2367 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2368 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2369 | return -EINVAL; |
2370 | } | |
2371 | ||
e68cb8b4 AK |
2372 | if (spapr->htab) { |
2373 | if (n_valid) { | |
2374 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2375 | HASH_PTE_SIZE_64 * n_valid); | |
2376 | } | |
2377 | if (n_invalid) { | |
2378 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2379 | HASH_PTE_SIZE_64 * n_invalid); | |
2380 | } | |
2381 | } else { | |
2382 | int rc; | |
2383 | ||
2384 | assert(fd >= 0); | |
2385 | ||
2386 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2387 | if (rc < 0) { | |
2388 | return rc; | |
2389 | } | |
4be21d56 DG |
2390 | } |
2391 | } | |
2392 | ||
e68cb8b4 AK |
2393 | if (!spapr->htab) { |
2394 | assert(fd >= 0); | |
2395 | close(fd); | |
2396 | } | |
2397 | ||
4be21d56 DG |
2398 | return 0; |
2399 | } | |
2400 | ||
70f794fc | 2401 | static void htab_save_cleanup(void *opaque) |
c573fc03 | 2402 | { |
ce2918cb | 2403 | SpaprMachineState *spapr = opaque; |
c573fc03 TH |
2404 | |
2405 | close_htab_fd(spapr); | |
2406 | } | |
2407 | ||
4be21d56 | 2408 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2409 | .save_setup = htab_save_setup, |
4be21d56 | 2410 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2411 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2412 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2413 | .load_state = htab_load, |
2414 | }; | |
2415 | ||
5b2128d2 AG |
2416 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2417 | Error **errp) | |
2418 | { | |
c86c1aff | 2419 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2420 | machine->boot_order = g_strdup(boot_device); |
2421 | } | |
2422 | ||
ce2918cb | 2423 | static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) |
224245bf DG |
2424 | { |
2425 | MachineState *machine = MACHINE(spapr); | |
2426 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2427 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2428 | int i; |
2429 | ||
2430 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2431 | uint64_t addr; |
2432 | ||
b0c14ec4 | 2433 | addr = i * lmb_size + machine->device_memory->base; |
6caf3ac6 DG |
2434 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2435 | addr / lmb_size); | |
224245bf DG |
2436 | } |
2437 | } | |
2438 | ||
2439 | /* | |
2440 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2441 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2442 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2443 | */ | |
7c150d6f | 2444 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2445 | { |
2446 | int i; | |
2447 | ||
7c150d6f DG |
2448 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2449 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
ab3dd749 | 2450 | " is not aligned to %" PRIu64 " MiB", |
7c150d6f | 2451 | machine->ram_size, |
d23b6caa | 2452 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f DG |
2453 | return; |
2454 | } | |
2455 | ||
2456 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2457 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
ab3dd749 | 2458 | " is not aligned to %" PRIu64 " MiB", |
7c150d6f | 2459 | machine->ram_size, |
d23b6caa | 2460 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f | 2461 | return; |
224245bf DG |
2462 | } |
2463 | ||
aa570207 | 2464 | for (i = 0; i < machine->numa_state->num_nodes; i++) { |
7e721e7b | 2465 | if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { |
7c150d6f DG |
2466 | error_setg(errp, |
2467 | "Node %d memory size 0x%" PRIx64 | |
ab3dd749 | 2468 | " is not aligned to %" PRIu64 " MiB", |
7e721e7b | 2469 | i, machine->numa_state->nodes[i].node_mem, |
d23b6caa | 2470 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f | 2471 | return; |
224245bf DG |
2472 | } |
2473 | } | |
2474 | } | |
2475 | ||
535455fd IM |
2476 | /* find cpu slot in machine->possible_cpus by core_id */ |
2477 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2478 | { | |
fe6b6346 | 2479 | int index = id / ms->smp.threads; |
535455fd IM |
2480 | |
2481 | if (index >= ms->possible_cpus->len) { | |
2482 | return NULL; | |
2483 | } | |
2484 | if (idx) { | |
2485 | *idx = index; | |
2486 | } | |
2487 | return &ms->possible_cpus->cpus[index]; | |
2488 | } | |
2489 | ||
ce2918cb | 2490 | static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) |
fa98fbfc | 2491 | { |
fe6b6346 | 2492 | MachineState *ms = MACHINE(spapr); |
29cb4187 | 2493 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
fa98fbfc SB |
2494 | Error *local_err = NULL; |
2495 | bool vsmt_user = !!spapr->vsmt; | |
2496 | int kvm_smt = kvmppc_smt_threads(); | |
2497 | int ret; | |
fe6b6346 | 2498 | unsigned int smp_threads = ms->smp.threads; |
fa98fbfc SB |
2499 | |
2500 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2501 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2502 | "on a pseries machine"); | |
2503 | goto out; | |
2504 | } | |
2505 | if (!is_power_of_2(smp_threads)) { | |
2506 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2507 | "machine because it must be a power of 2", smp_threads); | |
2508 | goto out; | |
2509 | } | |
2510 | ||
2511 | /* Detemine the VSMT mode to use: */ | |
2512 | if (vsmt_user) { | |
2513 | if (spapr->vsmt < smp_threads) { | |
2514 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2515 | " because it must be >= threads/core (%d)", | |
2516 | spapr->vsmt, smp_threads); | |
2517 | goto out; | |
2518 | } | |
2519 | /* In this case, spapr->vsmt has been set by the command line */ | |
29cb4187 | 2520 | } else if (!smc->smp_threads_vsmt) { |
8904e5a7 DG |
2521 | /* |
2522 | * Default VSMT value is tricky, because we need it to be as | |
2523 | * consistent as possible (for migration), but this requires | |
2524 | * changing it for at least some existing cases. We pick 8 as | |
2525 | * the value that we'd get with KVM on POWER8, the | |
2526 | * overwhelmingly common case in production systems. | |
2527 | */ | |
4ad64cbd | 2528 | spapr->vsmt = MAX(8, smp_threads); |
29cb4187 GK |
2529 | } else { |
2530 | spapr->vsmt = smp_threads; | |
fa98fbfc SB |
2531 | } |
2532 | ||
2533 | /* KVM: If necessary, set the SMT mode: */ | |
2534 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2535 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2536 | if (ret) { | |
1f20f2e0 | 2537 | /* Looks like KVM isn't able to change VSMT mode */ |
fa98fbfc SB |
2538 | error_setg(&local_err, |
2539 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2540 | spapr->vsmt, ret); | |
1f20f2e0 DG |
2541 | /* We can live with that if the default one is big enough |
2542 | * for the number of threads, and a submultiple of the one | |
2543 | * we want. In this case we'll waste some vcpu ids, but | |
2544 | * behaviour will be correct */ | |
2545 | if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { | |
2546 | warn_report_err(local_err); | |
2547 | local_err = NULL; | |
2548 | goto out; | |
2549 | } else { | |
2550 | if (!vsmt_user) { | |
2551 | error_append_hint(&local_err, | |
2552 | "On PPC, a VM with %d threads/core" | |
2553 | " on a host with %d threads/core" | |
2554 | " requires the use of VSMT mode %d.\n", | |
2555 | smp_threads, kvm_smt, spapr->vsmt); | |
2556 | } | |
cdcca22a | 2557 | kvmppc_error_append_smt_possible_hint(&local_err); |
1f20f2e0 | 2558 | goto out; |
fa98fbfc | 2559 | } |
fa98fbfc SB |
2560 | } |
2561 | } | |
2562 | /* else TCG: nothing to do currently */ | |
2563 | out: | |
2564 | error_propagate(errp, local_err); | |
2565 | } | |
2566 | ||
ce2918cb | 2567 | static void spapr_init_cpus(SpaprMachineState *spapr) |
1a5008fc GK |
2568 | { |
2569 | MachineState *machine = MACHINE(spapr); | |
2570 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
ce2918cb | 2571 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
1a5008fc GK |
2572 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); |
2573 | const CPUArchIdList *possible_cpus; | |
fe6b6346 LX |
2574 | unsigned int smp_cpus = machine->smp.cpus; |
2575 | unsigned int smp_threads = machine->smp.threads; | |
2576 | unsigned int max_cpus = machine->smp.max_cpus; | |
1a5008fc GK |
2577 | int boot_cores_nr = smp_cpus / smp_threads; |
2578 | int i; | |
2579 | ||
2580 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
2581 | if (mc->has_hotpluggable_cpus) { | |
2582 | if (smp_cpus % smp_threads) { | |
2583 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2584 | smp_cpus, smp_threads); | |
2585 | exit(1); | |
2586 | } | |
2587 | if (max_cpus % smp_threads) { | |
2588 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2589 | max_cpus, smp_threads); | |
2590 | exit(1); | |
2591 | } | |
2592 | } else { | |
2593 | if (max_cpus != smp_cpus) { | |
2594 | error_report("This machine version does not support CPU hotplug"); | |
2595 | exit(1); | |
2596 | } | |
2597 | boot_cores_nr = possible_cpus->len; | |
2598 | } | |
2599 | ||
1a5008fc GK |
2600 | if (smc->pre_2_10_has_unused_icps) { |
2601 | int i; | |
2602 | ||
1a518e76 | 2603 | for (i = 0; i < spapr_max_server_number(spapr); i++) { |
1a5008fc GK |
2604 | /* Dummy entries get deregistered when real ICPState objects |
2605 | * are registered during CPU core hotplug. | |
2606 | */ | |
2607 | pre_2_10_vmstate_register_dummy_icp(i); | |
2608 | } | |
2609 | } | |
2610 | ||
2611 | for (i = 0; i < possible_cpus->len; i++) { | |
2612 | int core_id = i * smp_threads; | |
2613 | ||
2614 | if (mc->has_hotpluggable_cpus) { | |
2615 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, | |
2616 | spapr_vcpu_id(spapr, core_id)); | |
2617 | } | |
2618 | ||
2619 | if (i < boot_cores_nr) { | |
2620 | Object *core = object_new(type); | |
2621 | int nr_threads = smp_threads; | |
2622 | ||
2623 | /* Handle the partially filled core for older machine types */ | |
2624 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2625 | nr_threads = smp_cpus - i * smp_threads; | |
2626 | } | |
2627 | ||
2628 | object_property_set_int(core, nr_threads, "nr-threads", | |
2629 | &error_fatal); | |
2630 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2631 | &error_fatal); | |
2632 | object_property_set_bool(core, true, "realized", &error_fatal); | |
ecda255e SB |
2633 | |
2634 | object_unref(core); | |
1a5008fc GK |
2635 | } |
2636 | } | |
2637 | } | |
2638 | ||
999c9caf GK |
2639 | static PCIHostState *spapr_create_default_phb(void) |
2640 | { | |
2641 | DeviceState *dev; | |
2642 | ||
2643 | dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
2644 | qdev_prop_set_uint32(dev, "index", 0); | |
2645 | qdev_init_nofail(dev); | |
2646 | ||
2647 | return PCI_HOST_BRIDGE(dev); | |
2648 | } | |
2649 | ||
425f0b7a DG |
2650 | static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) |
2651 | { | |
2652 | MachineState *machine = MACHINE(spapr); | |
2653 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
2654 | hwaddr rma_size = machine->ram_size; | |
2655 | hwaddr node0_size = spapr_node0_size(machine); | |
2656 | ||
2657 | /* RMA has to fit in the first NUMA node */ | |
2658 | rma_size = MIN(rma_size, node0_size); | |
2659 | ||
2660 | /* | |
2661 | * VRMA access is via a special 1TiB SLB mapping, so the RMA can | |
2662 | * never exceed that | |
2663 | */ | |
2664 | rma_size = MIN(rma_size, 1 * TiB); | |
2665 | ||
2666 | /* | |
2667 | * Clamp the RMA size based on machine type. This is for | |
2668 | * migration compatibility with older qemu versions, which limited | |
2669 | * the RMA size for complicated and mostly bad reasons. | |
2670 | */ | |
2671 | if (smc->rma_limit) { | |
2672 | rma_size = MIN(rma_size, smc->rma_limit); | |
2673 | } | |
2674 | ||
2675 | if (rma_size < MIN_RMA_SLOF) { | |
2676 | error_setg(errp, | |
2677 | "pSeries SLOF firmware requires >= %" HWADDR_PRIx | |
2678 | "ldMiB guest RMA (Real Mode Area memory)", | |
2679 | MIN_RMA_SLOF / MiB); | |
2680 | return 0; | |
2681 | } | |
2682 | ||
2683 | return rma_size; | |
2684 | } | |
2685 | ||
9fdf0c29 | 2686 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2687 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2688 | { |
ce2918cb DG |
2689 | SpaprMachineState *spapr = SPAPR_MACHINE(machine); |
2690 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); | |
ee3a71e3 | 2691 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
3ef96221 | 2692 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2693 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2694 | PCIHostState *phb; |
9fdf0c29 | 2695 | int i; |
890c2b77 | 2696 | MemoryRegion *sysmem = get_system_memory(); |
b7d1f77a | 2697 | long load_limit, fw_size; |
39ac8455 | 2698 | char *filename; |
30f4b05b | 2699 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2700 | |
226419d6 | 2701 | msi_nonbroken = true; |
0ee2c058 | 2702 | |
d43b45e2 | 2703 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2704 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2705 | |
9f6edd06 DG |
2706 | /* Determine capabilities to run with */ |
2707 | spapr_caps_init(spapr); | |
2708 | ||
30f4b05b DG |
2709 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); |
2710 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2711 | /* | |
2712 | * If the user explicitly requested a mode we should either | |
2713 | * supply it, or fail completely (which we do below). But if | |
2714 | * it's not set explicitly, we reset our mode to something | |
2715 | * that works | |
2716 | */ | |
2717 | if (resize_hpt_err) { | |
2718 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2719 | error_free(resize_hpt_err); | |
2720 | resize_hpt_err = NULL; | |
2721 | } else { | |
2722 | spapr->resize_hpt = smc->resize_hpt_default; | |
2723 | } | |
2724 | } | |
2725 | ||
2726 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2727 | ||
2728 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2729 | /* | |
2730 | * User requested HPT resize, but this host can't supply it. Bail out | |
2731 | */ | |
2732 | error_report_err(resize_hpt_err); | |
2733 | exit(1); | |
2734 | } | |
2735 | ||
425f0b7a | 2736 | spapr->rma_size = spapr_rma_size(spapr, &error_fatal); |
c4177479 | 2737 | |
b7d1f77a BH |
2738 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2739 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2740 | |
482969d6 CLG |
2741 | /* |
2742 | * VSMT must be set in order to be able to compute VCPU ids, ie to | |
1a518e76 | 2743 | * call spapr_max_server_number() or spapr_vcpu_id(). |
482969d6 CLG |
2744 | */ |
2745 | spapr_set_vsmt_mode(spapr, &error_fatal); | |
2746 | ||
7b565160 | 2747 | /* Set up Interrupt Controller before we create the VCPUs */ |
fab397d8 | 2748 | spapr_irq_init(spapr, &error_fatal); |
7b565160 | 2749 | |
dc1b5eee GK |
2750 | /* Set up containers for ibm,client-architecture-support negotiated options |
2751 | */ | |
facdb8b6 MR |
2752 | spapr->ov5 = spapr_ovec_new(); |
2753 | spapr->ov5_cas = spapr_ovec_new(); | |
2754 | ||
224245bf | 2755 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2756 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2757 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2758 | } |
2759 | ||
417ece33 MR |
2760 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
2761 | ||
ffbb1705 MR |
2762 | /* advertise support for dedicated HP event source to guests */ |
2763 | if (spapr->use_hotplug_event_source) { | |
2764 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2765 | } | |
2766 | ||
2772cf6b DG |
2767 | /* advertise support for HPT resizing */ |
2768 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2769 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2770 | } | |
2771 | ||
a324d6f1 BR |
2772 | /* advertise support for ibm,dyamic-memory-v2 */ |
2773 | spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); | |
2774 | ||
db592b5b | 2775 | /* advertise XIVE on POWER9 machines */ |
ca62823b | 2776 | if (spapr->irq->xive) { |
273fef83 | 2777 | spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); |
db592b5b CLG |
2778 | } |
2779 | ||
9fdf0c29 | 2780 | /* init CPUs */ |
0c86d0fd | 2781 | spapr_init_cpus(spapr); |
9fdf0c29 | 2782 | |
58c46efa LV |
2783 | /* |
2784 | * check we don't have a memory-less/cpu-less NUMA node | |
2785 | * Firmware relies on the existing memory/cpu topology to provide the | |
2786 | * NUMA topology to the kernel. | |
2787 | * And the linux kernel needs to know the NUMA topology at start | |
2788 | * to be able to hotplug CPUs later. | |
2789 | */ | |
2790 | if (machine->numa_state->num_nodes) { | |
2791 | for (i = 0; i < machine->numa_state->num_nodes; ++i) { | |
2792 | /* check for memory-less node */ | |
2793 | if (machine->numa_state->nodes[i].node_mem == 0) { | |
2794 | CPUState *cs; | |
2795 | int found = 0; | |
2796 | /* check for cpu-less node */ | |
2797 | CPU_FOREACH(cs) { | |
2798 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2799 | if (cpu->node_id == i) { | |
2800 | found = 1; | |
2801 | break; | |
2802 | } | |
2803 | } | |
2804 | /* memory-less and cpu-less node */ | |
2805 | if (!found) { | |
2806 | error_report( | |
2807 | "Memory-less/cpu-less nodes are not supported (node %d)", | |
2808 | i); | |
2809 | exit(1); | |
2810 | } | |
2811 | } | |
2812 | } | |
2813 | ||
2814 | } | |
2815 | ||
db5127b2 DG |
2816 | /* |
2817 | * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. | |
2818 | * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is | |
2819 | * called from vPHB reset handler so we initialize the counter here. | |
2820 | * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM | |
2821 | * must be equally distant from any other node. | |
2822 | * The final value of spapr->gpu_numa_id is going to be written to | |
2823 | * max-associativity-domains in spapr_build_fdt(). | |
2824 | */ | |
2825 | spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); | |
2826 | ||
0550b120 | 2827 | if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && |
ad99d04c DG |
2828 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
2829 | spapr->max_compat_pvr)) { | |
b4b83312 | 2830 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); |
0550b120 GK |
2831 | /* KVM and TCG always allow GTSE with radix... */ |
2832 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); | |
2833 | } | |
2834 | /* ... but not with hash (currently). */ | |
2835 | ||
026bfd89 DG |
2836 | if (kvm_enabled()) { |
2837 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2838 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2839 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2840 | |
2841 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2842 | kvmppc_enable_clear_ref_mod_hcalls(); | |
68f9f708 SJS |
2843 | |
2844 | /* Enable H_PAGE_INIT */ | |
2845 | kvmppc_enable_h_page_init(); | |
026bfd89 DG |
2846 | } |
2847 | ||
ab74e543 IM |
2848 | /* map RAM */ |
2849 | memory_region_add_subregion(sysmem, 0, machine->ram); | |
9fdf0c29 | 2850 | |
b0c14ec4 DH |
2851 | /* always allocate the device memory information */ |
2852 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
2853 | ||
4a1c9cf0 BR |
2854 | /* initialize hotplug memory address space */ |
2855 | if (machine->ram_size < machine->maxram_size) { | |
0c9269a5 | 2856 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
71c9a3dd BR |
2857 | /* |
2858 | * Limit the number of hotpluggable memory slots to half the number | |
2859 | * slots that KVM supports, leaving the other half for PCI and other | |
2860 | * devices. However ensure that number of slots doesn't drop below 32. | |
2861 | */ | |
2862 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2863 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2864 | |
71c9a3dd BR |
2865 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2866 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2867 | } | |
2868 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2869 | error_report("Specified number of memory slots %" |
2870 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2871 | machine->ram_slots, max_memslots); |
d54e4d76 | 2872 | exit(1); |
4a1c9cf0 BR |
2873 | } |
2874 | ||
b0c14ec4 | 2875 | machine->device_memory->base = ROUND_UP(machine->ram_size, |
0c9269a5 | 2876 | SPAPR_DEVICE_MEM_ALIGN); |
b0c14ec4 | 2877 | memory_region_init(&machine->device_memory->mr, OBJECT(spapr), |
0c9269a5 | 2878 | "device-memory", device_mem_size); |
b0c14ec4 DH |
2879 | memory_region_add_subregion(sysmem, machine->device_memory->base, |
2880 | &machine->device_memory->mr); | |
4a1c9cf0 BR |
2881 | } |
2882 | ||
224245bf DG |
2883 | if (smc->dr_lmb_enabled) { |
2884 | spapr_create_lmb_dr_connectors(spapr); | |
2885 | } | |
2886 | ||
8af7e1fe | 2887 | if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { |
2500fb42 AP |
2888 | /* Create the error string for live migration blocker */ |
2889 | error_setg(&spapr->fwnmi_migration_blocker, | |
2890 | "A machine check is being handled during migration. The handler" | |
2891 | "may run and log hardware error on the destination"); | |
2892 | } | |
2893 | ||
ee3a71e3 SB |
2894 | if (mc->nvdimm_supported) { |
2895 | spapr_create_nvdimm_dr_connectors(spapr); | |
2896 | } | |
2897 | ||
ffbb1705 | 2898 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2899 | spapr_events_init(spapr); |
2900 | ||
12f42174 | 2901 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2902 | spapr_rtc_create(spapr); |
12f42174 | 2903 | |
b5cec4c5 | 2904 | /* Set up VIO bus */ |
4040ab72 DG |
2905 | spapr->vio_bus = spapr_vio_bus_init(); |
2906 | ||
b8846a4d | 2907 | for (i = 0; i < serial_max_hds(); i++) { |
9bca0edb PM |
2908 | if (serial_hd(i)) { |
2909 | spapr_vty_create(spapr->vio_bus, serial_hd(i)); | |
4040ab72 DG |
2910 | } |
2911 | } | |
9fdf0c29 | 2912 | |
639e8102 DG |
2913 | /* We always have at least the nvram device on VIO */ |
2914 | spapr_create_nvram(spapr); | |
2915 | ||
962b6c36 MR |
2916 | /* |
2917 | * Setup hotplug / dynamic-reconfiguration connectors. top-level | |
2918 | * connectors (described in root DT node's "ibm,drc-types" property) | |
2919 | * are pre-initialized here. additional child connectors (such as | |
2920 | * connectors for a PHBs PCI slots) are added as needed during their | |
2921 | * parent's realization. | |
2922 | */ | |
2923 | if (smc->dr_phb_enabled) { | |
2924 | for (i = 0; i < SPAPR_MAX_PHBS; i++) { | |
2925 | spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); | |
2926 | } | |
2927 | } | |
2928 | ||
3384f95c | 2929 | /* Set up PCI */ |
fa28f71b AK |
2930 | spapr_pci_rtas_init(); |
2931 | ||
999c9caf | 2932 | phb = spapr_create_default_phb(); |
3384f95c | 2933 | |
277f9acf | 2934 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2935 | NICInfo *nd = &nd_table[i]; |
2936 | ||
2937 | if (!nd->model) { | |
3c3a4e7a | 2938 | nd->model = g_strdup("spapr-vlan"); |
8d90ad90 DG |
2939 | } |
2940 | ||
3c3a4e7a TH |
2941 | if (g_str_equal(nd->model, "spapr-vlan") || |
2942 | g_str_equal(nd->model, "ibmveth")) { | |
d601fac4 | 2943 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2944 | } else { |
29b358f9 | 2945 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2946 | } |
2947 | } | |
2948 | ||
6e270446 | 2949 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2950 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2951 | } |
2952 | ||
f28359d8 | 2953 | /* Graphics */ |
14c6a894 | 2954 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2955 | spapr->has_graphics = true; |
c6e76503 | 2956 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2957 | } |
2958 | ||
4ee9ced9 | 2959 | if (machine->usb) { |
57040d45 TH |
2960 | if (smc->use_ohci_by_default) { |
2961 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2962 | } else { | |
2963 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2964 | } | |
c86580b8 | 2965 | |
35139a59 | 2966 | if (spapr->has_graphics) { |
c86580b8 MA |
2967 | USBBus *usb_bus = usb_bus_find(-1); |
2968 | ||
2969 | usb_create_simple(usb_bus, "usb-kbd"); | |
2970 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2971 | } |
2972 | } | |
2973 | ||
9fdf0c29 DG |
2974 | if (kernel_filename) { |
2975 | uint64_t lowaddr = 0; | |
2976 | ||
4366e1db | 2977 | spapr->kernel_size = load_elf(kernel_filename, NULL, |
87262806 | 2978 | translate_kernel_address, spapr, |
6cdda0ff | 2979 | NULL, &lowaddr, NULL, NULL, 1, |
a19f7fb0 DG |
2980 | PPC_ELF_MACHINE, 0, 0); |
2981 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
4366e1db | 2982 | spapr->kernel_size = load_elf(kernel_filename, NULL, |
87262806 | 2983 | translate_kernel_address, spapr, NULL, |
6cdda0ff | 2984 | &lowaddr, NULL, NULL, 0, |
87262806 AK |
2985 | PPC_ELF_MACHINE, |
2986 | 0, 0); | |
a19f7fb0 | 2987 | spapr->kernel_le = spapr->kernel_size > 0; |
16457e7f | 2988 | } |
a19f7fb0 DG |
2989 | if (spapr->kernel_size < 0) { |
2990 | error_report("error loading %s: %s", kernel_filename, | |
2991 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2992 | exit(1); |
2993 | } | |
2994 | ||
2995 | /* load initrd */ | |
2996 | if (initrd_filename) { | |
4d8d5467 BH |
2997 | /* Try to locate the initrd in the gap between the kernel |
2998 | * and the firmware. Add a bit of space just in case | |
2999 | */ | |
87262806 | 3000 | spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size |
a19f7fb0 DG |
3001 | + 0x1ffff) & ~0xffff; |
3002 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
3003 | spapr->initrd_base, | |
3004 | load_limit | |
3005 | - spapr->initrd_base); | |
3006 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
3007 | error_report("could not load initial ram disk '%s'", |
3008 | initrd_filename); | |
9fdf0c29 DG |
3009 | exit(1); |
3010 | } | |
9fdf0c29 | 3011 | } |
4d8d5467 | 3012 | } |
a3467baa | 3013 | |
8e7ea787 AF |
3014 | if (bios_name == NULL) { |
3015 | bios_name = FW_FILE_NAME; | |
3016 | } | |
3017 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 3018 | if (!filename) { |
68fea5a0 | 3019 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
3020 | exit(1); |
3021 | } | |
4d8d5467 | 3022 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
3023 | if (fw_size <= 0) { |
3024 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
3025 | exit(1); |
3026 | } | |
3027 | g_free(filename); | |
4d8d5467 | 3028 | |
28e02042 DG |
3029 | /* FIXME: Should register things through the MachineState's qdev |
3030 | * interface, this is a legacy from the sPAPREnvironment structure | |
3031 | * which predated MachineState but had a similar function */ | |
4be21d56 | 3032 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
1df2c9a2 | 3033 | register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, |
4be21d56 DG |
3034 | &savevm_htab_handlers, spapr); |
3035 | ||
bb2bdd81 GK |
3036 | qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), |
3037 | &error_fatal); | |
3038 | ||
5b2128d2 | 3039 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 3040 | |
93eac7b8 NP |
3041 | /* |
3042 | * Nothing needs to be done to resume a suspended guest because | |
3043 | * suspending does not change the machine state, so no need for | |
3044 | * a ->wakeup method. | |
3045 | */ | |
3046 | qemu_register_wakeup_support(); | |
3047 | ||
42043e4f | 3048 | if (kvm_enabled()) { |
3dc410ae | 3049 | /* to stop and start vmclock */ |
42043e4f LV |
3050 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
3051 | &spapr->tb); | |
3dc410ae AK |
3052 | |
3053 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 3054 | } |
9ac703ac | 3055 | |
8af7e1fe | 3056 | qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); |
9fdf0c29 DG |
3057 | } |
3058 | ||
dc0ca80e | 3059 | static int spapr_kvm_type(MachineState *machine, const char *vm_type) |
135a129a AK |
3060 | { |
3061 | if (!vm_type) { | |
3062 | return 0; | |
3063 | } | |
3064 | ||
3065 | if (!strcmp(vm_type, "HV")) { | |
3066 | return 1; | |
3067 | } | |
3068 | ||
3069 | if (!strcmp(vm_type, "PR")) { | |
3070 | return 2; | |
3071 | } | |
3072 | ||
3073 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
3074 | exit(1); | |
3075 | } | |
3076 | ||
71461b0f | 3077 | /* |
627b84f4 | 3078 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
3079 | * for the bootindex property handling. |
3080 | */ | |
3081 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
3082 | DeviceState *dev) | |
3083 | { | |
3084 | #define CAST(type, obj, name) \ | |
3085 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
3086 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
ce2918cb | 3087 | SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); |
c4e13492 | 3088 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
3089 | |
3090 | if (d) { | |
3091 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
3092 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
3093 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
3094 | ||
3095 | if (spapr) { | |
3096 | /* | |
3097 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
1ac24c91 TH |
3098 | * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form |
3099 | * 0x8000 | (target << 8) | (bus << 5) | lun | |
3100 | * (see the "Logical unit addressing format" table in SAM5) | |
71461b0f | 3101 | */ |
1ac24c91 | 3102 | unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; |
71461b0f AK |
3103 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
3104 | (uint64_t)id << 48); | |
3105 | } else if (virtio) { | |
3106 | /* | |
3107 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
3108 | * in the top 32 bits of the 64-bit LUN | |
3109 | * Note: the quote above is from SLOF and it is wrong, | |
3110 | * the actual binding is: | |
3111 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
3112 | */ | |
3113 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
3114 | if (d->lun >= 256) { |
3115 | /* Use the LUN "flat space addressing method" */ | |
3116 | id |= 0x4000; | |
3117 | } | |
71461b0f AK |
3118 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
3119 | (uint64_t)id << 32); | |
3120 | } else if (usb) { | |
3121 | /* | |
3122 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
3123 | * in the top 32 bits of the 64-bit LUN | |
3124 | */ | |
3125 | unsigned usb_port = atoi(usb->port->path); | |
3126 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
3127 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
3128 | (uint64_t)id << 32); | |
3129 | } | |
3130 | } | |
3131 | ||
b99260eb TH |
3132 | /* |
3133 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
3134 | * storage device, it changes its name to "storage" instead of "usb-host", | |
3135 | * and additionally adds a child node for the SCSI LUN, so the correct | |
3136 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
3137 | */ | |
3138 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
3139 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
3140 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
3141 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
3142 | } | |
3143 | } | |
3144 | ||
71461b0f AK |
3145 | if (phb) { |
3146 | /* Replace "pci" with "pci@800000020000000" */ | |
3147 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
3148 | } | |
3149 | ||
c4e13492 FF |
3150 | if (vsc) { |
3151 | /* Same logic as virtio above */ | |
3152 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
3153 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
3154 | } | |
3155 | ||
4871dd4c TH |
3156 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
3157 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
3158 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
3159 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
3160 | } | |
3161 | ||
71461b0f AK |
3162 | return NULL; |
3163 | } | |
3164 | ||
23825581 EH |
3165 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
3166 | { | |
ce2918cb | 3167 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 3168 | |
28e02042 | 3169 | return g_strdup(spapr->kvm_type); |
23825581 EH |
3170 | } |
3171 | ||
3172 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
3173 | { | |
ce2918cb | 3174 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 3175 | |
28e02042 DG |
3176 | g_free(spapr->kvm_type); |
3177 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
3178 | } |
3179 | ||
f6229214 MR |
3180 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
3181 | { | |
ce2918cb | 3182 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
f6229214 MR |
3183 | |
3184 | return spapr->use_hotplug_event_source; | |
3185 | } | |
3186 | ||
3187 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
3188 | Error **errp) | |
3189 | { | |
ce2918cb | 3190 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
f6229214 MR |
3191 | |
3192 | spapr->use_hotplug_event_source = value; | |
3193 | } | |
3194 | ||
fcad0d21 AK |
3195 | static bool spapr_get_msix_emulation(Object *obj, Error **errp) |
3196 | { | |
3197 | return true; | |
3198 | } | |
3199 | ||
30f4b05b DG |
3200 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
3201 | { | |
ce2918cb | 3202 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
30f4b05b DG |
3203 | |
3204 | switch (spapr->resize_hpt) { | |
3205 | case SPAPR_RESIZE_HPT_DEFAULT: | |
3206 | return g_strdup("default"); | |
3207 | case SPAPR_RESIZE_HPT_DISABLED: | |
3208 | return g_strdup("disabled"); | |
3209 | case SPAPR_RESIZE_HPT_ENABLED: | |
3210 | return g_strdup("enabled"); | |
3211 | case SPAPR_RESIZE_HPT_REQUIRED: | |
3212 | return g_strdup("required"); | |
3213 | } | |
3214 | g_assert_not_reached(); | |
3215 | } | |
3216 | ||
3217 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
3218 | { | |
ce2918cb | 3219 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
30f4b05b DG |
3220 | |
3221 | if (strcmp(value, "default") == 0) { | |
3222 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
3223 | } else if (strcmp(value, "disabled") == 0) { | |
3224 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
3225 | } else if (strcmp(value, "enabled") == 0) { | |
3226 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
3227 | } else if (strcmp(value, "required") == 0) { | |
3228 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
3229 | } else { | |
3230 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
3231 | } | |
3232 | } | |
3233 | ||
3ba3d0bc CLG |
3234 | static char *spapr_get_ic_mode(Object *obj, Error **errp) |
3235 | { | |
ce2918cb | 3236 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3ba3d0bc CLG |
3237 | |
3238 | if (spapr->irq == &spapr_irq_xics_legacy) { | |
3239 | return g_strdup("legacy"); | |
3240 | } else if (spapr->irq == &spapr_irq_xics) { | |
3241 | return g_strdup("xics"); | |
3242 | } else if (spapr->irq == &spapr_irq_xive) { | |
3243 | return g_strdup("xive"); | |
13db0cd9 CLG |
3244 | } else if (spapr->irq == &spapr_irq_dual) { |
3245 | return g_strdup("dual"); | |
3ba3d0bc CLG |
3246 | } |
3247 | g_assert_not_reached(); | |
3248 | } | |
3249 | ||
3250 | static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) | |
3251 | { | |
ce2918cb | 3252 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3ba3d0bc | 3253 | |
21df5e4f GK |
3254 | if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
3255 | error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); | |
3256 | return; | |
3257 | } | |
3258 | ||
3ba3d0bc CLG |
3259 | /* The legacy IRQ backend can not be set */ |
3260 | if (strcmp(value, "xics") == 0) { | |
3261 | spapr->irq = &spapr_irq_xics; | |
3262 | } else if (strcmp(value, "xive") == 0) { | |
3263 | spapr->irq = &spapr_irq_xive; | |
13db0cd9 CLG |
3264 | } else if (strcmp(value, "dual") == 0) { |
3265 | spapr->irq = &spapr_irq_dual; | |
3ba3d0bc CLG |
3266 | } else { |
3267 | error_setg(errp, "Bad value for \"ic-mode\" property"); | |
3268 | } | |
3269 | } | |
3270 | ||
27461d69 PP |
3271 | static char *spapr_get_host_model(Object *obj, Error **errp) |
3272 | { | |
ce2918cb | 3273 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
27461d69 PP |
3274 | |
3275 | return g_strdup(spapr->host_model); | |
3276 | } | |
3277 | ||
3278 | static void spapr_set_host_model(Object *obj, const char *value, Error **errp) | |
3279 | { | |
ce2918cb | 3280 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
27461d69 PP |
3281 | |
3282 | g_free(spapr->host_model); | |
3283 | spapr->host_model = g_strdup(value); | |
3284 | } | |
3285 | ||
3286 | static char *spapr_get_host_serial(Object *obj, Error **errp) | |
3287 | { | |
ce2918cb | 3288 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
27461d69 PP |
3289 | |
3290 | return g_strdup(spapr->host_serial); | |
3291 | } | |
3292 | ||
3293 | static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) | |
3294 | { | |
ce2918cb | 3295 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
27461d69 PP |
3296 | |
3297 | g_free(spapr->host_serial); | |
3298 | spapr->host_serial = g_strdup(value); | |
3299 | } | |
3300 | ||
bcb5ce08 | 3301 | static void spapr_instance_init(Object *obj) |
23825581 | 3302 | { |
ce2918cb DG |
3303 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
3304 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
715c5407 DG |
3305 | |
3306 | spapr->htab_fd = -1; | |
f6229214 | 3307 | spapr->use_hotplug_event_source = true; |
23825581 | 3308 | object_property_add_str(obj, "kvm-type", |
d2623129 | 3309 | spapr_get_kvm_type, spapr_set_kvm_type); |
49d2e648 | 3310 | object_property_set_description(obj, "kvm-type", |
7eecec7d | 3311 | "Specifies the KVM virtualization mode (HV, PR)"); |
f6229214 MR |
3312 | object_property_add_bool(obj, "modern-hotplug-events", |
3313 | spapr_get_modern_hotplug_events, | |
d2623129 | 3314 | spapr_set_modern_hotplug_events); |
f6229214 MR |
3315 | object_property_set_description(obj, "modern-hotplug-events", |
3316 | "Use dedicated hotplug event mechanism in" | |
3317 | " place of standard EPOW events when possible" | |
7eecec7d | 3318 | " (required for memory hot-unplug support)"); |
7843c0d6 | 3319 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, |
40c2281c | 3320 | "Maximum permitted CPU compatibility mode"); |
30f4b05b DG |
3321 | |
3322 | object_property_add_str(obj, "resize-hpt", | |
d2623129 | 3323 | spapr_get_resize_hpt, spapr_set_resize_hpt); |
30f4b05b | 3324 | object_property_set_description(obj, "resize-hpt", |
7eecec7d | 3325 | "Resizing of the Hash Page Table (enabled, disabled, required)"); |
64a7b8de | 3326 | object_property_add_uint32_ptr(obj, "vsmt", |
d2623129 | 3327 | &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); |
fa98fbfc SB |
3328 | object_property_set_description(obj, "vsmt", |
3329 | "Virtual SMT: KVM behaves as if this were" | |
7eecec7d | 3330 | " the host's SMT mode"); |
64a7b8de | 3331 | |
fcad0d21 | 3332 | object_property_add_bool(obj, "vfio-no-msix-emulation", |
d2623129 | 3333 | spapr_get_msix_emulation, NULL); |
3ba3d0bc | 3334 | |
64a7b8de | 3335 | object_property_add_uint64_ptr(obj, "kernel-addr", |
d2623129 | 3336 | &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); |
87262806 AK |
3337 | object_property_set_description(obj, "kernel-addr", |
3338 | stringify(KERNEL_LOAD_ADDR) | |
7eecec7d | 3339 | " for -kernel is the default"); |
87262806 | 3340 | spapr->kernel_addr = KERNEL_LOAD_ADDR; |
3ba3d0bc CLG |
3341 | /* The machine class defines the default interrupt controller mode */ |
3342 | spapr->irq = smc->irq; | |
3343 | object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, | |
d2623129 | 3344 | spapr_set_ic_mode); |
3ba3d0bc | 3345 | object_property_set_description(obj, "ic-mode", |
7eecec7d | 3346 | "Specifies the interrupt controller mode (xics, xive, dual)"); |
27461d69 PP |
3347 | |
3348 | object_property_add_str(obj, "host-model", | |
d2623129 | 3349 | spapr_get_host_model, spapr_set_host_model); |
27461d69 | 3350 | object_property_set_description(obj, "host-model", |
7eecec7d | 3351 | "Host model to advertise in guest device tree"); |
27461d69 | 3352 | object_property_add_str(obj, "host-serial", |
d2623129 | 3353 | spapr_get_host_serial, spapr_set_host_serial); |
27461d69 | 3354 | object_property_set_description(obj, "host-serial", |
7eecec7d | 3355 | "Host serial number to advertise in guest device tree"); |
23825581 EH |
3356 | } |
3357 | ||
87bbdd9c DG |
3358 | static void spapr_machine_finalizefn(Object *obj) |
3359 | { | |
ce2918cb | 3360 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
87bbdd9c DG |
3361 | |
3362 | g_free(spapr->kvm_type); | |
3363 | } | |
3364 | ||
1c7ad77e | 3365 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 3366 | { |
0e236d34 | 3367 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
b5b7f391 NP |
3368 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
3369 | CPUPPCState *env = &cpu->env; | |
0e236d34 | 3370 | |
34316482 | 3371 | cpu_synchronize_state(cs); |
0e236d34 NP |
3372 | /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ |
3373 | if (spapr->fwnmi_system_reset_addr != -1) { | |
3374 | uint64_t rtas_addr, addr; | |
0e236d34 NP |
3375 | |
3376 | /* get rtas addr from fdt */ | |
3377 | rtas_addr = spapr_get_rtas_addr(); | |
3378 | if (!rtas_addr) { | |
3379 | qemu_system_guest_panicked(NULL); | |
3380 | return; | |
3381 | } | |
3382 | ||
3383 | addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; | |
3384 | stq_be_phys(&address_space_memory, addr, env->gpr[3]); | |
3385 | stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); | |
3386 | env->gpr[3] = addr; | |
3387 | } | |
b5b7f391 NP |
3388 | ppc_cpu_do_system_reset(cs); |
3389 | if (spapr->fwnmi_system_reset_addr != -1) { | |
3390 | env->nip = spapr->fwnmi_system_reset_addr; | |
3391 | } | |
34316482 AK |
3392 | } |
3393 | ||
3394 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
3395 | { | |
3396 | CPUState *cs; | |
3397 | ||
3398 | CPU_FOREACH(cs) { | |
1c7ad77e | 3399 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
3400 | } |
3401 | } | |
3402 | ||
ce2918cb | 3403 | int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
62d38c9b GK |
3404 | void *fdt, int *fdt_start_offset, Error **errp) |
3405 | { | |
3406 | uint64_t addr; | |
3407 | uint32_t node; | |
3408 | ||
3409 | addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; | |
3410 | node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, | |
3411 | &error_abort); | |
91335a5e DG |
3412 | *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, |
3413 | SPAPR_MEMORY_BLOCK_SIZE); | |
62d38c9b GK |
3414 | return 0; |
3415 | } | |
3416 | ||
79b78a6b | 3417 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
62d38c9b | 3418 | bool dedicated_hp_event_source, Error **errp) |
c20d332a | 3419 | { |
ce2918cb | 3420 | SpaprDrc *drc; |
c20d332a | 3421 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
62d38c9b | 3422 | int i; |
79b78a6b | 3423 | uint64_t addr = addr_start; |
94fd9cba | 3424 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 3425 | Error *local_err = NULL; |
c20d332a | 3426 | |
c20d332a | 3427 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
3428 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3429 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
3430 | g_assert(drc); |
3431 | ||
09d876ce | 3432 | spapr_drc_attach(drc, dev, &local_err); |
160bb678 GK |
3433 | if (local_err) { |
3434 | while (addr > addr_start) { | |
3435 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
3436 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
3437 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 3438 | spapr_drc_detach(drc); |
160bb678 | 3439 | } |
160bb678 GK |
3440 | error_propagate(errp, local_err); |
3441 | return; | |
3442 | } | |
94fd9cba LV |
3443 | if (!hotplugged) { |
3444 | spapr_drc_reset(drc); | |
3445 | } | |
c20d332a BR |
3446 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3447 | } | |
5dd5238c JD |
3448 | /* send hotplug notification to the |
3449 | * guest only in case of hotplugged memory | |
3450 | */ | |
94fd9cba | 3451 | if (hotplugged) { |
79b78a6b | 3452 | if (dedicated_hp_event_source) { |
fbf55397 DG |
3453 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3454 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
3455 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3456 | nr_lmbs, | |
0b55aa91 | 3457 | spapr_drc_index(drc)); |
79b78a6b MR |
3458 | } else { |
3459 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
3460 | nr_lmbs); | |
3461 | } | |
5dd5238c | 3462 | } |
c20d332a BR |
3463 | } |
3464 | ||
3465 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
81985f3b | 3466 | Error **errp) |
c20d332a BR |
3467 | { |
3468 | Error *local_err = NULL; | |
ce2918cb | 3469 | SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); |
c20d332a | 3470 | PCDIMMDevice *dimm = PC_DIMM(dev); |
ee3a71e3 SB |
3471 | uint64_t size, addr, slot; |
3472 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
04790978 | 3473 | |
946d6154 | 3474 | size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); |
df587133 | 3475 | |
fd3416f5 | 3476 | pc_dimm_plug(dimm, MACHINE(ms), &local_err); |
c20d332a BR |
3477 | if (local_err) { |
3478 | goto out; | |
3479 | } | |
3480 | ||
ee3a71e3 SB |
3481 | if (!is_nvdimm) { |
3482 | addr = object_property_get_uint(OBJECT(dimm), | |
3483 | PC_DIMM_ADDR_PROP, &local_err); | |
3484 | if (local_err) { | |
3485 | goto out_unplug; | |
3486 | } | |
3487 | spapr_add_lmbs(dev, addr, size, | |
3488 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
3489 | &local_err); | |
3490 | } else { | |
3491 | slot = object_property_get_uint(OBJECT(dimm), | |
3492 | PC_DIMM_SLOT_PROP, &local_err); | |
3493 | if (local_err) { | |
3494 | goto out_unplug; | |
3495 | } | |
3496 | spapr_add_nvdimm(dev, slot, &local_err); | |
c20d332a BR |
3497 | } |
3498 | ||
160bb678 GK |
3499 | if (local_err) { |
3500 | goto out_unplug; | |
3501 | } | |
3502 | ||
3503 | return; | |
c20d332a | 3504 | |
160bb678 | 3505 | out_unplug: |
fd3416f5 | 3506 | pc_dimm_unplug(dimm, MACHINE(ms)); |
c20d332a BR |
3507 | out: |
3508 | error_propagate(errp, local_err); | |
3509 | } | |
3510 | ||
c871bc70 LV |
3511 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3512 | Error **errp) | |
3513 | { | |
ce2918cb DG |
3514 | const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); |
3515 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); | |
ee3a71e3 SB |
3516 | const MachineClass *mc = MACHINE_CLASS(smc); |
3517 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
c871bc70 | 3518 | PCDIMMDevice *dimm = PC_DIMM(dev); |
8f1ffe5b | 3519 | Error *local_err = NULL; |
04790978 | 3520 | uint64_t size; |
123eec65 DG |
3521 | Object *memdev; |
3522 | hwaddr pagesize; | |
c871bc70 | 3523 | |
4e8a01bd DH |
3524 | if (!smc->dr_lmb_enabled) { |
3525 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3526 | return; | |
3527 | } | |
3528 | ||
ee3a71e3 SB |
3529 | if (is_nvdimm && !mc->nvdimm_supported) { |
3530 | error_setg(errp, "NVDIMM hotplug not supported for this machine"); | |
3531 | return; | |
3532 | } | |
3533 | ||
946d6154 DH |
3534 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); |
3535 | if (local_err) { | |
3536 | error_propagate(errp, local_err); | |
04790978 TH |
3537 | return; |
3538 | } | |
04790978 | 3539 | |
ee3a71e3 | 3540 | if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { |
c871bc70 | 3541 | error_setg(errp, "Hotplugged memory size must be a multiple of " |
ee3a71e3 | 3542 | "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); |
c871bc70 | 3543 | return; |
ee3a71e3 SB |
3544 | } else if (is_nvdimm) { |
3545 | spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); | |
3546 | if (local_err) { | |
3547 | error_propagate(errp, local_err); | |
3548 | return; | |
3549 | } | |
c871bc70 LV |
3550 | } |
3551 | ||
123eec65 DG |
3552 | memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, |
3553 | &error_abort); | |
3554 | pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); | |
8f1ffe5b DH |
3555 | spapr_check_pagesize(spapr, pagesize, &local_err); |
3556 | if (local_err) { | |
3557 | error_propagate(errp, local_err); | |
3558 | return; | |
3559 | } | |
3560 | ||
fd3416f5 | 3561 | pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); |
c871bc70 LV |
3562 | } |
3563 | ||
ce2918cb | 3564 | struct SpaprDimmState { |
0cffce56 | 3565 | PCDIMMDevice *dimm; |
cf632463 | 3566 | uint32_t nr_lmbs; |
ce2918cb | 3567 | QTAILQ_ENTRY(SpaprDimmState) next; |
0cffce56 DG |
3568 | }; |
3569 | ||
ce2918cb | 3570 | static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, |
0cffce56 DG |
3571 | PCDIMMDevice *dimm) |
3572 | { | |
ce2918cb | 3573 | SpaprDimmState *dimm_state = NULL; |
0cffce56 DG |
3574 | |
3575 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3576 | if (dimm_state->dimm == dimm) { | |
3577 | break; | |
3578 | } | |
3579 | } | |
3580 | return dimm_state; | |
3581 | } | |
3582 | ||
ce2918cb | 3583 | static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, |
8d5981c4 BR |
3584 | uint32_t nr_lmbs, |
3585 | PCDIMMDevice *dimm) | |
0cffce56 | 3586 | { |
ce2918cb | 3587 | SpaprDimmState *ds = NULL; |
8d5981c4 BR |
3588 | |
3589 | /* | |
3590 | * If this request is for a DIMM whose removal had failed earlier | |
3591 | * (due to guest's refusal to remove the LMBs), we would have this | |
3592 | * dimm already in the pending_dimm_unplugs list. In that | |
3593 | * case don't add again. | |
3594 | */ | |
3595 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3596 | if (!ds) { | |
ce2918cb | 3597 | ds = g_malloc0(sizeof(SpaprDimmState)); |
8d5981c4 BR |
3598 | ds->nr_lmbs = nr_lmbs; |
3599 | ds->dimm = dimm; | |
3600 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3601 | } | |
3602 | return ds; | |
0cffce56 DG |
3603 | } |
3604 | ||
ce2918cb DG |
3605 | static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, |
3606 | SpaprDimmState *dimm_state) | |
0cffce56 DG |
3607 | { |
3608 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3609 | g_free(dimm_state); | |
3610 | } | |
cf632463 | 3611 | |
ce2918cb | 3612 | static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, |
16ee9980 DHB |
3613 | PCDIMMDevice *dimm) |
3614 | { | |
ce2918cb | 3615 | SpaprDrc *drc; |
946d6154 DH |
3616 | uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), |
3617 | &error_abort); | |
16ee9980 DHB |
3618 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3619 | uint32_t avail_lmbs = 0; | |
3620 | uint64_t addr_start, addr; | |
3621 | int i; | |
16ee9980 DHB |
3622 | |
3623 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3624 | &error_abort); | |
3625 | ||
3626 | addr = addr_start; | |
3627 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3628 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3629 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3630 | g_assert(drc); |
454b580a | 3631 | if (drc->dev) { |
16ee9980 DHB |
3632 | avail_lmbs++; |
3633 | } | |
3634 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3635 | } | |
3636 | ||
8d5981c4 | 3637 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3638 | } |
3639 | ||
31834723 DHB |
3640 | /* Callback to be called during DRC release. */ |
3641 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3642 | { |
3ec71474 | 3643 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
ce2918cb DG |
3644 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); |
3645 | SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); | |
cf632463 | 3646 | |
16ee9980 DHB |
3647 | /* This information will get lost if a migration occurs |
3648 | * during the unplug process. In this case recover it. */ | |
3649 | if (ds == NULL) { | |
3650 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3651 | g_assert(ds); |
454b580a DG |
3652 | /* The DRC being examined by the caller at least must be counted */ |
3653 | g_assert(ds->nr_lmbs); | |
3654 | } | |
3655 | ||
3656 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3657 | return; |
3658 | } | |
3659 | ||
cf632463 BR |
3660 | /* |
3661 | * Now that all the LMBs have been removed by the guest, call the | |
3ec71474 | 3662 | * unplug handler chain. This can never fail. |
cf632463 | 3663 | */ |
3ec71474 | 3664 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
07578b0a | 3665 | object_unparent(OBJECT(dev)); |
3ec71474 DH |
3666 | } |
3667 | ||
3668 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3669 | { | |
ce2918cb DG |
3670 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
3671 | SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); | |
3ec71474 | 3672 | |
fd3416f5 | 3673 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); |
b69c3c21 | 3674 | object_property_set_bool(OBJECT(dev), false, "realized", &error_abort); |
2a129767 | 3675 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3676 | } |
3677 | ||
3678 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3679 | DeviceState *dev, Error **errp) | |
3680 | { | |
ce2918cb | 3681 | SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3682 | Error *local_err = NULL; |
3683 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
04790978 TH |
3684 | uint32_t nr_lmbs; |
3685 | uint64_t size, addr_start, addr; | |
0cffce56 | 3686 | int i; |
ce2918cb | 3687 | SpaprDrc *drc; |
04790978 | 3688 | |
ee3a71e3 SB |
3689 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
3690 | error_setg(&local_err, | |
3691 | "nvdimm device hot unplug is not supported yet."); | |
3692 | goto out; | |
3693 | } | |
3694 | ||
946d6154 | 3695 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); |
04790978 TH |
3696 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3697 | ||
9ed442b8 | 3698 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3699 | &local_err); |
cf632463 BR |
3700 | if (local_err) { |
3701 | goto out; | |
3702 | } | |
3703 | ||
2a129767 DHB |
3704 | /* |
3705 | * An existing pending dimm state for this DIMM means that there is an | |
3706 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3707 | * callback to complete the job (BQL can't cover that far). In this case, | |
3708 | * bail out to avoid detaching DRCs that were already released. | |
3709 | */ | |
3710 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3711 | error_setg(&local_err, | |
3712 | "Memory unplug already in progress for device %s", | |
3713 | dev->id); | |
3714 | goto out; | |
3715 | } | |
3716 | ||
8d5981c4 | 3717 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3718 | |
3719 | addr = addr_start; | |
3720 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3721 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3722 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3723 | g_assert(drc); |
3724 | ||
a8dc47fd | 3725 | spapr_drc_detach(drc); |
0cffce56 DG |
3726 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3727 | } | |
3728 | ||
fbf55397 DG |
3729 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3730 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3731 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3732 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3733 | out: |
3734 | error_propagate(errp, local_err); | |
3735 | } | |
3736 | ||
765d1bdd DG |
3737 | /* Callback to be called during DRC release. */ |
3738 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3739 | { |
a4261be1 DH |
3740 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3741 | ||
3742 | /* Call the unplug handler chain. This can never fail. */ | |
3743 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
07578b0a | 3744 | object_unparent(OBJECT(dev)); |
a4261be1 DH |
3745 | } |
3746 | ||
3747 | static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3748 | { | |
3749 | MachineState *ms = MACHINE(hotplug_dev); | |
ce2918cb | 3750 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3751 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3752 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3753 | |
46f7afa3 | 3754 | if (smc->pre_2_10_has_unused_icps) { |
ce2918cb | 3755 | SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); |
46f7afa3 GK |
3756 | int i; |
3757 | ||
3758 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3759 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3760 | |
3761 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3762 | } | |
3763 | } | |
3764 | ||
07572c06 | 3765 | assert(core_slot); |
535455fd | 3766 | core_slot->cpu = NULL; |
b69c3c21 | 3767 | object_property_set_bool(OBJECT(dev), false, "realized", &error_abort); |
ff9006dd IM |
3768 | } |
3769 | ||
115debf2 IM |
3770 | static |
3771 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3772 | Error **errp) | |
ff9006dd | 3773 | { |
ce2918cb | 3774 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
535455fd | 3775 | int index; |
ce2918cb | 3776 | SpaprDrc *drc; |
535455fd | 3777 | CPUCore *cc = CPU_CORE(dev); |
ff9006dd | 3778 | |
535455fd IM |
3779 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3780 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3781 | cc->core_id); | |
3782 | return; | |
3783 | } | |
ff9006dd IM |
3784 | if (index == 0) { |
3785 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3786 | return; | |
3787 | } | |
3788 | ||
5d0fb150 GK |
3789 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3790 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd IM |
3791 | g_assert(drc); |
3792 | ||
47c8c915 GK |
3793 | if (!spapr_drc_unplug_requested(drc)) { |
3794 | spapr_drc_detach(drc); | |
3795 | spapr_hotplug_req_remove_by_index(drc); | |
3796 | } | |
ff9006dd IM |
3797 | } |
3798 | ||
ce2918cb | 3799 | int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
345b12b9 GK |
3800 | void *fdt, int *fdt_start_offset, Error **errp) |
3801 | { | |
ce2918cb | 3802 | SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); |
345b12b9 GK |
3803 | CPUState *cs = CPU(core->threads[0]); |
3804 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3805 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
3806 | int id = spapr_get_vcpu_id(cpu); | |
3807 | char *nodename; | |
3808 | int offset; | |
3809 | ||
3810 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3811 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3812 | g_free(nodename); | |
3813 | ||
91335a5e | 3814 | spapr_dt_cpu(cs, fdt, offset, spapr); |
345b12b9 GK |
3815 | |
3816 | *fdt_start_offset = offset; | |
3817 | return 0; | |
3818 | } | |
3819 | ||
ff9006dd IM |
3820 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3821 | Error **errp) | |
3822 | { | |
ce2918cb | 3823 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
ff9006dd | 3824 | MachineClass *mc = MACHINE_GET_CLASS(spapr); |
ce2918cb DG |
3825 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3826 | SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); | |
ff9006dd | 3827 | CPUCore *cc = CPU_CORE(dev); |
345b12b9 | 3828 | CPUState *cs; |
ce2918cb | 3829 | SpaprDrc *drc; |
ff9006dd | 3830 | Error *local_err = NULL; |
535455fd IM |
3831 | CPUArchId *core_slot; |
3832 | int index; | |
94fd9cba | 3833 | bool hotplugged = spapr_drc_hotplugged(dev); |
b1e81567 | 3834 | int i; |
ff9006dd | 3835 | |
535455fd IM |
3836 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3837 | if (!core_slot) { | |
3838 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3839 | cc->core_id); | |
3840 | return; | |
3841 | } | |
5d0fb150 GK |
3842 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3843 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd | 3844 | |
c5514d0e | 3845 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3846 | |
ff9006dd | 3847 | if (drc) { |
09d876ce | 3848 | spapr_drc_attach(drc, dev, &local_err); |
ff9006dd | 3849 | if (local_err) { |
ff9006dd IM |
3850 | error_propagate(errp, local_err); |
3851 | return; | |
3852 | } | |
ff9006dd | 3853 | |
94fd9cba LV |
3854 | if (hotplugged) { |
3855 | /* | |
3856 | * Send hotplug notification interrupt to the guest only | |
3857 | * in case of hotplugged CPUs. | |
3858 | */ | |
3859 | spapr_hotplug_req_add_by_index(drc); | |
3860 | } else { | |
3861 | spapr_drc_reset(drc); | |
3862 | } | |
ff9006dd | 3863 | } |
94fd9cba | 3864 | |
535455fd | 3865 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3866 | |
3867 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 | 3868 | for (i = 0; i < cc->nr_threads; i++) { |
bc877283 | 3869 | cs = CPU(core->threads[i]); |
46f7afa3 GK |
3870 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3871 | } | |
3872 | } | |
b1e81567 GK |
3873 | |
3874 | /* | |
3875 | * Set compatibility mode to match the boot CPU, which was either set | |
3876 | * by the machine reset code or by CAS. | |
3877 | */ | |
3878 | if (hotplugged) { | |
3879 | for (i = 0; i < cc->nr_threads; i++) { | |
3880 | ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, | |
3881 | &local_err); | |
3882 | if (local_err) { | |
3883 | error_propagate(errp, local_err); | |
3884 | return; | |
3885 | } | |
3886 | } | |
3887 | } | |
ff9006dd IM |
3888 | } |
3889 | ||
3890 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3891 | Error **errp) | |
3892 | { | |
3893 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3894 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3895 | Error *local_err = NULL; |
3896 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3897 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3898 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3899 | CPUArchId *core_slot; |
3900 | int index; | |
fe6b6346 | 3901 | unsigned int smp_threads = machine->smp.threads; |
ff9006dd | 3902 | |
c5514d0e | 3903 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3904 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3905 | goto out; | |
3906 | } | |
3907 | ||
3908 | if (strcmp(base_core_type, type)) { | |
3909 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3910 | goto out; | |
3911 | } | |
3912 | ||
3913 | if (cc->core_id % smp_threads) { | |
3914 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3915 | goto out; | |
3916 | } | |
3917 | ||
459264ef DG |
3918 | /* |
3919 | * In general we should have homogeneous threads-per-core, but old | |
3920 | * (pre hotplug support) machine types allow the last core to have | |
3921 | * reduced threads as a compatibility hack for when we allowed | |
3922 | * total vcpus not a multiple of threads-per-core. | |
3923 | */ | |
3924 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3925 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3926 | cc->nr_threads, smp_threads); |
df8658de | 3927 | goto out; |
8149e299 DG |
3928 | } |
3929 | ||
535455fd IM |
3930 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3931 | if (!core_slot) { | |
ff9006dd IM |
3932 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3933 | goto out; | |
3934 | } | |
3935 | ||
535455fd | 3936 | if (core_slot->cpu) { |
ff9006dd IM |
3937 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3938 | goto out; | |
3939 | } | |
3940 | ||
a0ceb640 | 3941 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3942 | |
ff9006dd | 3943 | out: |
ff9006dd IM |
3944 | error_propagate(errp, local_err); |
3945 | } | |
3946 | ||
ce2918cb | 3947 | int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, |
bb2bdd81 GK |
3948 | void *fdt, int *fdt_start_offset, Error **errp) |
3949 | { | |
ce2918cb | 3950 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); |
bb2bdd81 GK |
3951 | int intc_phandle; |
3952 | ||
3953 | intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); | |
3954 | if (intc_phandle <= 0) { | |
3955 | return -1; | |
3956 | } | |
3957 | ||
8cbe71ec | 3958 | if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { |
bb2bdd81 GK |
3959 | error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); |
3960 | return -1; | |
3961 | } | |
3962 | ||
3963 | /* generally SLOF creates these, for hotplug it's up to QEMU */ | |
3964 | _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); | |
3965 | ||
3966 | return 0; | |
3967 | } | |
3968 | ||
3969 | static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3970 | Error **errp) | |
3971 | { | |
ce2918cb DG |
3972 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3973 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); | |
3974 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
bb2bdd81 GK |
3975 | const unsigned windows_supported = spapr_phb_windows_supported(sphb); |
3976 | ||
3977 | if (dev->hotplugged && !smc->dr_phb_enabled) { | |
3978 | error_setg(errp, "PHB hotplug not supported for this machine"); | |
3979 | return; | |
3980 | } | |
3981 | ||
3982 | if (sphb->index == (uint32_t)-1) { | |
3983 | error_setg(errp, "\"index\" for PAPR PHB is mandatory"); | |
3984 | return; | |
3985 | } | |
3986 | ||
3987 | /* | |
3988 | * This will check that sphb->index doesn't exceed the maximum number of | |
3989 | * PHBs for the current machine type. | |
3990 | */ | |
3991 | smc->phb_placement(spapr, sphb->index, | |
3992 | &sphb->buid, &sphb->io_win_addr, | |
3993 | &sphb->mem_win_addr, &sphb->mem64_win_addr, | |
ec132efa AK |
3994 | windows_supported, sphb->dma_liobn, |
3995 | &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, | |
3996 | errp); | |
bb2bdd81 GK |
3997 | } |
3998 | ||
3999 | static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
4000 | Error **errp) | |
4001 | { | |
ce2918cb DG |
4002 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
4003 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
4004 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); | |
4005 | SpaprDrc *drc; | |
bb2bdd81 GK |
4006 | bool hotplugged = spapr_drc_hotplugged(dev); |
4007 | Error *local_err = NULL; | |
4008 | ||
4009 | if (!smc->dr_phb_enabled) { | |
4010 | return; | |
4011 | } | |
4012 | ||
4013 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); | |
4014 | /* hotplug hooks should check it's enabled before getting this far */ | |
4015 | assert(drc); | |
4016 | ||
8e5c952b | 4017 | spapr_drc_attach(drc, dev, &local_err); |
bb2bdd81 GK |
4018 | if (local_err) { |
4019 | error_propagate(errp, local_err); | |
4020 | return; | |
4021 | } | |
4022 | ||
4023 | if (hotplugged) { | |
4024 | spapr_hotplug_req_add_by_index(drc); | |
4025 | } else { | |
4026 | spapr_drc_reset(drc); | |
4027 | } | |
4028 | } | |
4029 | ||
4030 | void spapr_phb_release(DeviceState *dev) | |
4031 | { | |
4032 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); | |
4033 | ||
4034 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
07578b0a | 4035 | object_unparent(OBJECT(dev)); |
bb2bdd81 GK |
4036 | } |
4037 | ||
4038 | static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
4039 | { | |
b69c3c21 | 4040 | object_property_set_bool(OBJECT(dev), false, "realized", &error_abort); |
bb2bdd81 GK |
4041 | } |
4042 | ||
4043 | static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, | |
4044 | DeviceState *dev, Error **errp) | |
4045 | { | |
ce2918cb DG |
4046 | SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); |
4047 | SpaprDrc *drc; | |
bb2bdd81 GK |
4048 | |
4049 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); | |
4050 | assert(drc); | |
4051 | ||
4052 | if (!spapr_drc_unplug_requested(drc)) { | |
4053 | spapr_drc_detach(drc); | |
4054 | spapr_hotplug_req_remove_by_index(drc); | |
4055 | } | |
4056 | } | |
4057 | ||
0fb6bd07 MR |
4058 | static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
4059 | Error **errp) | |
4060 | { | |
4061 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
4062 | SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); | |
4063 | ||
4064 | if (spapr->tpm_proxy != NULL) { | |
4065 | error_setg(errp, "Only one TPM proxy can be specified for this machine"); | |
4066 | return; | |
4067 | } | |
4068 | ||
4069 | spapr->tpm_proxy = tpm_proxy; | |
4070 | } | |
4071 | ||
4072 | static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
4073 | { | |
4074 | SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
4075 | ||
b69c3c21 | 4076 | object_property_set_bool(OBJECT(dev), false, "realized", &error_abort); |
0fb6bd07 MR |
4077 | object_unparent(OBJECT(dev)); |
4078 | spapr->tpm_proxy = NULL; | |
4079 | } | |
4080 | ||
c20d332a BR |
4081 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
4082 | DeviceState *dev, Error **errp) | |
4083 | { | |
c20d332a | 4084 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
81985f3b | 4085 | spapr_memory_plug(hotplug_dev, dev, errp); |
af81cf32 BR |
4086 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4087 | spapr_core_plug(hotplug_dev, dev, errp); | |
bb2bdd81 GK |
4088 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4089 | spapr_phb_plug(hotplug_dev, dev, errp); | |
0fb6bd07 MR |
4090 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4091 | spapr_tpm_proxy_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
4092 | } |
4093 | } | |
4094 | ||
88432f44 DH |
4095 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, |
4096 | DeviceState *dev, Error **errp) | |
4097 | { | |
3ec71474 DH |
4098 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4099 | spapr_memory_unplug(hotplug_dev, dev); | |
a4261be1 DH |
4100 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
4101 | spapr_core_unplug(hotplug_dev, dev); | |
bb2bdd81 GK |
4102 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4103 | spapr_phb_unplug(hotplug_dev, dev); | |
0fb6bd07 MR |
4104 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4105 | spapr_tpm_proxy_unplug(hotplug_dev, dev); | |
3ec71474 | 4106 | } |
88432f44 DH |
4107 | } |
4108 | ||
cf632463 BR |
4109 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
4110 | DeviceState *dev, Error **errp) | |
4111 | { | |
ce2918cb | 4112 | SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
c86c1aff | 4113 | MachineClass *mc = MACHINE_GET_CLASS(sms); |
ce2918cb | 4114 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
cf632463 BR |
4115 | |
4116 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
4117 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
4118 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
4119 | } else { | |
4120 | /* NOTE: this means there is a window after guest reset, prior to | |
4121 | * CAS negotiation, where unplug requests will fail due to the | |
4122 | * capability not being detected yet. This is a bit different than | |
4123 | * the case with PCI unplug, where the events will be queued and | |
4124 | * eventually handled by the guest after boot | |
4125 | */ | |
4126 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
4127 | } | |
6f4b5c3e | 4128 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 4129 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
4130 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
4131 | return; | |
4132 | } | |
115debf2 | 4133 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
bb2bdd81 GK |
4134 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4135 | if (!smc->dr_phb_enabled) { | |
4136 | error_setg(errp, "PHB hot unplug not supported on this machine"); | |
4137 | return; | |
4138 | } | |
4139 | spapr_phb_unplug_request(hotplug_dev, dev, errp); | |
0fb6bd07 MR |
4140 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { |
4141 | spapr_tpm_proxy_unplug(hotplug_dev, dev); | |
c20d332a BR |
4142 | } |
4143 | } | |
4144 | ||
94a94e4c BR |
4145 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
4146 | DeviceState *dev, Error **errp) | |
4147 | { | |
c871bc70 LV |
4148 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
4149 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
4150 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c | 4151 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
bb2bdd81 GK |
4152 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { |
4153 | spapr_phb_pre_plug(hotplug_dev, dev, errp); | |
94a94e4c BR |
4154 | } |
4155 | } | |
4156 | ||
7ebaf795 BR |
4157 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
4158 | DeviceState *dev) | |
c20d332a | 4159 | { |
94a94e4c | 4160 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
bb2bdd81 | 4161 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || |
0fb6bd07 MR |
4162 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || |
4163 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { | |
c20d332a BR |
4164 | return HOTPLUG_HANDLER(machine); |
4165 | } | |
cb600087 DG |
4166 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
4167 | PCIDevice *pcidev = PCI_DEVICE(dev); | |
4168 | PCIBus *root = pci_device_root_bus(pcidev); | |
4169 | SpaprPhbState *phb = | |
4170 | (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), | |
4171 | TYPE_SPAPR_PCI_HOST_BRIDGE); | |
4172 | ||
4173 | if (phb) { | |
4174 | return HOTPLUG_HANDLER(phb); | |
4175 | } | |
4176 | } | |
c20d332a BR |
4177 | return NULL; |
4178 | } | |
4179 | ||
ea089eeb IM |
4180 | static CpuInstanceProperties |
4181 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 4182 | { |
ea089eeb IM |
4183 | CPUArchId *core_slot; |
4184 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
4185 | ||
4186 | /* make sure possible_cpu are intialized */ | |
4187 | mc->possible_cpu_arch_ids(machine); | |
4188 | /* get CPU core slot containing thread that matches cpu_index */ | |
4189 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
4190 | assert(core_slot); | |
4191 | return core_slot->props; | |
20bb648d DG |
4192 | } |
4193 | ||
79e07936 IM |
4194 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
4195 | { | |
aa570207 | 4196 | return idx / ms->smp.cores % ms->numa_state->num_nodes; |
79e07936 IM |
4197 | } |
4198 | ||
535455fd IM |
4199 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
4200 | { | |
4201 | int i; | |
fe6b6346 LX |
4202 | unsigned int smp_threads = machine->smp.threads; |
4203 | unsigned int smp_cpus = machine->smp.cpus; | |
d342eb76 | 4204 | const char *core_type; |
fe6b6346 | 4205 | int spapr_max_cores = machine->smp.max_cpus / smp_threads; |
535455fd IM |
4206 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
4207 | ||
c5514d0e | 4208 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
4209 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
4210 | } | |
4211 | if (machine->possible_cpus) { | |
4212 | assert(machine->possible_cpus->len == spapr_max_cores); | |
4213 | return machine->possible_cpus; | |
4214 | } | |
4215 | ||
d342eb76 IM |
4216 | core_type = spapr_get_cpu_core_type(machine->cpu_type); |
4217 | if (!core_type) { | |
4218 | error_report("Unable to find sPAPR CPU Core definition"); | |
4219 | exit(1); | |
4220 | } | |
4221 | ||
535455fd IM |
4222 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
4223 | sizeof(CPUArchId) * spapr_max_cores); | |
4224 | machine->possible_cpus->len = spapr_max_cores; | |
4225 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
4226 | int core_id = i * smp_threads; | |
4227 | ||
d342eb76 | 4228 | machine->possible_cpus->cpus[i].type = core_type; |
f2d672c2 | 4229 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
4230 | machine->possible_cpus->cpus[i].arch_id = core_id; |
4231 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
4232 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
4233 | } |
4234 | return machine->possible_cpus; | |
4235 | } | |
4236 | ||
ce2918cb | 4237 | static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, |
daa23699 DG |
4238 | uint64_t *buid, hwaddr *pio, |
4239 | hwaddr *mmio32, hwaddr *mmio64, | |
ec132efa AK |
4240 | unsigned n_dma, uint32_t *liobns, |
4241 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) | |
6737d9ad | 4242 | { |
357d1e3b DG |
4243 | /* |
4244 | * New-style PHB window placement. | |
4245 | * | |
4246 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
4247 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
4248 | * windows. | |
4249 | * | |
4250 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
4251 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
4252 | * | |
4253 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
4254 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
4255 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
4256 | * 1TiB 64-bit MMIO windows for each PHB. | |
4257 | */ | |
6737d9ad | 4258 | const uint64_t base_buid = 0x800000020000000ULL; |
6737d9ad DG |
4259 | int i; |
4260 | ||
357d1e3b DG |
4261 | /* Sanity check natural alignments */ |
4262 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
4263 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
4264 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
4265 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
4266 | /* Sanity check bounds */ | |
25e6a118 MT |
4267 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
4268 | SPAPR_PCI_MEM32_WIN_SIZE); | |
4269 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
4270 | SPAPR_PCI_MEM64_WIN_SIZE); | |
4271 | ||
4272 | if (index >= SPAPR_MAX_PHBS) { | |
4273 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
4274 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
4275 | return; |
4276 | } | |
4277 | ||
4278 | *buid = base_buid + index; | |
4279 | for (i = 0; i < n_dma; ++i) { | |
4280 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4281 | } | |
4282 | ||
357d1e3b DG |
4283 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
4284 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
4285 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
ec132efa AK |
4286 | |
4287 | *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; | |
4288 | *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; | |
6737d9ad DG |
4289 | } |
4290 | ||
7844e12b CLG |
4291 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
4292 | { | |
ce2918cb | 4293 | SpaprMachineState *spapr = SPAPR_MACHINE(dev); |
7844e12b CLG |
4294 | |
4295 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
4296 | } | |
4297 | ||
4298 | static void spapr_ics_resend(XICSFabric *dev) | |
4299 | { | |
ce2918cb | 4300 | SpaprMachineState *spapr = SPAPR_MACHINE(dev); |
7844e12b CLG |
4301 | |
4302 | ics_resend(spapr->ics); | |
4303 | } | |
4304 | ||
81210c20 | 4305 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 4306 | { |
2e886fb3 | 4307 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 4308 | |
a28b9a5a | 4309 | return cpu ? spapr_cpu_state(cpu)->icp : NULL; |
b2fc59aa CLG |
4310 | } |
4311 | ||
6449da45 CLG |
4312 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
4313 | Monitor *mon) | |
4314 | { | |
ce2918cb | 4315 | SpaprMachineState *spapr = SPAPR_MACHINE(obj); |
6449da45 | 4316 | |
328d8eb2 | 4317 | spapr_irq_print_info(spapr, mon); |
f041d6af GK |
4318 | monitor_printf(mon, "irqchip: %s\n", |
4319 | kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); | |
6449da45 CLG |
4320 | } |
4321 | ||
baa45b17 CLG |
4322 | /* |
4323 | * This is a XIVE only operation | |
4324 | */ | |
932de7ae CLG |
4325 | static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, |
4326 | uint8_t nvt_blk, uint32_t nvt_idx, | |
4327 | bool cam_ignore, uint8_t priority, | |
4328 | uint32_t logic_serv, XiveTCTXMatch *match) | |
4329 | { | |
4330 | SpaprMachineState *spapr = SPAPR_MACHINE(xfb); | |
baa45b17 | 4331 | XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); |
932de7ae CLG |
4332 | XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); |
4333 | int count; | |
4334 | ||
932de7ae CLG |
4335 | count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, |
4336 | priority, logic_serv, match); | |
4337 | if (count < 0) { | |
4338 | return count; | |
4339 | } | |
4340 | ||
4341 | /* | |
4342 | * When we implement the save and restore of the thread interrupt | |
4343 | * contexts in the enter/exit CPU handlers of the machine and the | |
4344 | * escalations in QEMU, we should be able to handle non dispatched | |
4345 | * vCPUs. | |
4346 | * | |
4347 | * Until this is done, the sPAPR machine should find at least one | |
4348 | * matching context always. | |
4349 | */ | |
4350 | if (count == 0) { | |
4351 | qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", | |
4352 | nvt_blk, nvt_idx); | |
4353 | } | |
4354 | ||
4355 | return count; | |
4356 | } | |
4357 | ||
14bb4486 | 4358 | int spapr_get_vcpu_id(PowerPCCPU *cpu) |
2e886fb3 | 4359 | { |
b1a568c1 | 4360 | return cpu->vcpu_id; |
2e886fb3 SB |
4361 | } |
4362 | ||
648edb64 GK |
4363 | void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) |
4364 | { | |
ce2918cb | 4365 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
fe6b6346 | 4366 | MachineState *ms = MACHINE(spapr); |
648edb64 GK |
4367 | int vcpu_id; |
4368 | ||
5d0fb150 | 4369 | vcpu_id = spapr_vcpu_id(spapr, cpu_index); |
648edb64 GK |
4370 | |
4371 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { | |
4372 | error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); | |
4373 | error_append_hint(errp, "Adjust the number of cpus to %d " | |
4374 | "or try to raise the number of threads per core\n", | |
fe6b6346 | 4375 | vcpu_id * ms->smp.threads / spapr->vsmt); |
648edb64 GK |
4376 | return; |
4377 | } | |
4378 | ||
4379 | cpu->vcpu_id = vcpu_id; | |
4380 | } | |
4381 | ||
2e886fb3 SB |
4382 | PowerPCCPU *spapr_find_cpu(int vcpu_id) |
4383 | { | |
4384 | CPUState *cs; | |
4385 | ||
4386 | CPU_FOREACH(cs) { | |
4387 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
4388 | ||
14bb4486 | 4389 | if (spapr_get_vcpu_id(cpu) == vcpu_id) { |
2e886fb3 SB |
4390 | return cpu; |
4391 | } | |
4392 | } | |
4393 | ||
4394 | return NULL; | |
4395 | } | |
4396 | ||
03ef074c NP |
4397 | static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) |
4398 | { | |
4399 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); | |
4400 | ||
4401 | /* These are only called by TCG, KVM maintains dispatch state */ | |
4402 | ||
3a6e6224 | 4403 | spapr_cpu->prod = false; |
03ef074c NP |
4404 | if (spapr_cpu->vpa_addr) { |
4405 | CPUState *cs = CPU(cpu); | |
4406 | uint32_t dispatch; | |
4407 | ||
4408 | dispatch = ldl_be_phys(cs->as, | |
4409 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); | |
4410 | dispatch++; | |
4411 | if ((dispatch & 1) != 0) { | |
4412 | qemu_log_mask(LOG_GUEST_ERROR, | |
4413 | "VPA: incorrect dispatch counter value for " | |
4414 | "dispatched partition %u, correcting.\n", dispatch); | |
4415 | dispatch++; | |
4416 | } | |
4417 | stl_be_phys(cs->as, | |
4418 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); | |
4419 | } | |
4420 | } | |
4421 | ||
4422 | static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) | |
4423 | { | |
4424 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); | |
4425 | ||
4426 | if (spapr_cpu->vpa_addr) { | |
4427 | CPUState *cs = CPU(cpu); | |
4428 | uint32_t dispatch; | |
4429 | ||
4430 | dispatch = ldl_be_phys(cs->as, | |
4431 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); | |
4432 | dispatch++; | |
4433 | if ((dispatch & 1) != 1) { | |
4434 | qemu_log_mask(LOG_GUEST_ERROR, | |
4435 | "VPA: incorrect dispatch counter value for " | |
4436 | "preempted partition %u, correcting.\n", dispatch); | |
4437 | dispatch++; | |
4438 | } | |
4439 | stl_be_phys(cs->as, | |
4440 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); | |
4441 | } | |
4442 | } | |
4443 | ||
29ee3247 AK |
4444 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
4445 | { | |
4446 | MachineClass *mc = MACHINE_CLASS(oc); | |
ce2918cb | 4447 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 4448 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 4449 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 4450 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 4451 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 4452 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 4453 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
932de7ae | 4454 | XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); |
958db90c | 4455 | |
0eb9054c | 4456 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
907aac2f | 4457 | mc->ignore_boot_device_suffixes = true; |
fc9f38c3 DG |
4458 | |
4459 | /* | |
4460 | * We set up the default / latest behaviour here. The class_init | |
4461 | * functions for the specific versioned machine types can override | |
4462 | * these details for backwards compatibility | |
4463 | */ | |
bcb5ce08 DG |
4464 | mc->init = spapr_machine_init; |
4465 | mc->reset = spapr_machine_reset; | |
958db90c | 4466 | mc->block_default_type = IF_SCSI; |
6244bb7e | 4467 | mc->max_cpus = 1024; |
958db90c | 4468 | mc->no_parallel = 1; |
5b2128d2 | 4469 | mc->default_boot_order = ""; |
d23b6caa | 4470 | mc->default_ram_size = 512 * MiB; |
ab74e543 | 4471 | mc->default_ram_id = "ppc_spapr.ram"; |
29f9cef3 | 4472 | mc->default_display = "std"; |
958db90c | 4473 | mc->kvm_type = spapr_kvm_type; |
7da79a16 | 4474 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); |
e4024630 | 4475 | mc->pci_allow_0_address = true; |
debbdc00 | 4476 | assert(!mc->get_hotplug_handler); |
7ebaf795 | 4477 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 4478 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 4479 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 4480 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 4481 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 4482 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 4483 | hc->unplug_request = spapr_machine_device_unplug_request; |
88432f44 | 4484 | hc->unplug = spapr_machine_device_unplug; |
00b4fbe2 | 4485 | |
fc9f38c3 | 4486 | smc->dr_lmb_enabled = true; |
fea35ca4 | 4487 | smc->update_dt_enabled = true; |
34a6b015 | 4488 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); |
c5514d0e | 4489 | mc->has_hotpluggable_cpus = true; |
ee3a71e3 | 4490 | mc->nvdimm_supported = true; |
52b81ab5 | 4491 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 4492 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 4493 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 4494 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 4495 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
4496 | vhc->hpt_mask = spapr_hpt_mask; |
4497 | vhc->map_hptes = spapr_map_hptes; | |
4498 | vhc->unmap_hptes = spapr_unmap_hptes; | |
a2dd4e83 BH |
4499 | vhc->hpte_set_c = spapr_hpte_set_c; |
4500 | vhc->hpte_set_r = spapr_hpte_set_r; | |
79825f4d | 4501 | vhc->get_pate = spapr_get_pate; |
1ec26c75 | 4502 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
03ef074c NP |
4503 | vhc->cpu_exec_enter = spapr_cpu_exec_enter; |
4504 | vhc->cpu_exec_exit = spapr_cpu_exec_exit; | |
7844e12b CLG |
4505 | xic->ics_get = spapr_ics_get; |
4506 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 4507 | xic->icp_get = spapr_icp_get; |
6449da45 | 4508 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
4509 | /* Force NUMA node memory size to be a multiple of |
4510 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
4511 | * in which LMBs are represented and hot-added | |
4512 | */ | |
4513 | mc->numa_mem_align_shift = 28; | |
cd5ff833 | 4514 | mc->numa_mem_supported = true; |
0533ef5f | 4515 | mc->auto_enable_numa = true; |
33face6b | 4516 | |
4e5fe368 SJS |
4517 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
4518 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; | |
4519 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; | |
2782ad4c SJS |
4520 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; |
4521 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; | |
4522 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; | |
2309832a | 4523 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ |
b9a477b7 | 4524 | smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; |
edaa7995 | 4525 | smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; |
37965dfe | 4526 | smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; |
8af7e1fe | 4527 | smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; |
40c2281c | 4528 | spapr_caps_add_properties(smc); |
bd94bc06 | 4529 | smc->irq = &spapr_irq_dual; |
dae5e39a | 4530 | smc->dr_phb_enabled = true; |
6c3829a2 | 4531 | smc->linux_pci_probe = true; |
29cb4187 | 4532 | smc->smp_threads_vsmt = true; |
54255c1f | 4533 | smc->nr_xirqs = SPAPR_NR_XIRQS; |
932de7ae | 4534 | xfc->match_nvt = spapr_match_nvt; |
29ee3247 AK |
4535 | } |
4536 | ||
4537 | static const TypeInfo spapr_machine_info = { | |
4538 | .name = TYPE_SPAPR_MACHINE, | |
4539 | .parent = TYPE_MACHINE, | |
4aee7362 | 4540 | .abstract = true, |
ce2918cb | 4541 | .instance_size = sizeof(SpaprMachineState), |
bcb5ce08 | 4542 | .instance_init = spapr_instance_init, |
87bbdd9c | 4543 | .instance_finalize = spapr_machine_finalizefn, |
ce2918cb | 4544 | .class_size = sizeof(SpaprMachineClass), |
29ee3247 | 4545 | .class_init = spapr_machine_class_init, |
71461b0f AK |
4546 | .interfaces = (InterfaceInfo[]) { |
4547 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 4548 | { TYPE_NMI }, |
c20d332a | 4549 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 4550 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 4551 | { TYPE_XICS_FABRIC }, |
6449da45 | 4552 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
932de7ae | 4553 | { TYPE_XIVE_FABRIC }, |
71461b0f AK |
4554 | { } |
4555 | }, | |
29ee3247 AK |
4556 | }; |
4557 | ||
a7849268 MT |
4558 | static void spapr_machine_latest_class_options(MachineClass *mc) |
4559 | { | |
4560 | mc->alias = "pseries"; | |
ea0ac7f6 | 4561 | mc->is_default = true; |
a7849268 MT |
4562 | } |
4563 | ||
fccbc785 | 4564 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
4565 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
4566 | void *data) \ | |
4567 | { \ | |
4568 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
4569 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 | 4570 | if (latest) { \ |
a7849268 | 4571 | spapr_machine_latest_class_options(mc); \ |
fccbc785 | 4572 | } \ |
5013c547 | 4573 | } \ |
5013c547 DG |
4574 | static const TypeInfo spapr_machine_##suffix##_info = { \ |
4575 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
4576 | .parent = TYPE_SPAPR_MACHINE, \ | |
4577 | .class_init = spapr_machine_##suffix##_class_init, \ | |
5013c547 DG |
4578 | }; \ |
4579 | static void spapr_machine_register_##suffix(void) \ | |
4580 | { \ | |
4581 | type_register(&spapr_machine_##suffix##_info); \ | |
4582 | } \ | |
0e6aac87 | 4583 | type_init(spapr_machine_register_##suffix) |
5013c547 | 4584 | |
541aaa1d CH |
4585 | /* |
4586 | * pseries-5.1 | |
4587 | */ | |
4588 | static void spapr_machine_5_1_class_options(MachineClass *mc) | |
4589 | { | |
4590 | /* Defaults for the latest behaviour inherited from the base class */ | |
4591 | } | |
4592 | ||
4593 | DEFINE_SPAPR_MACHINE(5_1, "5.1", true); | |
4594 | ||
3eb74d20 CH |
4595 | /* |
4596 | * pseries-5.0 | |
4597 | */ | |
4598 | static void spapr_machine_5_0_class_options(MachineClass *mc) | |
4599 | { | |
541aaa1d CH |
4600 | spapr_machine_5_1_class_options(mc); |
4601 | compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); | |
3eb74d20 CH |
4602 | } |
4603 | ||
541aaa1d | 4604 | DEFINE_SPAPR_MACHINE(5_0, "5.0", false); |
3eb74d20 | 4605 | |
9aec2e52 CH |
4606 | /* |
4607 | * pseries-4.2 | |
4608 | */ | |
4609 | static void spapr_machine_4_2_class_options(MachineClass *mc) | |
4610 | { | |
37965dfe DG |
4611 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4612 | ||
3eb74d20 | 4613 | spapr_machine_5_0_class_options(mc); |
5f258577 | 4614 | compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); |
37965dfe | 4615 | smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; |
8af7e1fe | 4616 | smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; |
1052ab67 | 4617 | smc->rma_limit = 16 * GiB; |
ee3a71e3 | 4618 | mc->nvdimm_supported = false; |
9aec2e52 CH |
4619 | } |
4620 | ||
3eb74d20 | 4621 | DEFINE_SPAPR_MACHINE(4_2, "4.2", false); |
9aec2e52 | 4622 | |
9bf2650b CH |
4623 | /* |
4624 | * pseries-4.1 | |
4625 | */ | |
4626 | static void spapr_machine_4_1_class_options(MachineClass *mc) | |
4627 | { | |
6c3829a2 | 4628 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
d15d4ad6 DG |
4629 | static GlobalProperty compat[] = { |
4630 | /* Only allow 4kiB and 64kiB IOMMU pagesizes */ | |
4631 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, | |
4632 | }; | |
4633 | ||
9aec2e52 | 4634 | spapr_machine_4_2_class_options(mc); |
6c3829a2 | 4635 | smc->linux_pci_probe = false; |
29cb4187 | 4636 | smc->smp_threads_vsmt = false; |
9aec2e52 | 4637 | compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); |
d15d4ad6 | 4638 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
9bf2650b CH |
4639 | } |
4640 | ||
9aec2e52 | 4641 | DEFINE_SPAPR_MACHINE(4_1, "4.1", false); |
9bf2650b | 4642 | |
84e060bf AW |
4643 | /* |
4644 | * pseries-4.0 | |
4645 | */ | |
eb3cba82 | 4646 | static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, |
ec132efa AK |
4647 | uint64_t *buid, hwaddr *pio, |
4648 | hwaddr *mmio32, hwaddr *mmio64, | |
4649 | unsigned n_dma, uint32_t *liobns, | |
4650 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) | |
4651 | { | |
4652 | spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, | |
4653 | nv2gpa, nv2atsd, errp); | |
4654 | *nv2gpa = 0; | |
4655 | *nv2atsd = 0; | |
4656 | } | |
4657 | ||
eb3cba82 DG |
4658 | static void spapr_machine_4_0_class_options(MachineClass *mc) |
4659 | { | |
4660 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); | |
4661 | ||
4662 | spapr_machine_4_1_class_options(mc); | |
4663 | compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); | |
4664 | smc->phb_placement = phb_placement_4_0; | |
bd94bc06 | 4665 | smc->irq = &spapr_irq_xics; |
3725ef1a | 4666 | smc->pre_4_1_migration = true; |
eb3cba82 DG |
4667 | } |
4668 | ||
4669 | DEFINE_SPAPR_MACHINE(4_0, "4.0", false); | |
4670 | ||
4671 | /* | |
4672 | * pseries-3.1 | |
4673 | */ | |
d45360d9 CLG |
4674 | static void spapr_machine_3_1_class_options(MachineClass *mc) |
4675 | { | |
ce2918cb | 4676 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
fea35ca4 | 4677 | |
84e060bf | 4678 | spapr_machine_4_0_class_options(mc); |
abd93cc7 | 4679 | compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); |
27461d69 | 4680 | |
34a6b015 | 4681 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
fea35ca4 | 4682 | smc->update_dt_enabled = false; |
dae5e39a | 4683 | smc->dr_phb_enabled = false; |
0a794529 | 4684 | smc->broken_host_serial_model = true; |
2782ad4c SJS |
4685 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
4686 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; | |
4687 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; | |
edaa7995 | 4688 | smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; |
d45360d9 CLG |
4689 | } |
4690 | ||
84e060bf | 4691 | DEFINE_SPAPR_MACHINE(3_1, "3.1", false); |
d45360d9 | 4692 | |
8a4fd427 | 4693 | /* |
d8c0c7af | 4694 | * pseries-3.0 |
8a4fd427 | 4695 | */ |
d45360d9 | 4696 | |
d8c0c7af | 4697 | static void spapr_machine_3_0_class_options(MachineClass *mc) |
8a4fd427 | 4698 | { |
ce2918cb | 4699 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
82cffa2e | 4700 | |
d45360d9 | 4701 | spapr_machine_3_1_class_options(mc); |
ddb3235d | 4702 | compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); |
82cffa2e CLG |
4703 | |
4704 | smc->legacy_irq_allocation = true; | |
54255c1f | 4705 | smc->nr_xirqs = 0x400; |
ae837402 | 4706 | smc->irq = &spapr_irq_xics_legacy; |
8a4fd427 DG |
4707 | } |
4708 | ||
d45360d9 | 4709 | DEFINE_SPAPR_MACHINE(3_0, "3.0", false); |
8a4fd427 | 4710 | |
2b615412 DG |
4711 | /* |
4712 | * pseries-2.12 | |
4713 | */ | |
2b615412 DG |
4714 | static void spapr_machine_2_12_class_options(MachineClass *mc) |
4715 | { | |
ce2918cb | 4716 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
88cbe073 | 4717 | static GlobalProperty compat[] = { |
6c36bddf EH |
4718 | { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, |
4719 | { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, | |
88cbe073 | 4720 | }; |
2309832a | 4721 | |
d8c0c7af | 4722 | spapr_machine_3_0_class_options(mc); |
0d47310b | 4723 | compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); |
88cbe073 | 4724 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
2309832a | 4725 | |
e8937295 GK |
4726 | /* We depend on kvm_enabled() to choose a default value for the |
4727 | * hpt-max-page-size capability. Of course we can't do it here | |
4728 | * because this is too early and the HW accelerator isn't initialzed | |
4729 | * yet. Postpone this to machine init (see default_caps_with_cpu()). | |
4730 | */ | |
4731 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; | |
2b615412 DG |
4732 | } |
4733 | ||
8a4fd427 | 4734 | DEFINE_SPAPR_MACHINE(2_12, "2.12", false); |
2b615412 | 4735 | |
813f3cf6 SJS |
4736 | static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) |
4737 | { | |
ce2918cb | 4738 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
813f3cf6 SJS |
4739 | |
4740 | spapr_machine_2_12_class_options(mc); | |
4741 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; | |
4742 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; | |
4743 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; | |
4744 | } | |
4745 | ||
4746 | DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); | |
4747 | ||
e2676b16 GK |
4748 | /* |
4749 | * pseries-2.11 | |
4750 | */ | |
2b615412 | 4751 | |
e2676b16 GK |
4752 | static void spapr_machine_2_11_class_options(MachineClass *mc) |
4753 | { | |
ce2918cb | 4754 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ee76a09f | 4755 | |
2b615412 | 4756 | spapr_machine_2_12_class_options(mc); |
4e5fe368 | 4757 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
43df70a9 | 4758 | compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); |
e2676b16 GK |
4759 | } |
4760 | ||
2b615412 | 4761 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 4762 | |
3fa14fbe DG |
4763 | /* |
4764 | * pseries-2.10 | |
4765 | */ | |
e2676b16 | 4766 | |
3fa14fbe DG |
4767 | static void spapr_machine_2_10_class_options(MachineClass *mc) |
4768 | { | |
e2676b16 | 4769 | spapr_machine_2_11_class_options(mc); |
503224f4 | 4770 | compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); |
3fa14fbe DG |
4771 | } |
4772 | ||
e2676b16 | 4773 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 4774 | |
fa325e6c DG |
4775 | /* |
4776 | * pseries-2.9 | |
4777 | */ | |
3fa14fbe | 4778 | |
fa325e6c DG |
4779 | static void spapr_machine_2_9_class_options(MachineClass *mc) |
4780 | { | |
ce2918cb | 4781 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
88cbe073 | 4782 | static GlobalProperty compat[] = { |
6c36bddf | 4783 | { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, |
88cbe073 | 4784 | }; |
46f7afa3 | 4785 | |
3fa14fbe | 4786 | spapr_machine_2_10_class_options(mc); |
3e803152 | 4787 | compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); |
88cbe073 | 4788 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
3bfe5716 | 4789 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 4790 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 4791 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
4792 | } |
4793 | ||
3fa14fbe | 4794 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 4795 | |
db800b21 DG |
4796 | /* |
4797 | * pseries-2.8 | |
4798 | */ | |
fa325e6c | 4799 | |
db800b21 DG |
4800 | static void spapr_machine_2_8_class_options(MachineClass *mc) |
4801 | { | |
88cbe073 | 4802 | static GlobalProperty compat[] = { |
6c36bddf | 4803 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, |
88cbe073 MAL |
4804 | }; |
4805 | ||
fa325e6c | 4806 | spapr_machine_2_9_class_options(mc); |
edc24ccd | 4807 | compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); |
88cbe073 | 4808 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
55641213 | 4809 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
4810 | } |
4811 | ||
fa325e6c | 4812 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 4813 | |
1ea1eefc BR |
4814 | /* |
4815 | * pseries-2.7 | |
4816 | */ | |
357d1e3b | 4817 | |
ce2918cb | 4818 | static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, |
357d1e3b DG |
4819 | uint64_t *buid, hwaddr *pio, |
4820 | hwaddr *mmio32, hwaddr *mmio64, | |
ec132efa AK |
4821 | unsigned n_dma, uint32_t *liobns, |
4822 | hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) | |
357d1e3b DG |
4823 | { |
4824 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4825 | const uint64_t base_buid = 0x800000020000000ULL; | |
4826 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4827 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4828 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4829 | const uint32_t max_index = 255; | |
4830 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4831 | ||
4832 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4833 | hwaddr phb0_base, phb_base; | |
4834 | int i; | |
4835 | ||
0c9269a5 | 4836 | /* Do we have device memory? */ |
357d1e3b DG |
4837 | if (MACHINE(spapr)->maxram_size > ram_top) { |
4838 | /* Can't just use maxram_size, because there may be an | |
0c9269a5 DH |
4839 | * alignment gap between normal and device memory regions |
4840 | */ | |
b0c14ec4 DH |
4841 | ram_top = MACHINE(spapr)->device_memory->base + |
4842 | memory_region_size(&MACHINE(spapr)->device_memory->mr); | |
357d1e3b DG |
4843 | } |
4844 | ||
4845 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4846 | ||
4847 | if (index > max_index) { | |
4848 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4849 | max_index); | |
4850 | return; | |
4851 | } | |
4852 | ||
4853 | *buid = base_buid + index; | |
4854 | for (i = 0; i < n_dma; ++i) { | |
4855 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4856 | } | |
4857 | ||
4858 | phb_base = phb0_base + index * phb_spacing; | |
4859 | *pio = phb_base + pio_offset; | |
4860 | *mmio32 = phb_base + mmio_offset; | |
4861 | /* | |
4862 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4863 | * fallback behaviour of automatically splitting a large "32-bit" | |
4864 | * window into contiguous 32-bit and 64-bit windows | |
4865 | */ | |
ec132efa AK |
4866 | |
4867 | *nv2gpa = 0; | |
4868 | *nv2atsd = 0; | |
357d1e3b | 4869 | } |
db800b21 | 4870 | |
1ea1eefc BR |
4871 | static void spapr_machine_2_7_class_options(MachineClass *mc) |
4872 | { | |
ce2918cb | 4873 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
88cbe073 | 4874 | static GlobalProperty compat[] = { |
6c36bddf EH |
4875 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, |
4876 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, | |
4877 | { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, | |
4878 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, | |
88cbe073 | 4879 | }; |
3daa4a9f | 4880 | |
db800b21 | 4881 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4882 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
a140c199 | 4883 | mc->default_machine_opts = "modern-hotplug-events=off"; |
5a995064 | 4884 | compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); |
88cbe073 | 4885 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
357d1e3b | 4886 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4887 | } |
4888 | ||
db800b21 | 4889 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4890 | |
4b23699c DG |
4891 | /* |
4892 | * pseries-2.6 | |
4893 | */ | |
1ea1eefc | 4894 | |
4b23699c DG |
4895 | static void spapr_machine_2_6_class_options(MachineClass *mc) |
4896 | { | |
88cbe073 | 4897 | static GlobalProperty compat[] = { |
6c36bddf | 4898 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, |
88cbe073 MAL |
4899 | }; |
4900 | ||
1ea1eefc | 4901 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4902 | mc->has_hotpluggable_cpus = false; |
ff8f261f | 4903 | compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); |
88cbe073 | 4904 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
4b23699c DG |
4905 | } |
4906 | ||
1ea1eefc | 4907 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4908 | |
1c5f29bb DG |
4909 | /* |
4910 | * pseries-2.5 | |
4911 | */ | |
4b23699c | 4912 | |
5013c547 DG |
4913 | static void spapr_machine_2_5_class_options(MachineClass *mc) |
4914 | { | |
ce2918cb | 4915 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
88cbe073 | 4916 | static GlobalProperty compat[] = { |
6c36bddf | 4917 | { "spapr-vlan", "use-rx-buffer-pools", "off" }, |
88cbe073 | 4918 | }; |
57040d45 | 4919 | |
4b23699c | 4920 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4921 | smc->use_ohci_by_default = true; |
fe759610 | 4922 | compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); |
88cbe073 | 4923 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
1c5f29bb DG |
4924 | } |
4925 | ||
4b23699c | 4926 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4927 | |
4928 | /* | |
4929 | * pseries-2.4 | |
4930 | */ | |
80fd50f9 | 4931 | |
5013c547 DG |
4932 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4933 | { | |
ce2918cb | 4934 | SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
fc9f38c3 DG |
4935 | |
4936 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4937 | smc->dr_lmb_enabled = false; |
2f99b9c2 | 4938 | compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); |
1c5f29bb DG |
4939 | } |
4940 | ||
fccbc785 | 4941 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4942 | |
4943 | /* | |
4944 | * pseries-2.3 | |
4945 | */ | |
38ff32c6 | 4946 | |
5013c547 | 4947 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4948 | { |
88cbe073 | 4949 | static GlobalProperty compat[] = { |
6c36bddf | 4950 | { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, |
88cbe073 | 4951 | }; |
fc9f38c3 | 4952 | spapr_machine_2_4_class_options(mc); |
8995dd90 | 4953 | compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); |
88cbe073 | 4954 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
6026db45 | 4955 | } |
fccbc785 | 4956 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4957 | |
1c5f29bb DG |
4958 | /* |
4959 | * pseries-2.2 | |
4960 | */ | |
1c5f29bb | 4961 | |
5013c547 | 4962 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4963 | { |
88cbe073 | 4964 | static GlobalProperty compat[] = { |
6c36bddf | 4965 | { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, |
88cbe073 MAL |
4966 | }; |
4967 | ||
fc9f38c3 | 4968 | spapr_machine_2_3_class_options(mc); |
1c30044e | 4969 | compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); |
88cbe073 | 4970 | compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); |
f6d0656b | 4971 | mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; |
4aee7362 | 4972 | } |
fccbc785 | 4973 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4974 | |
1c5f29bb DG |
4975 | /* |
4976 | * pseries-2.1 | |
4977 | */ | |
3dab0244 | 4978 | |
5013c547 | 4979 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4980 | { |
fc9f38c3 | 4981 | spapr_machine_2_2_class_options(mc); |
c4fc5695 | 4982 | compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); |
d25228e7 | 4983 | } |
fccbc785 | 4984 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4985 | |
29ee3247 | 4986 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4987 | { |
29ee3247 | 4988 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4989 | } |
4990 | ||
29ee3247 | 4991 | type_init(spapr_machine_register_types) |