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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
fa98fbfc | 29 | #include "qapi/visitor.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
e35704ba | 31 | #include "sysemu/numa.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
03dd024f | 33 | #include "qemu/log.h" |
71461b0f | 34 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 35 | #include "elf.h" |
1422e32d | 36 | #include "net/net.h" |
ad440b4a | 37 | #include "sysemu/device_tree.h" |
9c17d615 | 38 | #include "sysemu/cpus.h" |
b3946626 | 39 | #include "sysemu/hw_accel.h" |
e97c3636 | 40 | #include "kvm_ppc.h" |
c4b63b7c | 41 | #include "migration/misc.h" |
84a899de | 42 | #include "migration/global_state.h" |
f2a8f0a6 | 43 | #include "migration/register.h" |
4be21d56 | 44 | #include "mmu-hash64.h" |
b4db5413 | 45 | #include "mmu-book3s-v3.h" |
7abd43ba | 46 | #include "cpu-models.h" |
3794d548 | 47 | #include "qom/cpu.h" |
9fdf0c29 DG |
48 | |
49 | #include "hw/boards.h" | |
0d09e41a | 50 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
51 | #include "hw/loader.h" |
52 | ||
7804c353 | 53 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
54 | #include "hw/ppc/spapr.h" |
55 | #include "hw/ppc/spapr_vio.h" | |
56 | #include "hw/pci-host/spapr.h" | |
57 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 58 | #include "hw/pci/msi.h" |
9fdf0c29 | 59 | |
83c9f4ca | 60 | #include "hw/pci/pci.h" |
71461b0f AK |
61 | #include "hw/scsi/scsi.h" |
62 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 63 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 64 | |
022c62cb | 65 | #include "exec/address-spaces.h" |
35139a59 | 66 | #include "hw/usb.h" |
1de7afc9 | 67 | #include "qemu/config-file.h" |
135a129a | 68 | #include "qemu/error-report.h" |
2a6593cb | 69 | #include "trace.h" |
34316482 | 70 | #include "hw/nmi.h" |
6449da45 | 71 | #include "hw/intc/intc.h" |
890c2b77 | 72 | |
68a27b20 | 73 | #include "hw/compat.h" |
f348b6d1 | 74 | #include "qemu/cutils.h" |
94a94e4c | 75 | #include "hw/ppc/spapr_cpu_core.h" |
2cc0e2e8 | 76 | #include "hw/mem/memory-device.h" |
68a27b20 | 77 | |
9fdf0c29 DG |
78 | #include <libfdt.h> |
79 | ||
4d8d5467 BH |
80 | /* SLOF memory layout: |
81 | * | |
82 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
83 | * device-tree, then position SLOF itself 31M below that | |
84 | * | |
85 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
86 | * and more | |
87 | * | |
88 | * We load our kernel at 4M, leaving space for SLOF initial image | |
89 | */ | |
38b02bd8 | 90 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 91 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 92 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
93 | #define FW_MAX_SIZE 0x400000 |
94 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
95 | #define FW_OVERHEAD 0x2800000 |
96 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 97 | |
4d8d5467 | 98 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 99 | |
0c103f8e DG |
100 | #define PHANDLE_XICP 0x00001111 |
101 | ||
5d0fb150 GK |
102 | /* These two functions implement the VCPU id numbering: one to compute them |
103 | * all and one to identify thread 0 of a VCORE. Any change to the first one | |
104 | * is likely to have an impact on the second one, so let's keep them close. | |
105 | */ | |
106 | static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) | |
107 | { | |
1a5008fc | 108 | assert(spapr->vsmt); |
5d0fb150 GK |
109 | return |
110 | (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; | |
111 | } | |
112 | static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, | |
113 | PowerPCCPU *cpu) | |
114 | { | |
1a5008fc | 115 | assert(spapr->vsmt); |
5d0fb150 GK |
116 | return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; |
117 | } | |
118 | ||
71cd4dac CLG |
119 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
120 | const char *type_ics, | |
121 | int nr_irqs, Error **errp) | |
c04d6cfa | 122 | { |
175d2aa0 | 123 | Error *local_err = NULL; |
71cd4dac | 124 | Object *obj; |
4e4169f7 | 125 | |
71cd4dac | 126 | obj = object_new(type_ics); |
175d2aa0 | 127 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
ad265631 GK |
128 | object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
129 | &error_abort); | |
175d2aa0 GK |
130 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
131 | if (local_err) { | |
132 | goto error; | |
133 | } | |
71cd4dac | 134 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
135 | if (local_err) { |
136 | goto error; | |
4e4169f7 | 137 | } |
4e4169f7 | 138 | |
71cd4dac | 139 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
140 | |
141 | error: | |
142 | error_propagate(errp, local_err); | |
143 | return NULL; | |
c04d6cfa AL |
144 | } |
145 | ||
46f7afa3 GK |
146 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
147 | { | |
148 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
149 | * and newer QEMUs don't even have them. In both cases, we don't want | |
150 | * to send anything on the wire. | |
151 | */ | |
152 | return false; | |
153 | } | |
154 | ||
155 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
156 | .name = "icp/server", | |
157 | .version_id = 1, | |
158 | .minimum_version_id = 1, | |
159 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
160 | .fields = (VMStateField[]) { | |
161 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
162 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
163 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
164 | VMSTATE_END_OF_LIST() | |
165 | }, | |
166 | }; | |
167 | ||
168 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
169 | { | |
170 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
171 | (void *)(uintptr_t) i); | |
172 | } | |
173 | ||
174 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
175 | { | |
176 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
177 | (void *)(uintptr_t) i); | |
178 | } | |
179 | ||
72194664 | 180 | static int xics_max_server_number(sPAPRMachineState *spapr) |
46f7afa3 | 181 | { |
1a5008fc | 182 | assert(spapr->vsmt); |
72194664 | 183 | return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); |
46f7afa3 GK |
184 | } |
185 | ||
71cd4dac | 186 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 187 | { |
71cd4dac | 188 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
844afc54 | 189 | Error *local_err = NULL; |
c04d6cfa | 190 | |
11ad93f6 | 191 | if (kvm_enabled()) { |
2192a930 | 192 | if (machine_kernel_irqchip_allowed(machine) && |
844afc54 | 193 | !xics_kvm_init(spapr, &local_err)) { |
71cd4dac | 194 | spapr->icp_type = TYPE_KVM_ICP; |
844afc54 GK |
195 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, |
196 | &local_err); | |
11ad93f6 | 197 | } |
71cd4dac | 198 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
844afc54 GK |
199 | error_prepend(&local_err, |
200 | "kernel_irqchip requested but unavailable: "); | |
201 | goto error; | |
11ad93f6 | 202 | } |
844afc54 GK |
203 | error_free(local_err); |
204 | local_err = NULL; | |
11ad93f6 DG |
205 | } |
206 | ||
71cd4dac | 207 | if (!spapr->ics) { |
f63ebfe0 | 208 | xics_spapr_init(spapr); |
71cd4dac | 209 | spapr->icp_type = TYPE_ICP; |
844afc54 GK |
210 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, |
211 | &local_err); | |
c04d6cfa | 212 | } |
844afc54 GK |
213 | |
214 | error: | |
215 | error_propagate(errp, local_err); | |
c04d6cfa AL |
216 | } |
217 | ||
833d4668 AK |
218 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
219 | int smt_threads) | |
220 | { | |
221 | int i, ret = 0; | |
222 | uint32_t servers_prop[smt_threads]; | |
223 | uint32_t gservers_prop[smt_threads * 2]; | |
14bb4486 | 224 | int index = spapr_get_vcpu_id(cpu); |
833d4668 | 225 | |
d6e166c0 DG |
226 | if (cpu->compat_pvr) { |
227 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
228 | if (ret < 0) { |
229 | return ret; | |
230 | } | |
231 | } | |
232 | ||
833d4668 AK |
233 | /* Build interrupt servers and gservers properties */ |
234 | for (i = 0; i < smt_threads; i++) { | |
235 | servers_prop[i] = cpu_to_be32(index + i); | |
236 | /* Hack, direct the group queues back to cpu 0 */ | |
237 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
238 | gservers_prop[i*2 + 1] = 0; | |
239 | } | |
240 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
241 | servers_prop, sizeof(servers_prop)); | |
242 | if (ret < 0) { | |
243 | return ret; | |
244 | } | |
245 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
246 | gservers_prop, sizeof(gservers_prop)); | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
99861ecb | 251 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 252 | { |
14bb4486 | 253 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
254 | uint32_t associativity[] = {cpu_to_be32(0x5), |
255 | cpu_to_be32(0x0), | |
256 | cpu_to_be32(0x0), | |
257 | cpu_to_be32(0x0), | |
15f8b142 | 258 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
259 | cpu_to_be32(index)}; |
260 | ||
261 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 262 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 263 | sizeof(associativity)); |
0da6f3fe BR |
264 | } |
265 | ||
86d5771a | 266 | /* Populate the "ibm,pa-features" property */ |
ee76a09f DG |
267 | static void spapr_populate_pa_features(sPAPRMachineState *spapr, |
268 | PowerPCCPU *cpu, | |
269 | void *fdt, int offset, | |
7abd43ba | 270 | bool legacy_guest) |
86d5771a SB |
271 | { |
272 | uint8_t pa_features_206[] = { 6, 0, | |
273 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
274 | uint8_t pa_features_207[] = { 24, 0, | |
275 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
276 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
277 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
278 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
279 | uint8_t pa_features_300[] = { 66, 0, |
280 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
281 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
282 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
283 | /* 6: DS207 */ | |
284 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
285 | /* 16: Vector */ | |
86d5771a | 286 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 287 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 288 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
289 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
290 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
291 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
292 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
293 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
294 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
295 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
296 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
297 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
298 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
299 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
300 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
301 | /* 60: NM atomic, 62: RNG */ | |
302 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
303 | }; | |
7abd43ba | 304 | uint8_t *pa_features = NULL; |
86d5771a SB |
305 | size_t pa_size; |
306 | ||
7abd43ba | 307 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
308 | pa_features = pa_features_206; |
309 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
310 | } |
311 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
312 | pa_features = pa_features_207; |
313 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
314 | } |
315 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
316 | pa_features = pa_features_300; |
317 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
318 | } |
319 | if (!pa_features) { | |
86d5771a SB |
320 | return; |
321 | } | |
322 | ||
26cd35b8 | 323 | if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { |
86d5771a SB |
324 | /* |
325 | * Note: we keep CI large pages off by default because a 64K capable | |
326 | * guest provisioned with large pages might otherwise try to map a qemu | |
327 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
328 | * even if that qemu runs on a 4k host. | |
329 | * We dd this bit back here if we are confident this is not an issue | |
330 | */ | |
331 | pa_features[3] |= 0x20; | |
332 | } | |
4e5fe368 | 333 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
86d5771a SB |
334 | pa_features[24] |= 0x80; /* Transactional memory support */ |
335 | } | |
e957f6a9 SB |
336 | if (legacy_guest && pa_size > 40) { |
337 | /* Workaround for broken kernels that attempt (guest) radix | |
338 | * mode when they can't handle it, if they see the radix bit set | |
339 | * in pa-features. So hide it from them. */ | |
340 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
341 | } | |
86d5771a SB |
342 | |
343 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
344 | } | |
345 | ||
28e02042 | 346 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 347 | { |
82677ed2 AK |
348 | int ret = 0, offset, cpus_offset; |
349 | CPUState *cs; | |
6e806cc3 | 350 | char cpu_model[32]; |
7f763a5d | 351 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 352 | |
82677ed2 AK |
353 | CPU_FOREACH(cs) { |
354 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
355 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 356 | int index = spapr_get_vcpu_id(cpu); |
abbc1247 | 357 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
6e806cc3 | 358 | |
5d0fb150 | 359 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
6e806cc3 BR |
360 | continue; |
361 | } | |
362 | ||
82677ed2 | 363 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 364 | |
82677ed2 AK |
365 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
366 | if (cpus_offset < 0) { | |
a4f3885c | 367 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
82677ed2 AK |
368 | if (cpus_offset < 0) { |
369 | return cpus_offset; | |
370 | } | |
371 | } | |
372 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 373 | if (offset < 0) { |
82677ed2 AK |
374 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
375 | if (offset < 0) { | |
376 | return offset; | |
377 | } | |
6e806cc3 BR |
378 | } |
379 | ||
7f763a5d DG |
380 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
381 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
382 | if (ret < 0) { |
383 | return ret; | |
384 | } | |
833d4668 | 385 | |
99861ecb IM |
386 | if (nb_numa_nodes > 1) { |
387 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
388 | if (ret < 0) { | |
389 | return ret; | |
390 | } | |
0da6f3fe BR |
391 | } |
392 | ||
12dbeb16 | 393 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
394 | if (ret < 0) { |
395 | return ret; | |
396 | } | |
e957f6a9 | 397 | |
ee76a09f DG |
398 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
399 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
400 | } |
401 | return ret; | |
402 | } | |
403 | ||
c86c1aff | 404 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a AK |
405 | { |
406 | if (nb_numa_nodes) { | |
407 | int i; | |
408 | for (i = 0; i < nb_numa_nodes; ++i) { | |
409 | if (numa_info[i].node_mem) { | |
fb164994 DG |
410 | return MIN(pow2floor(numa_info[i].node_mem), |
411 | machine->ram_size); | |
b082d65a AK |
412 | } |
413 | } | |
414 | } | |
fb164994 | 415 | return machine->ram_size; |
b082d65a AK |
416 | } |
417 | ||
a1d59c0f AK |
418 | static void add_str(GString *s, const gchar *s1) |
419 | { | |
420 | g_string_append_len(s, s1, strlen(s1) + 1); | |
421 | } | |
7f763a5d | 422 | |
03d196b7 | 423 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
424 | hwaddr size) |
425 | { | |
426 | uint32_t associativity[] = { | |
427 | cpu_to_be32(0x4), /* length */ | |
428 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 429 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
430 | }; |
431 | char mem_name[32]; | |
432 | uint64_t mem_reg_property[2]; | |
433 | int off; | |
434 | ||
435 | mem_reg_property[0] = cpu_to_be64(start); | |
436 | mem_reg_property[1] = cpu_to_be64(size); | |
437 | ||
438 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
439 | off = fdt_add_subnode(fdt, 0, mem_name); | |
440 | _FDT(off); | |
441 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
442 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
443 | sizeof(mem_reg_property)))); | |
444 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
445 | sizeof(associativity)))); | |
03d196b7 | 446 | return off; |
26a8c353 AK |
447 | } |
448 | ||
28e02042 | 449 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 450 | { |
fb164994 | 451 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
452 | hwaddr mem_start, node_size; |
453 | int i, nb_nodes = nb_numa_nodes; | |
454 | NodeInfo *nodes = numa_info; | |
455 | NodeInfo ramnode; | |
456 | ||
457 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
458 | if (!nb_numa_nodes) { | |
459 | nb_nodes = 1; | |
fb164994 | 460 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 461 | nodes = &ramnode; |
5fe269b1 | 462 | } |
7f763a5d | 463 | |
7db8a127 AK |
464 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
465 | if (!nodes[i].node_mem) { | |
466 | continue; | |
467 | } | |
fb164994 | 468 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
469 | node_size = 0; |
470 | } else { | |
7db8a127 | 471 | node_size = nodes[i].node_mem; |
fb164994 DG |
472 | if (node_size > machine->ram_size - mem_start) { |
473 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
474 | } |
475 | } | |
7db8a127 | 476 | if (!mem_start) { |
b472b1a7 DHB |
477 | /* spapr_machine_init() checks for rma_size <= node0_size |
478 | * already */ | |
e8f986fc | 479 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
480 | mem_start += spapr->rma_size; |
481 | node_size -= spapr->rma_size; | |
482 | } | |
6010818c AK |
483 | for ( ; node_size; ) { |
484 | hwaddr sizetmp = pow2floor(node_size); | |
485 | ||
486 | /* mem_start != 0 here */ | |
487 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
488 | sizetmp = 1ULL << ctzl(mem_start); | |
489 | } | |
490 | ||
491 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
492 | node_size -= sizetmp; | |
493 | mem_start += sizetmp; | |
494 | } | |
7f763a5d DG |
495 | } |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
0da6f3fe BR |
500 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
501 | sPAPRMachineState *spapr) | |
502 | { | |
503 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
504 | CPUPPCState *env = &cpu->env; | |
505 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
14bb4486 | 506 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
507 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
508 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
509 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
510 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
511 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
512 | uint32_t page_sizes_prop[64]; | |
513 | size_t page_sizes_prop_size; | |
22419c2a | 514 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 515 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
abbc1247 | 516 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
af81cf32 | 517 | sPAPRDRConnector *drc; |
af81cf32 | 518 | int drc_index; |
c64abd1f SB |
519 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
520 | int i; | |
af81cf32 | 521 | |
fbf55397 | 522 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 523 | if (drc) { |
0b55aa91 | 524 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
525 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
526 | } | |
0da6f3fe BR |
527 | |
528 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
529 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
530 | ||
531 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
532 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
533 | env->dcache_line_size))); | |
534 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
535 | env->dcache_line_size))); | |
536 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
537 | env->icache_line_size))); | |
538 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
539 | env->icache_line_size))); | |
540 | ||
541 | if (pcc->l1_dcache_size) { | |
542 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
543 | pcc->l1_dcache_size))); | |
544 | } else { | |
3dc6f869 | 545 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
546 | } |
547 | if (pcc->l1_icache_size) { | |
548 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
549 | pcc->l1_icache_size))); | |
550 | } else { | |
3dc6f869 | 551 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
552 | } |
553 | ||
554 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
555 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
67d7d66f DG |
556 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); |
557 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); | |
0da6f3fe BR |
558 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); |
559 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
560 | ||
561 | if (env->spr_cb[SPR_PURR].oea_read) { | |
562 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
563 | } | |
564 | ||
58969eee | 565 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
0da6f3fe BR |
566 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", |
567 | segs, sizeof(segs)))); | |
568 | } | |
569 | ||
29386642 | 570 | /* Advertise VSX (vector extensions) if available |
0da6f3fe | 571 | * 1 == VMX / Altivec available |
29386642 DG |
572 | * 2 == VSX available |
573 | * | |
574 | * Only CPUs for which we create core types in spapr_cpu_core.c | |
575 | * are possible, and all of those have VMX */ | |
4e5fe368 | 576 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { |
29386642 DG |
577 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); |
578 | } else { | |
579 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); | |
0da6f3fe BR |
580 | } |
581 | ||
582 | /* Advertise DFP (Decimal Floating Point) if available | |
583 | * 0 / no property == no DFP | |
584 | * 1 == DFP available */ | |
4e5fe368 | 585 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { |
0da6f3fe BR |
586 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); |
587 | } | |
588 | ||
644a2c99 DG |
589 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
590 | sizeof(page_sizes_prop)); | |
0da6f3fe BR |
591 | if (page_sizes_prop_size) { |
592 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
593 | page_sizes_prop, page_sizes_prop_size))); | |
594 | } | |
595 | ||
ee76a09f | 596 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
90da0d5a | 597 | |
0da6f3fe | 598 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 599 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
600 | |
601 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
602 | pft_size_prop, sizeof(pft_size_prop)))); | |
603 | ||
99861ecb IM |
604 | if (nb_numa_nodes > 1) { |
605 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
606 | } | |
0da6f3fe | 607 | |
12dbeb16 | 608 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
609 | |
610 | if (pcc->radix_page_info) { | |
611 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
612 | radix_AP_encodings[i] = | |
613 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
614 | } | |
615 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
616 | radix_AP_encodings, | |
617 | pcc->radix_page_info->count * | |
618 | sizeof(radix_AP_encodings[0])))); | |
619 | } | |
0da6f3fe BR |
620 | } |
621 | ||
622 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
623 | { | |
624 | CPUState *cs; | |
625 | int cpus_offset; | |
626 | char *nodename; | |
0da6f3fe BR |
627 | |
628 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
629 | _FDT(cpus_offset); | |
630 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
631 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
632 | ||
633 | /* | |
634 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
635 | * created by fdt_add_subnode() end up in the right order in FDT | |
636 | * for the guest kernel the enumerate the CPUs correctly. | |
637 | */ | |
638 | CPU_FOREACH_REVERSE(cs) { | |
639 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
14bb4486 | 640 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
641 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
642 | int offset; | |
643 | ||
5d0fb150 | 644 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
0da6f3fe BR |
645 | continue; |
646 | } | |
647 | ||
648 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
649 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
650 | g_free(nodename); | |
651 | _FDT(offset); | |
652 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
653 | } | |
654 | ||
655 | } | |
656 | ||
f47bd1c8 IM |
657 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
658 | { | |
659 | MemoryDeviceInfoList *info; | |
660 | ||
661 | for (info = list; info; info = info->next) { | |
662 | MemoryDeviceInfo *value = info->value; | |
663 | ||
664 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
665 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
666 | ||
667 | if (pcdimm_info->addr >= addr && | |
668 | addr < (pcdimm_info->addr + pcdimm_info->size)) { | |
669 | return pcdimm_info->node; | |
670 | } | |
671 | } | |
672 | } | |
673 | ||
674 | return -1; | |
675 | } | |
676 | ||
a324d6f1 BR |
677 | struct sPAPRDrconfCellV2 { |
678 | uint32_t seq_lmbs; | |
679 | uint64_t base_addr; | |
680 | uint32_t drc_index; | |
681 | uint32_t aa_index; | |
682 | uint32_t flags; | |
683 | } QEMU_PACKED; | |
684 | ||
685 | typedef struct DrconfCellQueue { | |
686 | struct sPAPRDrconfCellV2 cell; | |
687 | QSIMPLEQ_ENTRY(DrconfCellQueue) entry; | |
688 | } DrconfCellQueue; | |
689 | ||
690 | static DrconfCellQueue * | |
691 | spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, | |
692 | uint32_t drc_index, uint32_t aa_index, | |
693 | uint32_t flags) | |
03d196b7 | 694 | { |
a324d6f1 BR |
695 | DrconfCellQueue *elem; |
696 | ||
697 | elem = g_malloc0(sizeof(*elem)); | |
698 | elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); | |
699 | elem->cell.base_addr = cpu_to_be64(base_addr); | |
700 | elem->cell.drc_index = cpu_to_be32(drc_index); | |
701 | elem->cell.aa_index = cpu_to_be32(aa_index); | |
702 | elem->cell.flags = cpu_to_be32(flags); | |
703 | ||
704 | return elem; | |
705 | } | |
706 | ||
707 | /* ibm,dynamic-memory-v2 */ | |
708 | static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, | |
709 | int offset, MemoryDeviceInfoList *dimms) | |
710 | { | |
b0c14ec4 | 711 | MachineState *machine = MACHINE(spapr); |
a324d6f1 BR |
712 | uint8_t *int_buf, *cur_index, buf_len; |
713 | int ret; | |
714 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
715 | uint64_t addr, cur_addr, size; | |
b0c14ec4 DH |
716 | uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); |
717 | uint64_t mem_end = machine->device_memory->base + | |
718 | memory_region_size(&machine->device_memory->mr); | |
a324d6f1 BR |
719 | uint32_t node, nr_entries = 0; |
720 | sPAPRDRConnector *drc; | |
721 | DrconfCellQueue *elem, *next; | |
722 | MemoryDeviceInfoList *info; | |
723 | QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue | |
724 | = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); | |
725 | ||
726 | /* Entry to cover RAM and the gap area */ | |
727 | elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, | |
728 | SPAPR_LMB_FLAGS_RESERVED | | |
729 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
730 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
731 | nr_entries++; | |
732 | ||
b0c14ec4 | 733 | cur_addr = machine->device_memory->base; |
a324d6f1 BR |
734 | for (info = dimms; info; info = info->next) { |
735 | PCDIMMDeviceInfo *di = info->value->u.dimm.data; | |
736 | ||
737 | addr = di->addr; | |
738 | size = di->size; | |
739 | node = di->node; | |
740 | ||
741 | /* Entry for hot-pluggable area */ | |
742 | if (cur_addr < addr) { | |
743 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
744 | g_assert(drc); | |
745 | elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, | |
746 | cur_addr, spapr_drc_index(drc), -1, 0); | |
747 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
748 | nr_entries++; | |
749 | } | |
750 | ||
751 | /* Entry for DIMM */ | |
752 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); | |
753 | g_assert(drc); | |
754 | elem = spapr_get_drconf_cell(size / lmb_size, addr, | |
755 | spapr_drc_index(drc), node, | |
756 | SPAPR_LMB_FLAGS_ASSIGNED); | |
757 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
758 | nr_entries++; | |
759 | cur_addr = addr + size; | |
760 | } | |
761 | ||
762 | /* Entry for remaining hotpluggable area */ | |
763 | if (cur_addr < mem_end) { | |
764 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
765 | g_assert(drc); | |
766 | elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, | |
767 | cur_addr, spapr_drc_index(drc), -1, 0); | |
768 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
769 | nr_entries++; | |
770 | } | |
771 | ||
772 | buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); | |
773 | int_buf = cur_index = g_malloc0(buf_len); | |
774 | *(uint32_t *)int_buf = cpu_to_be32(nr_entries); | |
775 | cur_index += sizeof(nr_entries); | |
776 | ||
777 | QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { | |
778 | memcpy(cur_index, &elem->cell, sizeof(elem->cell)); | |
779 | cur_index += sizeof(elem->cell); | |
780 | QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); | |
781 | g_free(elem); | |
782 | } | |
783 | ||
784 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); | |
785 | g_free(int_buf); | |
786 | if (ret < 0) { | |
787 | return -1; | |
788 | } | |
789 | return 0; | |
790 | } | |
791 | ||
792 | /* ibm,dynamic-memory */ | |
793 | static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, | |
794 | int offset, MemoryDeviceInfoList *dimms) | |
795 | { | |
b0c14ec4 | 796 | MachineState *machine = MACHINE(spapr); |
a324d6f1 | 797 | int i, ret; |
03d196b7 | 798 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
0c9269a5 | 799 | uint32_t device_lmb_start = machine->device_memory->base / lmb_size; |
b0c14ec4 DH |
800 | uint32_t nr_lmbs = (machine->device_memory->base + |
801 | memory_region_size(&machine->device_memory->mr)) / | |
d0e5a8f2 | 802 | lmb_size; |
03d196b7 | 803 | uint32_t *int_buf, *cur_index, buf_len; |
16c25aef | 804 | |
ef001f06 TH |
805 | /* |
806 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
ef001f06 | 807 | */ |
a324d6f1 | 808 | buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); |
03d196b7 | 809 | cur_index = int_buf = g_malloc0(buf_len); |
03d196b7 BR |
810 | int_buf[0] = cpu_to_be32(nr_lmbs); |
811 | cur_index++; | |
812 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 813 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
814 | uint32_t *dynamic_memory = cur_index; |
815 | ||
0c9269a5 | 816 | if (i >= device_lmb_start) { |
d0e5a8f2 | 817 | sPAPRDRConnector *drc; |
d0e5a8f2 | 818 | |
fbf55397 | 819 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 820 | g_assert(drc); |
d0e5a8f2 BR |
821 | |
822 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
823 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 824 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 825 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 826 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
827 | if (memory_region_present(get_system_memory(), addr)) { |
828 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
829 | } else { | |
830 | dynamic_memory[5] = cpu_to_be32(0); | |
831 | } | |
03d196b7 | 832 | } else { |
d0e5a8f2 BR |
833 | /* |
834 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
0c9269a5 | 835 | * device memory region -- all these are marked as reserved |
d0e5a8f2 BR |
836 | * and as having no valid DRC. |
837 | */ | |
838 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
839 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
840 | dynamic_memory[2] = cpu_to_be32(0); | |
841 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
842 | dynamic_memory[4] = cpu_to_be32(-1); | |
843 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
844 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
845 | } |
846 | ||
847 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
848 | } | |
849 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
a324d6f1 | 850 | g_free(int_buf); |
03d196b7 | 851 | if (ret < 0) { |
a324d6f1 BR |
852 | return -1; |
853 | } | |
854 | return 0; | |
855 | } | |
856 | ||
857 | /* | |
858 | * Adds ibm,dynamic-reconfiguration-memory node. | |
859 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
860 | * of this device tree node. | |
861 | */ | |
862 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
863 | { | |
864 | MachineState *machine = MACHINE(spapr); | |
865 | int ret, i, offset; | |
866 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
867 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
868 | uint32_t *int_buf, *cur_index, buf_len; | |
869 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; | |
870 | MemoryDeviceInfoList *dimms = NULL; | |
871 | ||
872 | /* | |
0c9269a5 | 873 | * Don't create the node if there is no device memory |
a324d6f1 BR |
874 | */ |
875 | if (machine->ram_size == machine->maxram_size) { | |
876 | return 0; | |
877 | } | |
878 | ||
879 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
880 | ||
881 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
882 | sizeof(prop_lmb_size)); | |
883 | if (ret < 0) { | |
884 | return ret; | |
885 | } | |
886 | ||
887 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
888 | if (ret < 0) { | |
889 | return ret; | |
890 | } | |
891 | ||
892 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
893 | if (ret < 0) { | |
894 | return ret; | |
895 | } | |
896 | ||
897 | /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ | |
2cc0e2e8 | 898 | dimms = qmp_memory_device_list(); |
a324d6f1 BR |
899 | if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { |
900 | ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); | |
901 | } else { | |
902 | ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); | |
903 | } | |
904 | qapi_free_MemoryDeviceInfoList(dimms); | |
905 | ||
906 | if (ret < 0) { | |
907 | return ret; | |
03d196b7 BR |
908 | } |
909 | ||
910 | /* ibm,associativity-lookup-arrays */ | |
a324d6f1 BR |
911 | buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); |
912 | cur_index = int_buf = g_malloc0(buf_len); | |
913 | ||
03d196b7 | 914 | cur_index = int_buf; |
6663864e | 915 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
916 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
917 | cur_index += 2; | |
6663864e | 918 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
919 | uint32_t associativity[] = { |
920 | cpu_to_be32(0x0), | |
921 | cpu_to_be32(0x0), | |
922 | cpu_to_be32(0x0), | |
923 | cpu_to_be32(i) | |
924 | }; | |
925 | memcpy(cur_index, associativity, sizeof(associativity)); | |
926 | cur_index += 4; | |
927 | } | |
928 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
929 | (cur_index - int_buf) * sizeof(uint32_t)); | |
03d196b7 | 930 | g_free(int_buf); |
a324d6f1 | 931 | |
03d196b7 BR |
932 | return ret; |
933 | } | |
934 | ||
6787d27b MR |
935 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
936 | sPAPROptionVector *ov5_updates) | |
937 | { | |
938 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 939 | int ret = 0, offset; |
6787d27b MR |
940 | |
941 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
942 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
943 | g_assert(smc->dr_lmb_enabled); | |
944 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
945 | if (ret) { |
946 | goto out; | |
947 | } | |
6787d27b MR |
948 | } |
949 | ||
417ece33 MR |
950 | offset = fdt_path_offset(fdt, "/chosen"); |
951 | if (offset < 0) { | |
952 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
953 | if (offset < 0) { | |
954 | return offset; | |
955 | } | |
956 | } | |
957 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
958 | "ibm,architecture-vec-5"); | |
959 | ||
960 | out: | |
6787d27b MR |
961 | return ret; |
962 | } | |
963 | ||
10f12e64 DHB |
964 | static bool spapr_hotplugged_dev_before_cas(void) |
965 | { | |
966 | Object *drc_container, *obj; | |
967 | ObjectProperty *prop; | |
968 | ObjectPropertyIterator iter; | |
969 | ||
970 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
971 | object_property_iter_init(&iter, drc_container); | |
972 | while ((prop = object_property_iter_next(&iter))) { | |
973 | if (!strstart(prop->type, "link<", NULL)) { | |
974 | continue; | |
975 | } | |
976 | obj = object_property_get_link(drc_container, prop->name, NULL); | |
977 | if (spapr_drc_needed(obj)) { | |
978 | return true; | |
979 | } | |
980 | } | |
981 | return false; | |
982 | } | |
983 | ||
03d196b7 BR |
984 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
985 | target_ulong addr, target_ulong size, | |
6787d27b | 986 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
987 | { |
988 | void *fdt, *fdt_skel; | |
989 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 | 990 | |
10f12e64 DHB |
991 | if (spapr_hotplugged_dev_before_cas()) { |
992 | return 1; | |
993 | } | |
994 | ||
827b17c4 GK |
995 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
996 | error_report("SLOF provided an unexpected CAS buffer size " | |
997 | TARGET_FMT_lu " (min: %zu, max: %u)", | |
998 | size, sizeof(hdr), FW_MAX_SIZE); | |
999 | exit(EXIT_FAILURE); | |
1000 | } | |
1001 | ||
03d196b7 BR |
1002 | size -= sizeof(hdr); |
1003 | ||
10f12e64 | 1004 | /* Create skeleton */ |
03d196b7 BR |
1005 | fdt_skel = g_malloc0(size); |
1006 | _FDT((fdt_create(fdt_skel, size))); | |
127f03e4 | 1007 | _FDT((fdt_finish_reservemap(fdt_skel))); |
03d196b7 BR |
1008 | _FDT((fdt_begin_node(fdt_skel, ""))); |
1009 | _FDT((fdt_end_node(fdt_skel))); | |
1010 | _FDT((fdt_finish(fdt_skel))); | |
1011 | fdt = g_malloc0(size); | |
1012 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
1013 | g_free(fdt_skel); | |
1014 | ||
1015 | /* Fixup cpu nodes */ | |
5b120785 | 1016 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 1017 | |
6787d27b MR |
1018 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
1019 | return -1; | |
03d196b7 BR |
1020 | } |
1021 | ||
1022 | /* Pack resulting tree */ | |
1023 | _FDT((fdt_pack(fdt))); | |
1024 | ||
1025 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
1026 | trace_spapr_cas_failed(size); | |
1027 | return -1; | |
1028 | } | |
1029 | ||
1030 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
1031 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
1032 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
1033 | g_free(fdt); | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
3f5dabce DG |
1038 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
1039 | { | |
1040 | int rtas; | |
1041 | GString *hypertas = g_string_sized_new(256); | |
1042 | GString *qemu_hypertas = g_string_sized_new(256); | |
1043 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
0c9269a5 | 1044 | uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + |
b0c14ec4 | 1045 | memory_region_size(&MACHINE(spapr)->device_memory->mr); |
3f5dabce | 1046 | uint32_t lrdr_capacity[] = { |
0c9269a5 DH |
1047 | cpu_to_be32(max_device_addr >> 32), |
1048 | cpu_to_be32(max_device_addr & 0xffffffff), | |
3f5dabce DG |
1049 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), |
1050 | cpu_to_be32(max_cpus / smp_threads), | |
1051 | }; | |
da9f80fb SP |
1052 | uint32_t maxdomains[] = { |
1053 | cpu_to_be32(4), | |
1054 | cpu_to_be32(0), | |
1055 | cpu_to_be32(0), | |
1056 | cpu_to_be32(0), | |
1057 | cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), | |
1058 | }; | |
3f5dabce DG |
1059 | |
1060 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
1061 | ||
1062 | /* hypertas */ | |
1063 | add_str(hypertas, "hcall-pft"); | |
1064 | add_str(hypertas, "hcall-term"); | |
1065 | add_str(hypertas, "hcall-dabr"); | |
1066 | add_str(hypertas, "hcall-interrupt"); | |
1067 | add_str(hypertas, "hcall-tce"); | |
1068 | add_str(hypertas, "hcall-vio"); | |
1069 | add_str(hypertas, "hcall-splpar"); | |
1070 | add_str(hypertas, "hcall-bulk"); | |
1071 | add_str(hypertas, "hcall-set-mode"); | |
1072 | add_str(hypertas, "hcall-sprg0"); | |
1073 | add_str(hypertas, "hcall-copy"); | |
1074 | add_str(hypertas, "hcall-debug"); | |
1075 | add_str(qemu_hypertas, "hcall-memop1"); | |
1076 | ||
1077 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
1078 | add_str(hypertas, "hcall-multi-tce"); | |
1079 | } | |
30f4b05b DG |
1080 | |
1081 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
1082 | add_str(hypertas, "hcall-hpt-resize"); | |
1083 | } | |
1084 | ||
3f5dabce DG |
1085 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
1086 | hypertas->str, hypertas->len)); | |
1087 | g_string_free(hypertas, TRUE); | |
1088 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
1089 | qemu_hypertas->str, qemu_hypertas->len)); | |
1090 | g_string_free(qemu_hypertas, TRUE); | |
1091 | ||
1092 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
1093 | refpoints, sizeof(refpoints))); | |
1094 | ||
da9f80fb SP |
1095 | _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", |
1096 | maxdomains, sizeof(maxdomains))); | |
1097 | ||
3f5dabce DG |
1098 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", |
1099 | RTAS_ERROR_LOG_MAX)); | |
1100 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
1101 | RTAS_EVENT_SCAN_RATE)); | |
1102 | ||
4f441474 DG |
1103 | g_assert(msi_nonbroken); |
1104 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
1105 | |
1106 | /* | |
1107 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
1108 | * back to the guest cpu. | |
1109 | * | |
1110 | * While an additional ibm,extended-os-term property indicates | |
1111 | * that rtas call return will always occur. Set this property. | |
1112 | */ | |
1113 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
1114 | ||
1115 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
1116 | lrdr_capacity, sizeof(lrdr_capacity))); | |
1117 | ||
1118 | spapr_dt_rtas_tokens(fdt, rtas); | |
1119 | } | |
1120 | ||
9fb4541f SB |
1121 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
1122 | * that the guest may request and thus the valid values for bytes 24..26 of | |
1123 | * option vector 5: */ | |
1124 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
1125 | { | |
545d6e2b SJS |
1126 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
1127 | ||
f2b14e3a | 1128 | char val[2 * 4] = { |
21f3f8db | 1129 | 23, 0x00, /* Xive mode, filled in below. */ |
9fb4541f SB |
1130 | 24, 0x00, /* Hash/Radix, filled in below. */ |
1131 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
1132 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
1133 | }; | |
1134 | ||
7abd43ba SJS |
1135 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
1136 | first_ppc_cpu->compat_pvr)) { | |
1137 | /* If we're in a pre POWER9 compat mode then the guest should do hash */ | |
1138 | val[3] = 0x00; /* Hash */ | |
1139 | } else if (kvm_enabled()) { | |
9fb4541f | 1140 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 1141 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 1142 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 1143 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 1144 | } else { |
f2b14e3a | 1145 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
1146 | } |
1147 | } else { | |
7abd43ba SJS |
1148 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
1149 | val[3] = 0xC0; | |
9fb4541f SB |
1150 | } |
1151 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
1152 | val, sizeof(val))); | |
1153 | } | |
1154 | ||
7c866c6a DG |
1155 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
1156 | { | |
1157 | MachineState *machine = MACHINE(spapr); | |
1158 | int chosen; | |
1159 | const char *boot_device = machine->boot_order; | |
1160 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1161 | size_t cb = 0; | |
1162 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
1163 | |
1164 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1165 | ||
7c866c6a DG |
1166 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
1167 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1168 | spapr->initrd_base)); | |
1169 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1170 | spapr->initrd_base + spapr->initrd_size)); | |
1171 | ||
1172 | if (spapr->kernel_size) { | |
1173 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
1174 | cpu_to_be64(spapr->kernel_size) }; | |
1175 | ||
1176 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
1177 | &kprop, sizeof(kprop))); | |
1178 | if (spapr->kernel_le) { | |
1179 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1180 | } | |
1181 | } | |
1182 | if (boot_menu) { | |
1183 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1184 | } | |
1185 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1186 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1187 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
1188 | ||
1189 | if (cb && bootlist) { | |
1190 | int i; | |
1191 | ||
1192 | for (i = 0; i < cb; i++) { | |
1193 | if (bootlist[i] == '\n') { | |
1194 | bootlist[i] = ' '; | |
1195 | } | |
1196 | } | |
1197 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
1198 | } | |
1199 | ||
1200 | if (boot_device && strlen(boot_device)) { | |
1201 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1202 | } | |
1203 | ||
1204 | if (!spapr->has_graphics && stdout_path) { | |
90ee4e01 ND |
1205 | /* |
1206 | * "linux,stdout-path" and "stdout" properties are deprecated by linux | |
1207 | * kernel. New platforms should only use the "stdout-path" property. Set | |
1208 | * the new property and continue using older property to remain | |
1209 | * compatible with the existing firmware. | |
1210 | */ | |
7c866c6a | 1211 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); |
90ee4e01 | 1212 | _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); |
7c866c6a DG |
1213 | } |
1214 | ||
9fb4541f SB |
1215 | spapr_dt_ov5_platform_support(fdt, chosen); |
1216 | ||
7c866c6a DG |
1217 | g_free(stdout_path); |
1218 | g_free(bootlist); | |
1219 | } | |
1220 | ||
fca5f2dc DG |
1221 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1222 | { | |
1223 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1224 | * KVM to work under pHyp with some guest co-operation */ | |
1225 | int hypervisor; | |
1226 | uint8_t hypercall[16]; | |
1227 | ||
1228 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1229 | /* indicate KVM hypercall interface */ | |
1230 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1231 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1232 | /* | |
1233 | * Older KVM versions with older guest kernels were broken | |
1234 | * with the magic page, don't allow the guest to map it. | |
1235 | */ | |
1236 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1237 | sizeof(hypercall))) { | |
1238 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1239 | hypercall, sizeof(hypercall))); | |
1240 | } | |
1241 | } | |
1242 | } | |
1243 | ||
997b6cfc DG |
1244 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1245 | hwaddr rtas_addr, | |
1246 | hwaddr rtas_size) | |
a3467baa | 1247 | { |
c86c1aff | 1248 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1249 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1250 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1251 | int ret; |
a3467baa | 1252 | void *fdt; |
3384f95c | 1253 | sPAPRPHBState *phb; |
398a0bd5 | 1254 | char *buf; |
a3467baa | 1255 | |
398a0bd5 DG |
1256 | fdt = g_malloc0(FDT_MAX_SIZE); |
1257 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1258 | |
398a0bd5 DG |
1259 | /* Root node */ |
1260 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1261 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1262 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1263 | ||
1264 | /* | |
1265 | * Add info to guest to indentify which host is it being run on | |
1266 | * and what is the uuid of the guest | |
1267 | */ | |
1268 | if (kvmppc_get_host_model(&buf)) { | |
1269 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1270 | g_free(buf); | |
1271 | } | |
1272 | if (kvmppc_get_host_serial(&buf)) { | |
1273 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1274 | g_free(buf); | |
1275 | } | |
1276 | ||
1277 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1278 | ||
1279 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1280 | if (qemu_uuid_set) { | |
1281 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1282 | } | |
1283 | g_free(buf); | |
1284 | ||
1285 | if (qemu_get_vm_name()) { | |
1286 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1287 | qemu_get_vm_name())); | |
1288 | } | |
1289 | ||
1290 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1291 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1292 | |
fc7e0765 | 1293 | /* /interrupt controller */ |
72194664 | 1294 | spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); |
fc7e0765 | 1295 | |
e8f986fc BR |
1296 | ret = spapr_populate_memory(spapr, fdt); |
1297 | if (ret < 0) { | |
ce9863b7 | 1298 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1299 | exit(1); |
7f763a5d DG |
1300 | } |
1301 | ||
bf5a6696 DG |
1302 | /* /vdevice */ |
1303 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1304 | |
4d9392be TH |
1305 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1306 | ret = spapr_rng_populate_dt(fdt); | |
1307 | if (ret < 0) { | |
ce9863b7 | 1308 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1309 | exit(1); |
1310 | } | |
1311 | } | |
1312 | ||
3384f95c | 1313 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1314 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1315 | if (ret < 0) { |
1316 | error_report("couldn't setup PCI devices in fdt"); | |
1317 | exit(1); | |
1318 | } | |
3384f95c DG |
1319 | } |
1320 | ||
0da6f3fe BR |
1321 | /* cpus */ |
1322 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1323 | |
c20d332a BR |
1324 | if (smc->dr_lmb_enabled) { |
1325 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1326 | } | |
1327 | ||
c5514d0e | 1328 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1329 | int offset = fdt_path_offset(fdt, "/cpus"); |
1330 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1331 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1332 | if (ret < 0) { | |
1333 | error_report("Couldn't set up CPU DR device tree properties"); | |
1334 | exit(1); | |
1335 | } | |
1336 | } | |
1337 | ||
ffb1e275 | 1338 | /* /event-sources */ |
ffbb1705 | 1339 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1340 | |
3f5dabce DG |
1341 | /* /rtas */ |
1342 | spapr_dt_rtas(spapr, fdt); | |
1343 | ||
7c866c6a DG |
1344 | /* /chosen */ |
1345 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1346 | |
fca5f2dc DG |
1347 | /* /hypervisor */ |
1348 | if (kvm_enabled()) { | |
1349 | spapr_dt_hypervisor(spapr, fdt); | |
1350 | } | |
1351 | ||
cf6e5223 DG |
1352 | /* Build memory reserve map */ |
1353 | if (spapr->kernel_size) { | |
1354 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1355 | } | |
1356 | if (spapr->initrd_size) { | |
1357 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1358 | } | |
1359 | ||
6787d27b MR |
1360 | /* ibm,client-architecture-support updates */ |
1361 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1362 | if (ret < 0) { | |
1363 | error_report("couldn't setup CAS properties fdt"); | |
1364 | exit(1); | |
1365 | } | |
1366 | ||
997b6cfc | 1367 | return fdt; |
9fdf0c29 DG |
1368 | } |
1369 | ||
1370 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1371 | { | |
1372 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1373 | } | |
1374 | ||
1d1be34d DG |
1375 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1376 | PowerPCCPU *cpu) | |
9fdf0c29 | 1377 | { |
1b14670a AF |
1378 | CPUPPCState *env = &cpu->env; |
1379 | ||
8d04fb55 JK |
1380 | /* The TCG path should also be holding the BQL at this point */ |
1381 | g_assert(qemu_mutex_iothread_locked()); | |
1382 | ||
efcb9383 DG |
1383 | if (msr_pr) { |
1384 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1385 | env->gpr[3] = H_PRIVILEGE; | |
1386 | } else { | |
aa100fa4 | 1387 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1388 | } |
9fdf0c29 DG |
1389 | } |
1390 | ||
9861bb3e SJS |
1391 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1392 | { | |
1393 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1394 | ||
1395 | return spapr->patb_entry; | |
1396 | } | |
1397 | ||
e6b8fd24 SMJ |
1398 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1399 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1400 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1401 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1402 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1403 | ||
715c5407 DG |
1404 | /* |
1405 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1406 | */ | |
1407 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1408 | { | |
14b0d748 GK |
1409 | Error *local_err = NULL; |
1410 | ||
715c5407 DG |
1411 | if (spapr->htab_fd >= 0) { |
1412 | return spapr->htab_fd; | |
1413 | } | |
1414 | ||
14b0d748 | 1415 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1416 | if (spapr->htab_fd < 0) { |
14b0d748 | 1417 | error_report_err(local_err); |
715c5407 DG |
1418 | } |
1419 | ||
1420 | return spapr->htab_fd; | |
1421 | } | |
1422 | ||
b4db5413 | 1423 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1424 | { |
1425 | if (spapr->htab_fd >= 0) { | |
1426 | close(spapr->htab_fd); | |
1427 | } | |
1428 | spapr->htab_fd = -1; | |
1429 | } | |
1430 | ||
e57ca75c DG |
1431 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1432 | { | |
1433 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1434 | ||
1435 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1436 | } | |
1437 | ||
1ec26c75 GK |
1438 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1439 | { | |
1440 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1441 | ||
1442 | assert(kvm_enabled()); | |
1443 | ||
1444 | if (!spapr->htab) { | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1449 | } | |
1450 | ||
e57ca75c DG |
1451 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1452 | hwaddr ptex, int n) | |
1453 | { | |
1454 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1455 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1456 | ||
1457 | if (!spapr->htab) { | |
1458 | /* | |
1459 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1460 | */ | |
1461 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1462 | kvmppc_read_hptes(hptes, ptex, n); | |
1463 | return hptes; | |
1464 | } | |
1465 | ||
1466 | /* | |
1467 | * HTAB is controlled by QEMU. Just point to the internally | |
1468 | * accessible PTEG. | |
1469 | */ | |
1470 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1471 | } | |
1472 | ||
1473 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1474 | const ppc_hash_pte64_t *hptes, | |
1475 | hwaddr ptex, int n) | |
1476 | { | |
1477 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1478 | ||
1479 | if (!spapr->htab) { | |
1480 | g_free((void *)hptes); | |
1481 | } | |
1482 | ||
1483 | /* Nothing to do for qemu managed HPT */ | |
1484 | } | |
1485 | ||
1486 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1487 | uint64_t pte0, uint64_t pte1) | |
1488 | { | |
1489 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1490 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1491 | ||
1492 | if (!spapr->htab) { | |
1493 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1494 | } else { | |
1495 | stq_p(spapr->htab + offset, pte0); | |
1496 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1497 | } | |
1498 | } | |
1499 | ||
0b0b8310 | 1500 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1501 | { |
1502 | int shift; | |
1503 | ||
1504 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1505 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1506 | * that's much more than is needed for Linux guests */ | |
1507 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1508 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1509 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1510 | return shift; | |
1511 | } | |
1512 | ||
06ec79e8 BR |
1513 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1514 | { | |
1515 | g_free(spapr->htab); | |
1516 | spapr->htab = NULL; | |
1517 | spapr->htab_shift = 0; | |
1518 | close_htab_fd(spapr); | |
1519 | } | |
1520 | ||
2772cf6b DG |
1521 | void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1522 | Error **errp) | |
7f763a5d | 1523 | { |
c5f54f3e DG |
1524 | long rc; |
1525 | ||
1526 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1527 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1528 | |
1529 | rc = kvmppc_reset_htab(shift); | |
1530 | if (rc < 0) { | |
1531 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1532 | error_setg_errno(errp, errno, | |
1533 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1534 | shift); | |
1535 | /* This is almost certainly fatal, but if the caller really | |
1536 | * wants to carry on with shift == 0, it's welcome to try */ | |
1537 | } else if (rc > 0) { | |
1538 | /* kernel-side HPT allocated */ | |
1539 | if (rc != shift) { | |
1540 | error_setg(errp, | |
1541 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1542 | shift, rc); | |
7735feda BR |
1543 | } |
1544 | ||
7f763a5d | 1545 | spapr->htab_shift = shift; |
c18ad9a5 | 1546 | spapr->htab = NULL; |
b817772a | 1547 | } else { |
c5f54f3e DG |
1548 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1549 | size_t size = 1ULL << shift; | |
1550 | int i; | |
b817772a | 1551 | |
c5f54f3e DG |
1552 | spapr->htab = qemu_memalign(size, size); |
1553 | if (!spapr->htab) { | |
1554 | error_setg_errno(errp, errno, | |
1555 | "Could not allocate HPT of order %d", shift); | |
1556 | return; | |
7735feda BR |
1557 | } |
1558 | ||
c5f54f3e DG |
1559 | memset(spapr->htab, 0, size); |
1560 | spapr->htab_shift = shift; | |
e6b8fd24 | 1561 | |
c5f54f3e DG |
1562 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1563 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1564 | } |
7f763a5d | 1565 | } |
ee4d9ecc SJS |
1566 | /* We're setting up a hash table, so that means we're not radix */ |
1567 | spapr->patb_entry = 0; | |
9fdf0c29 DG |
1568 | } |
1569 | ||
b4db5413 SJS |
1570 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1571 | { | |
2772cf6b DG |
1572 | int hpt_shift; |
1573 | ||
1574 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) | |
1575 | || (spapr->cas_reboot | |
1576 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { | |
1577 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1578 | } else { | |
768a20f3 DG |
1579 | uint64_t current_ram_size; |
1580 | ||
1581 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1582 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1583 | } |
1584 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1585 | ||
b4db5413 | 1586 | if (spapr->vrma_adjust) { |
c86c1aff | 1587 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
b4db5413 SJS |
1588 | spapr->htab_shift); |
1589 | } | |
b4db5413 SJS |
1590 | } |
1591 | ||
82512483 GK |
1592 | static int spapr_reset_drcs(Object *child, void *opaque) |
1593 | { | |
1594 | sPAPRDRConnector *drc = | |
1595 | (sPAPRDRConnector *) object_dynamic_cast(child, | |
1596 | TYPE_SPAPR_DR_CONNECTOR); | |
1597 | ||
1598 | if (drc) { | |
1599 | spapr_drc_reset(drc); | |
1600 | } | |
1601 | ||
1602 | return 0; | |
1603 | } | |
1604 | ||
bcb5ce08 | 1605 | static void spapr_machine_reset(void) |
a3467baa | 1606 | { |
c5f54f3e DG |
1607 | MachineState *machine = MACHINE(qdev_get_machine()); |
1608 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1609 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1610 | uint32_t rtas_limit; |
cae172ab | 1611 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1612 | void *fdt; |
1613 | int rc; | |
259186a7 | 1614 | |
9f6edd06 | 1615 | spapr_caps_apply(spapr); |
33face6b | 1616 | |
1481fe5f LV |
1617 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1618 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
ad99d04c DG |
1619 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
1620 | spapr->max_compat_pvr)) { | |
b4db5413 SJS |
1621 | /* If using KVM with radix mode available, VCPUs can be started |
1622 | * without a HPT because KVM will start them in radix mode. | |
1623 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1624 | spapr->patb_entry = PATBE1_GR; | |
1625 | } else { | |
b4db5413 | 1626 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1627 | } |
a3467baa | 1628 | |
9012a53f GK |
1629 | /* if this reset wasn't generated by CAS, we should reset our |
1630 | * negotiated options and start from scratch */ | |
1631 | if (!spapr->cas_reboot) { | |
1632 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1633 | spapr->ov5_cas = spapr_ovec_new(); | |
1634 | ||
1635 | ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); | |
1636 | } | |
1637 | ||
c8787ad4 | 1638 | qemu_devices_reset(); |
82512483 GK |
1639 | |
1640 | /* DRC reset may cause a device to be unplugged. This will cause troubles | |
1641 | * if this device is used by another device (eg, a running vhost backend | |
1642 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1643 | * situations, we reset DRCs after all devices have been reset. | |
1644 | */ | |
1645 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1646 | ||
56258174 | 1647 | spapr_clear_pending_events(spapr); |
a3467baa | 1648 | |
b7d1f77a BH |
1649 | /* |
1650 | * We place the device tree and RTAS just below either the top of the RMA, | |
1651 | * or just below 2GB, whichever is lowere, so that it can be | |
1652 | * processed with 32-bit real mode code if necessary | |
1653 | */ | |
1654 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1655 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1656 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1657 | |
cae172ab | 1658 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1659 | |
2cac78c1 | 1660 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1661 | |
997b6cfc DG |
1662 | rc = fdt_pack(fdt); |
1663 | ||
1664 | /* Should only fail if we've built a corrupted tree */ | |
1665 | assert(rc == 0); | |
1666 | ||
1667 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1668 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1669 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1670 | exit(1); | |
1671 | } | |
1672 | ||
1673 | /* Load the fdt */ | |
1674 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1675 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1676 | g_free(fdt); |
1677 | ||
a3467baa | 1678 | /* Set up the entry state */ |
84369f63 | 1679 | spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); |
182735ef | 1680 | first_ppc_cpu->env.gpr[5] = 0; |
a3467baa | 1681 | |
6787d27b | 1682 | spapr->cas_reboot = false; |
a3467baa DG |
1683 | } |
1684 | ||
28e02042 | 1685 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1686 | { |
2ff3de68 | 1687 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1688 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1689 | |
3978b863 | 1690 | if (dinfo) { |
6231a6da MA |
1691 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1692 | &error_fatal); | |
639e8102 DG |
1693 | } |
1694 | ||
1695 | qdev_init_nofail(dev); | |
1696 | ||
1697 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1698 | } | |
1699 | ||
28e02042 | 1700 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1701 | { |
147ff807 CLG |
1702 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1703 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1704 | &error_fatal); | |
1705 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1706 | &error_fatal); | |
1707 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1708 | "date", &error_fatal); | |
28df36a1 DG |
1709 | } |
1710 | ||
8c57b867 | 1711 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1712 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1713 | { |
8c57b867 | 1714 | switch (vga_interface_type) { |
8c57b867 | 1715 | case VGA_NONE: |
7effdaa3 MW |
1716 | return false; |
1717 | case VGA_DEVICE: | |
1718 | return true; | |
1ddcae82 | 1719 | case VGA_STD: |
b798c190 | 1720 | case VGA_VIRTIO: |
1ddcae82 | 1721 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1722 | default: |
14c6a894 DG |
1723 | error_setg(errp, |
1724 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1725 | return false; | |
f28359d8 | 1726 | } |
f28359d8 LZ |
1727 | } |
1728 | ||
4e5fe368 SJS |
1729 | static int spapr_pre_load(void *opaque) |
1730 | { | |
1731 | int rc; | |
1732 | ||
1733 | rc = spapr_caps_pre_load(opaque); | |
1734 | if (rc) { | |
1735 | return rc; | |
1736 | } | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | ||
880ae7de DG |
1741 | static int spapr_post_load(void *opaque, int version_id) |
1742 | { | |
28e02042 | 1743 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1744 | int err = 0; |
1745 | ||
be85537d DG |
1746 | err = spapr_caps_post_migration(spapr); |
1747 | if (err) { | |
1748 | return err; | |
1749 | } | |
1750 | ||
a7ff1212 | 1751 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1752 | CPUState *cs; |
1753 | CPU_FOREACH(cs) { | |
1754 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1755 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1756 | } |
1757 | } | |
1758 | ||
631b22ea | 1759 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1760 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1761 | * So when migrating from those versions, poke the incoming offset | |
1762 | * value into the RTC device */ | |
1763 | if (version_id < 3) { | |
147ff807 | 1764 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1765 | } |
1766 | ||
0c86b2df | 1767 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 BR |
1768 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1769 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1770 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1771 | ||
1772 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1773 | if (err) { | |
1774 | error_report("Process table config unsupported by the host"); | |
1775 | return -EINVAL; | |
1776 | } | |
1777 | } | |
1778 | ||
880ae7de DG |
1779 | return err; |
1780 | } | |
1781 | ||
4e5fe368 SJS |
1782 | static int spapr_pre_save(void *opaque) |
1783 | { | |
1784 | int rc; | |
1785 | ||
1786 | rc = spapr_caps_pre_save(opaque); | |
1787 | if (rc) { | |
1788 | return rc; | |
1789 | } | |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
880ae7de DG |
1794 | static bool version_before_3(void *opaque, int version_id) |
1795 | { | |
1796 | return version_id < 3; | |
1797 | } | |
1798 | ||
fd38804b DHB |
1799 | static bool spapr_pending_events_needed(void *opaque) |
1800 | { | |
1801 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1802 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1803 | } | |
1804 | ||
1805 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1806 | .name = "spapr_event_log_entry", | |
1807 | .version_id = 1, | |
1808 | .minimum_version_id = 1, | |
1809 | .fields = (VMStateField[]) { | |
5341258e DG |
1810 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1811 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1812 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1813 | NULL, extended_length), |
fd38804b DHB |
1814 | VMSTATE_END_OF_LIST() |
1815 | }, | |
1816 | }; | |
1817 | ||
1818 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1819 | .name = "spapr_pending_events", | |
1820 | .version_id = 1, | |
1821 | .minimum_version_id = 1, | |
1822 | .needed = spapr_pending_events_needed, | |
1823 | .fields = (VMStateField[]) { | |
1824 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1825 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1826 | VMSTATE_END_OF_LIST() | |
1827 | }, | |
1828 | }; | |
1829 | ||
62ef3760 MR |
1830 | static bool spapr_ov5_cas_needed(void *opaque) |
1831 | { | |
1832 | sPAPRMachineState *spapr = opaque; | |
1833 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1834 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1835 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1836 | bool cas_needed; | |
1837 | ||
1838 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1839 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1840 | * Both of these options encode machine topology into the device-tree | |
1841 | * in such a way that the now-booted OS should still be able to interact | |
1842 | * appropriately with QEMU regardless of what options were actually | |
1843 | * negotiatied on the source side. | |
1844 | * | |
1845 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1846 | * are the only options available on the current machine/platform. | |
1847 | * Since these are the only options available for pseries-2.7 and | |
1848 | * earlier, this allows us to maintain old->new/new->old migration | |
1849 | * compatibility. | |
1850 | * | |
1851 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1852 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1853 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1854 | * of the actual CAS-negotiated values to continue working properly. For | |
1855 | * example, availability of memory unplug depends on knowing whether | |
1856 | * OV5_HP_EVT was negotiated via CAS. | |
1857 | * | |
1858 | * Thus, for any cases where the set of available CAS-negotiatable | |
1859 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
aef19c04 GK |
1860 | * include the CAS-negotiated options in the migration stream, unless |
1861 | * if they affect boot time behaviour only. | |
62ef3760 MR |
1862 | */ |
1863 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1864 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
aef19c04 | 1865 | spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); |
62ef3760 MR |
1866 | |
1867 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1868 | * the mask itself since in the future it's possible "legacy" bits may be | |
1869 | * removed via machine options, which could generate a false positive | |
1870 | * that breaks migration. | |
1871 | */ | |
1872 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1873 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1874 | ||
1875 | spapr_ovec_cleanup(ov5_mask); | |
1876 | spapr_ovec_cleanup(ov5_legacy); | |
1877 | spapr_ovec_cleanup(ov5_removed); | |
1878 | ||
1879 | return cas_needed; | |
1880 | } | |
1881 | ||
1882 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1883 | .name = "spapr_option_vector_ov5_cas", | |
1884 | .version_id = 1, | |
1885 | .minimum_version_id = 1, | |
1886 | .needed = spapr_ov5_cas_needed, | |
1887 | .fields = (VMStateField[]) { | |
1888 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1889 | vmstate_spapr_ovec, sPAPROptionVector), | |
1890 | VMSTATE_END_OF_LIST() | |
1891 | }, | |
1892 | }; | |
1893 | ||
9861bb3e SJS |
1894 | static bool spapr_patb_entry_needed(void *opaque) |
1895 | { | |
1896 | sPAPRMachineState *spapr = opaque; | |
1897 | ||
1898 | return !!spapr->patb_entry; | |
1899 | } | |
1900 | ||
1901 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1902 | .name = "spapr_patb_entry", | |
1903 | .version_id = 1, | |
1904 | .minimum_version_id = 1, | |
1905 | .needed = spapr_patb_entry_needed, | |
1906 | .fields = (VMStateField[]) { | |
1907 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1908 | VMSTATE_END_OF_LIST() | |
1909 | }, | |
1910 | }; | |
1911 | ||
4be21d56 DG |
1912 | static const VMStateDescription vmstate_spapr = { |
1913 | .name = "spapr", | |
880ae7de | 1914 | .version_id = 3, |
4be21d56 | 1915 | .minimum_version_id = 1, |
4e5fe368 | 1916 | .pre_load = spapr_pre_load, |
880ae7de | 1917 | .post_load = spapr_post_load, |
4e5fe368 | 1918 | .pre_save = spapr_pre_save, |
3aff6c2f | 1919 | .fields = (VMStateField[]) { |
880ae7de DG |
1920 | /* used to be @next_irq */ |
1921 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1922 | |
1923 | /* RTC offset */ | |
28e02042 | 1924 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1925 | |
28e02042 | 1926 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1927 | VMSTATE_END_OF_LIST() |
1928 | }, | |
62ef3760 MR |
1929 | .subsections = (const VMStateDescription*[]) { |
1930 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1931 | &vmstate_spapr_patb_entry, |
fd38804b | 1932 | &vmstate_spapr_pending_events, |
4e5fe368 SJS |
1933 | &vmstate_spapr_cap_htm, |
1934 | &vmstate_spapr_cap_vsx, | |
1935 | &vmstate_spapr_cap_dfp, | |
8f38eaf8 | 1936 | &vmstate_spapr_cap_cfpc, |
09114fd8 | 1937 | &vmstate_spapr_cap_sbbc, |
4be8d4e7 | 1938 | &vmstate_spapr_cap_ibs, |
62ef3760 MR |
1939 | NULL |
1940 | } | |
4be21d56 DG |
1941 | }; |
1942 | ||
4be21d56 DG |
1943 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1944 | { | |
28e02042 | 1945 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1946 | |
4be21d56 | 1947 | /* "Iteration" header */ |
3a384297 BR |
1948 | if (!spapr->htab_shift) { |
1949 | qemu_put_be32(f, -1); | |
1950 | } else { | |
1951 | qemu_put_be32(f, spapr->htab_shift); | |
1952 | } | |
4be21d56 | 1953 | |
e68cb8b4 AK |
1954 | if (spapr->htab) { |
1955 | spapr->htab_save_index = 0; | |
1956 | spapr->htab_first_pass = true; | |
1957 | } else { | |
3a384297 BR |
1958 | if (spapr->htab_shift) { |
1959 | assert(kvm_enabled()); | |
1960 | } | |
e68cb8b4 AK |
1961 | } |
1962 | ||
1963 | ||
4be21d56 DG |
1964 | return 0; |
1965 | } | |
1966 | ||
332f7721 GK |
1967 | static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, |
1968 | int chunkstart, int n_valid, int n_invalid) | |
1969 | { | |
1970 | qemu_put_be32(f, chunkstart); | |
1971 | qemu_put_be16(f, n_valid); | |
1972 | qemu_put_be16(f, n_invalid); | |
1973 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1974 | HASH_PTE_SIZE_64 * n_valid); | |
1975 | } | |
1976 | ||
1977 | static void htab_save_end_marker(QEMUFile *f) | |
1978 | { | |
1979 | qemu_put_be32(f, 0); | |
1980 | qemu_put_be16(f, 0); | |
1981 | qemu_put_be16(f, 0); | |
1982 | } | |
1983 | ||
28e02042 | 1984 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1985 | int64_t max_ns) |
1986 | { | |
378bc217 | 1987 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1988 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1989 | int index = spapr->htab_save_index; | |
bc72ad67 | 1990 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1991 | |
1992 | assert(spapr->htab_first_pass); | |
1993 | ||
1994 | do { | |
1995 | int chunkstart; | |
1996 | ||
1997 | /* Consume invalid HPTEs */ | |
1998 | while ((index < htabslots) | |
1999 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 2000 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2001 | index++; |
4be21d56 DG |
2002 | } |
2003 | ||
2004 | /* Consume valid HPTEs */ | |
2005 | chunkstart = index; | |
338c25b6 | 2006 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 2007 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 2008 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2009 | index++; |
4be21d56 DG |
2010 | } |
2011 | ||
2012 | if (index > chunkstart) { | |
2013 | int n_valid = index - chunkstart; | |
2014 | ||
332f7721 | 2015 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 2016 | |
378bc217 DG |
2017 | if (has_timeout && |
2018 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
2019 | break; |
2020 | } | |
2021 | } | |
2022 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
2023 | ||
2024 | if (index >= htabslots) { | |
2025 | assert(index == htabslots); | |
2026 | index = 0; | |
2027 | spapr->htab_first_pass = false; | |
2028 | } | |
2029 | spapr->htab_save_index = index; | |
2030 | } | |
2031 | ||
28e02042 | 2032 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 2033 | int64_t max_ns) |
4be21d56 DG |
2034 | { |
2035 | bool final = max_ns < 0; | |
2036 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
2037 | int examined = 0, sent = 0; | |
2038 | int index = spapr->htab_save_index; | |
bc72ad67 | 2039 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
2040 | |
2041 | assert(!spapr->htab_first_pass); | |
2042 | ||
2043 | do { | |
2044 | int chunkstart, invalidstart; | |
2045 | ||
2046 | /* Consume non-dirty HPTEs */ | |
2047 | while ((index < htabslots) | |
2048 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
2049 | index++; | |
2050 | examined++; | |
2051 | } | |
2052 | ||
2053 | chunkstart = index; | |
2054 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 2055 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
2056 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2057 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
2058 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2059 | index++; | |
2060 | examined++; | |
2061 | } | |
2062 | ||
2063 | invalidstart = index; | |
2064 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 2065 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
2066 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2067 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
2068 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2069 | index++; | |
2070 | examined++; | |
2071 | } | |
2072 | ||
2073 | if (index > chunkstart) { | |
2074 | int n_valid = invalidstart - chunkstart; | |
2075 | int n_invalid = index - invalidstart; | |
2076 | ||
332f7721 | 2077 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
2078 | sent += index - chunkstart; |
2079 | ||
bc72ad67 | 2080 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
2081 | break; |
2082 | } | |
2083 | } | |
2084 | ||
2085 | if (examined >= htabslots) { | |
2086 | break; | |
2087 | } | |
2088 | ||
2089 | if (index >= htabslots) { | |
2090 | assert(index == htabslots); | |
2091 | index = 0; | |
2092 | } | |
2093 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
2094 | ||
2095 | if (index >= htabslots) { | |
2096 | assert(index == htabslots); | |
2097 | index = 0; | |
2098 | } | |
2099 | ||
2100 | spapr->htab_save_index = index; | |
2101 | ||
e68cb8b4 | 2102 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
2103 | } |
2104 | ||
e68cb8b4 AK |
2105 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
2106 | #define MAX_KVM_BUF_SIZE 2048 | |
2107 | ||
4be21d56 DG |
2108 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
2109 | { | |
28e02042 | 2110 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2111 | int fd; |
e68cb8b4 | 2112 | int rc = 0; |
4be21d56 DG |
2113 | |
2114 | /* Iteration header */ | |
3a384297 BR |
2115 | if (!spapr->htab_shift) { |
2116 | qemu_put_be32(f, -1); | |
e8cd4247 | 2117 | return 1; |
3a384297 BR |
2118 | } else { |
2119 | qemu_put_be32(f, 0); | |
2120 | } | |
4be21d56 | 2121 | |
e68cb8b4 AK |
2122 | if (!spapr->htab) { |
2123 | assert(kvm_enabled()); | |
2124 | ||
715c5407 DG |
2125 | fd = get_htab_fd(spapr); |
2126 | if (fd < 0) { | |
2127 | return fd; | |
01a57972 SMJ |
2128 | } |
2129 | ||
715c5407 | 2130 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
2131 | if (rc < 0) { |
2132 | return rc; | |
2133 | } | |
2134 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
2135 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
2136 | } else { | |
e68cb8b4 | 2137 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
2138 | } |
2139 | ||
332f7721 | 2140 | htab_save_end_marker(f); |
4be21d56 | 2141 | |
e68cb8b4 | 2142 | return rc; |
4be21d56 DG |
2143 | } |
2144 | ||
2145 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
2146 | { | |
28e02042 | 2147 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2148 | int fd; |
4be21d56 DG |
2149 | |
2150 | /* Iteration header */ | |
3a384297 BR |
2151 | if (!spapr->htab_shift) { |
2152 | qemu_put_be32(f, -1); | |
2153 | return 0; | |
2154 | } else { | |
2155 | qemu_put_be32(f, 0); | |
2156 | } | |
4be21d56 | 2157 | |
e68cb8b4 AK |
2158 | if (!spapr->htab) { |
2159 | int rc; | |
2160 | ||
2161 | assert(kvm_enabled()); | |
2162 | ||
715c5407 DG |
2163 | fd = get_htab_fd(spapr); |
2164 | if (fd < 0) { | |
2165 | return fd; | |
01a57972 SMJ |
2166 | } |
2167 | ||
715c5407 | 2168 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
2169 | if (rc < 0) { |
2170 | return rc; | |
2171 | } | |
e68cb8b4 | 2172 | } else { |
378bc217 DG |
2173 | if (spapr->htab_first_pass) { |
2174 | htab_save_first_pass(f, spapr, -1); | |
2175 | } | |
e68cb8b4 AK |
2176 | htab_save_later_pass(f, spapr, -1); |
2177 | } | |
4be21d56 DG |
2178 | |
2179 | /* End marker */ | |
332f7721 | 2180 | htab_save_end_marker(f); |
4be21d56 DG |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2186 | { | |
28e02042 | 2187 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 2188 | uint32_t section_hdr; |
e68cb8b4 | 2189 | int fd = -1; |
14b0d748 | 2190 | Error *local_err = NULL; |
4be21d56 DG |
2191 | |
2192 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2193 | error_report("htab_load() bad version"); |
4be21d56 DG |
2194 | return -EINVAL; |
2195 | } | |
2196 | ||
2197 | section_hdr = qemu_get_be32(f); | |
2198 | ||
3a384297 BR |
2199 | if (section_hdr == -1) { |
2200 | spapr_free_hpt(spapr); | |
2201 | return 0; | |
2202 | } | |
2203 | ||
4be21d56 | 2204 | if (section_hdr) { |
c5f54f3e DG |
2205 | /* First section gives the htab size */ |
2206 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2207 | if (local_err) { | |
2208 | error_report_err(local_err); | |
4be21d56 DG |
2209 | return -EINVAL; |
2210 | } | |
2211 | return 0; | |
2212 | } | |
2213 | ||
e68cb8b4 AK |
2214 | if (!spapr->htab) { |
2215 | assert(kvm_enabled()); | |
2216 | ||
14b0d748 | 2217 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2218 | if (fd < 0) { |
14b0d748 | 2219 | error_report_err(local_err); |
82be8e73 | 2220 | return fd; |
e68cb8b4 AK |
2221 | } |
2222 | } | |
2223 | ||
4be21d56 DG |
2224 | while (true) { |
2225 | uint32_t index; | |
2226 | uint16_t n_valid, n_invalid; | |
2227 | ||
2228 | index = qemu_get_be32(f); | |
2229 | n_valid = qemu_get_be16(f); | |
2230 | n_invalid = qemu_get_be16(f); | |
2231 | ||
2232 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2233 | /* End of Stream */ | |
2234 | break; | |
2235 | } | |
2236 | ||
e68cb8b4 | 2237 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2238 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2239 | /* Bad index in stream */ | |
98a5d100 DG |
2240 | error_report( |
2241 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2242 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2243 | return -EINVAL; |
2244 | } | |
2245 | ||
e68cb8b4 AK |
2246 | if (spapr->htab) { |
2247 | if (n_valid) { | |
2248 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2249 | HASH_PTE_SIZE_64 * n_valid); | |
2250 | } | |
2251 | if (n_invalid) { | |
2252 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2253 | HASH_PTE_SIZE_64 * n_invalid); | |
2254 | } | |
2255 | } else { | |
2256 | int rc; | |
2257 | ||
2258 | assert(fd >= 0); | |
2259 | ||
2260 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2261 | if (rc < 0) { | |
2262 | return rc; | |
2263 | } | |
4be21d56 DG |
2264 | } |
2265 | } | |
2266 | ||
e68cb8b4 AK |
2267 | if (!spapr->htab) { |
2268 | assert(fd >= 0); | |
2269 | close(fd); | |
2270 | } | |
2271 | ||
4be21d56 DG |
2272 | return 0; |
2273 | } | |
2274 | ||
70f794fc | 2275 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
2276 | { |
2277 | sPAPRMachineState *spapr = opaque; | |
2278 | ||
2279 | close_htab_fd(spapr); | |
2280 | } | |
2281 | ||
4be21d56 | 2282 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2283 | .save_setup = htab_save_setup, |
4be21d56 | 2284 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2285 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2286 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2287 | .load_state = htab_load, |
2288 | }; | |
2289 | ||
5b2128d2 AG |
2290 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2291 | Error **errp) | |
2292 | { | |
c86c1aff | 2293 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2294 | machine->boot_order = g_strdup(boot_device); |
2295 | } | |
2296 | ||
224245bf DG |
2297 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2298 | { | |
2299 | MachineState *machine = MACHINE(spapr); | |
2300 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2301 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2302 | int i; |
2303 | ||
2304 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2305 | uint64_t addr; |
2306 | ||
b0c14ec4 | 2307 | addr = i * lmb_size + machine->device_memory->base; |
6caf3ac6 DG |
2308 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2309 | addr / lmb_size); | |
224245bf DG |
2310 | } |
2311 | } | |
2312 | ||
2313 | /* | |
2314 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2315 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2316 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2317 | */ | |
7c150d6f | 2318 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2319 | { |
2320 | int i; | |
2321 | ||
7c150d6f DG |
2322 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2323 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
2324 | " is not aligned to %llu MiB", | |
2325 | machine->ram_size, | |
2326 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2327 | return; | |
2328 | } | |
2329 | ||
2330 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2331 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
2332 | " is not aligned to %llu MiB", | |
2333 | machine->ram_size, | |
2334 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2335 | return; | |
224245bf DG |
2336 | } |
2337 | ||
2338 | for (i = 0; i < nb_numa_nodes; i++) { | |
2339 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2340 | error_setg(errp, |
2341 | "Node %d memory size 0x%" PRIx64 | |
2342 | " is not aligned to %llu MiB", | |
2343 | i, numa_info[i].node_mem, | |
2344 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2345 | return; | |
224245bf DG |
2346 | } |
2347 | } | |
2348 | } | |
2349 | ||
535455fd IM |
2350 | /* find cpu slot in machine->possible_cpus by core_id */ |
2351 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2352 | { | |
2353 | int index = id / smp_threads; | |
2354 | ||
2355 | if (index >= ms->possible_cpus->len) { | |
2356 | return NULL; | |
2357 | } | |
2358 | if (idx) { | |
2359 | *idx = index; | |
2360 | } | |
2361 | return &ms->possible_cpus->cpus[index]; | |
2362 | } | |
2363 | ||
fa98fbfc SB |
2364 | static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) |
2365 | { | |
2366 | Error *local_err = NULL; | |
2367 | bool vsmt_user = !!spapr->vsmt; | |
2368 | int kvm_smt = kvmppc_smt_threads(); | |
2369 | int ret; | |
2370 | ||
2371 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2372 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2373 | "on a pseries machine"); | |
2374 | goto out; | |
2375 | } | |
2376 | if (!is_power_of_2(smp_threads)) { | |
2377 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2378 | "machine because it must be a power of 2", smp_threads); | |
2379 | goto out; | |
2380 | } | |
2381 | ||
2382 | /* Detemine the VSMT mode to use: */ | |
2383 | if (vsmt_user) { | |
2384 | if (spapr->vsmt < smp_threads) { | |
2385 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2386 | " because it must be >= threads/core (%d)", | |
2387 | spapr->vsmt, smp_threads); | |
2388 | goto out; | |
2389 | } | |
2390 | /* In this case, spapr->vsmt has been set by the command line */ | |
2391 | } else { | |
8904e5a7 DG |
2392 | /* |
2393 | * Default VSMT value is tricky, because we need it to be as | |
2394 | * consistent as possible (for migration), but this requires | |
2395 | * changing it for at least some existing cases. We pick 8 as | |
2396 | * the value that we'd get with KVM on POWER8, the | |
2397 | * overwhelmingly common case in production systems. | |
2398 | */ | |
4ad64cbd | 2399 | spapr->vsmt = MAX(8, smp_threads); |
fa98fbfc SB |
2400 | } |
2401 | ||
2402 | /* KVM: If necessary, set the SMT mode: */ | |
2403 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2404 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2405 | if (ret) { | |
1f20f2e0 | 2406 | /* Looks like KVM isn't able to change VSMT mode */ |
fa98fbfc SB |
2407 | error_setg(&local_err, |
2408 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2409 | spapr->vsmt, ret); | |
1f20f2e0 DG |
2410 | /* We can live with that if the default one is big enough |
2411 | * for the number of threads, and a submultiple of the one | |
2412 | * we want. In this case we'll waste some vcpu ids, but | |
2413 | * behaviour will be correct */ | |
2414 | if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { | |
2415 | warn_report_err(local_err); | |
2416 | local_err = NULL; | |
2417 | goto out; | |
2418 | } else { | |
2419 | if (!vsmt_user) { | |
2420 | error_append_hint(&local_err, | |
2421 | "On PPC, a VM with %d threads/core" | |
2422 | " on a host with %d threads/core" | |
2423 | " requires the use of VSMT mode %d.\n", | |
2424 | smp_threads, kvm_smt, spapr->vsmt); | |
2425 | } | |
2426 | kvmppc_hint_smt_possible(&local_err); | |
2427 | goto out; | |
fa98fbfc | 2428 | } |
fa98fbfc SB |
2429 | } |
2430 | } | |
2431 | /* else TCG: nothing to do currently */ | |
2432 | out: | |
2433 | error_propagate(errp, local_err); | |
2434 | } | |
2435 | ||
1a5008fc GK |
2436 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2437 | { | |
2438 | MachineState *machine = MACHINE(spapr); | |
2439 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2440 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); | |
2441 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); | |
2442 | const CPUArchIdList *possible_cpus; | |
2443 | int boot_cores_nr = smp_cpus / smp_threads; | |
2444 | int i; | |
2445 | ||
2446 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
2447 | if (mc->has_hotpluggable_cpus) { | |
2448 | if (smp_cpus % smp_threads) { | |
2449 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2450 | smp_cpus, smp_threads); | |
2451 | exit(1); | |
2452 | } | |
2453 | if (max_cpus % smp_threads) { | |
2454 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2455 | max_cpus, smp_threads); | |
2456 | exit(1); | |
2457 | } | |
2458 | } else { | |
2459 | if (max_cpus != smp_cpus) { | |
2460 | error_report("This machine version does not support CPU hotplug"); | |
2461 | exit(1); | |
2462 | } | |
2463 | boot_cores_nr = possible_cpus->len; | |
2464 | } | |
2465 | ||
2466 | /* VSMT must be set in order to be able to compute VCPU ids, ie to | |
2467 | * call xics_max_server_number() or spapr_vcpu_id(). | |
2468 | */ | |
2469 | spapr_set_vsmt_mode(spapr, &error_fatal); | |
2470 | ||
2471 | if (smc->pre_2_10_has_unused_icps) { | |
2472 | int i; | |
2473 | ||
2474 | for (i = 0; i < xics_max_server_number(spapr); i++) { | |
2475 | /* Dummy entries get deregistered when real ICPState objects | |
2476 | * are registered during CPU core hotplug. | |
2477 | */ | |
2478 | pre_2_10_vmstate_register_dummy_icp(i); | |
2479 | } | |
2480 | } | |
2481 | ||
2482 | for (i = 0; i < possible_cpus->len; i++) { | |
2483 | int core_id = i * smp_threads; | |
2484 | ||
2485 | if (mc->has_hotpluggable_cpus) { | |
2486 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, | |
2487 | spapr_vcpu_id(spapr, core_id)); | |
2488 | } | |
2489 | ||
2490 | if (i < boot_cores_nr) { | |
2491 | Object *core = object_new(type); | |
2492 | int nr_threads = smp_threads; | |
2493 | ||
2494 | /* Handle the partially filled core for older machine types */ | |
2495 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2496 | nr_threads = smp_cpus - i * smp_threads; | |
2497 | } | |
2498 | ||
2499 | object_property_set_int(core, nr_threads, "nr-threads", | |
2500 | &error_fatal); | |
2501 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2502 | &error_fatal); | |
2503 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2504 | } | |
2505 | } | |
2506 | } | |
2507 | ||
9fdf0c29 | 2508 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2509 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2510 | { |
28e02042 | 2511 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2512 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2513 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2514 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2515 | PCIHostState *phb; |
9fdf0c29 | 2516 | int i; |
890c2b77 AK |
2517 | MemoryRegion *sysmem = get_system_memory(); |
2518 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
c86c1aff | 2519 | hwaddr node0_size = spapr_node0_size(machine); |
b7d1f77a | 2520 | long load_limit, fw_size; |
39ac8455 | 2521 | char *filename; |
30f4b05b | 2522 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2523 | |
226419d6 | 2524 | msi_nonbroken = true; |
0ee2c058 | 2525 | |
d43b45e2 | 2526 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2527 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2528 | |
9f6edd06 DG |
2529 | /* Determine capabilities to run with */ |
2530 | spapr_caps_init(spapr); | |
2531 | ||
30f4b05b DG |
2532 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); |
2533 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2534 | /* | |
2535 | * If the user explicitly requested a mode we should either | |
2536 | * supply it, or fail completely (which we do below). But if | |
2537 | * it's not set explicitly, we reset our mode to something | |
2538 | * that works | |
2539 | */ | |
2540 | if (resize_hpt_err) { | |
2541 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2542 | error_free(resize_hpt_err); | |
2543 | resize_hpt_err = NULL; | |
2544 | } else { | |
2545 | spapr->resize_hpt = smc->resize_hpt_default; | |
2546 | } | |
2547 | } | |
2548 | ||
2549 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2550 | ||
2551 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2552 | /* | |
2553 | * User requested HPT resize, but this host can't supply it. Bail out | |
2554 | */ | |
2555 | error_report_err(resize_hpt_err); | |
2556 | exit(1); | |
2557 | } | |
2558 | ||
090052aa | 2559 | spapr->rma_size = node0_size; |
354ac20a | 2560 | |
090052aa DG |
2561 | /* With KVM, we don't actually know whether KVM supports an |
2562 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2563 | * (HV KVM using VRMA), so we always assume the latter | |
2564 | * | |
2565 | * In that case, we also limit the initial allocations for RTAS | |
2566 | * etc... to 256M since we have no way to know what the VRMA size | |
2567 | * is going to be as it depends on the size of the hash table | |
2568 | * which isn't determined yet. | |
2569 | */ | |
2570 | if (kvm_enabled()) { | |
2571 | spapr->vrma_adjust = 1; | |
2572 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
354ac20a | 2573 | } |
7f763a5d | 2574 | |
090052aa DG |
2575 | /* Actually we don't support unbounded RMA anymore since we added |
2576 | * proper emulation of HV mode. The max we can get is 16G which | |
2577 | * also happens to be what we configure for PAPR mode so make sure | |
2578 | * we don't do anything bigger than that | |
2579 | */ | |
2580 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a | 2581 | |
c4177479 | 2582 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2583 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2584 | spapr->rma_size); | |
c4177479 AK |
2585 | exit(1); |
2586 | } | |
2587 | ||
b7d1f77a BH |
2588 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2589 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2590 | |
7b565160 | 2591 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2592 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2593 | |
dc1b5eee GK |
2594 | /* Set up containers for ibm,client-architecture-support negotiated options |
2595 | */ | |
facdb8b6 MR |
2596 | spapr->ov5 = spapr_ovec_new(); |
2597 | spapr->ov5_cas = spapr_ovec_new(); | |
2598 | ||
224245bf | 2599 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2600 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2601 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2602 | } |
2603 | ||
417ece33 MR |
2604 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
2605 | ||
ffbb1705 MR |
2606 | /* advertise support for dedicated HP event source to guests */ |
2607 | if (spapr->use_hotplug_event_source) { | |
2608 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2609 | } | |
2610 | ||
2772cf6b DG |
2611 | /* advertise support for HPT resizing */ |
2612 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2613 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2614 | } | |
2615 | ||
a324d6f1 BR |
2616 | /* advertise support for ibm,dyamic-memory-v2 */ |
2617 | spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); | |
2618 | ||
9fdf0c29 | 2619 | /* init CPUs */ |
0c86d0fd | 2620 | spapr_init_cpus(spapr); |
9fdf0c29 | 2621 | |
0550b120 | 2622 | if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && |
ad99d04c DG |
2623 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
2624 | spapr->max_compat_pvr)) { | |
0550b120 GK |
2625 | /* KVM and TCG always allow GTSE with radix... */ |
2626 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); | |
2627 | } | |
2628 | /* ... but not with hash (currently). */ | |
2629 | ||
026bfd89 DG |
2630 | if (kvm_enabled()) { |
2631 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2632 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2633 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2634 | |
2635 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2636 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2637 | } |
2638 | ||
9fdf0c29 | 2639 | /* allocate RAM */ |
f92f5da1 | 2640 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2641 | machine->ram_size); |
f92f5da1 | 2642 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2643 | |
b0c14ec4 DH |
2644 | /* always allocate the device memory information */ |
2645 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
2646 | ||
4a1c9cf0 BR |
2647 | /* initialize hotplug memory address space */ |
2648 | if (machine->ram_size < machine->maxram_size) { | |
0c9269a5 | 2649 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
71c9a3dd BR |
2650 | /* |
2651 | * Limit the number of hotpluggable memory slots to half the number | |
2652 | * slots that KVM supports, leaving the other half for PCI and other | |
2653 | * devices. However ensure that number of slots doesn't drop below 32. | |
2654 | */ | |
2655 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2656 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2657 | |
71c9a3dd BR |
2658 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2659 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2660 | } | |
2661 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2662 | error_report("Specified number of memory slots %" |
2663 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2664 | machine->ram_slots, max_memslots); |
d54e4d76 | 2665 | exit(1); |
4a1c9cf0 BR |
2666 | } |
2667 | ||
b0c14ec4 | 2668 | machine->device_memory->base = ROUND_UP(machine->ram_size, |
0c9269a5 | 2669 | SPAPR_DEVICE_MEM_ALIGN); |
b0c14ec4 | 2670 | memory_region_init(&machine->device_memory->mr, OBJECT(spapr), |
0c9269a5 | 2671 | "device-memory", device_mem_size); |
b0c14ec4 DH |
2672 | memory_region_add_subregion(sysmem, machine->device_memory->base, |
2673 | &machine->device_memory->mr); | |
4a1c9cf0 BR |
2674 | } |
2675 | ||
224245bf DG |
2676 | if (smc->dr_lmb_enabled) { |
2677 | spapr_create_lmb_dr_connectors(spapr); | |
2678 | } | |
2679 | ||
39ac8455 | 2680 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2681 | if (!filename) { |
730fce59 | 2682 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2683 | exit(1); |
2684 | } | |
b7d1f77a | 2685 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2686 | if (spapr->rtas_size < 0) { |
2687 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2688 | exit(1); | |
2689 | } | |
b7d1f77a BH |
2690 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2691 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2692 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2693 | exit(1); |
2694 | } | |
4d8d5467 | 2695 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2696 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2697 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2698 | exit(1); |
2699 | } | |
7267c094 | 2700 | g_free(filename); |
39ac8455 | 2701 | |
ffbb1705 | 2702 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2703 | spapr_events_init(spapr); |
2704 | ||
12f42174 | 2705 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2706 | spapr_rtc_create(spapr); |
12f42174 | 2707 | |
b5cec4c5 | 2708 | /* Set up VIO bus */ |
4040ab72 DG |
2709 | spapr->vio_bus = spapr_vio_bus_init(); |
2710 | ||
b8846a4d | 2711 | for (i = 0; i < serial_max_hds(); i++) { |
9bca0edb PM |
2712 | if (serial_hd(i)) { |
2713 | spapr_vty_create(spapr->vio_bus, serial_hd(i)); | |
4040ab72 DG |
2714 | } |
2715 | } | |
9fdf0c29 | 2716 | |
639e8102 DG |
2717 | /* We always have at least the nvram device on VIO */ |
2718 | spapr_create_nvram(spapr); | |
2719 | ||
3384f95c | 2720 | /* Set up PCI */ |
fa28f71b AK |
2721 | spapr_pci_rtas_init(); |
2722 | ||
89dfd6e1 | 2723 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2724 | |
277f9acf | 2725 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2726 | NICInfo *nd = &nd_table[i]; |
2727 | ||
2728 | if (!nd->model) { | |
3c3a4e7a | 2729 | nd->model = g_strdup("spapr-vlan"); |
8d90ad90 DG |
2730 | } |
2731 | ||
3c3a4e7a TH |
2732 | if (g_str_equal(nd->model, "spapr-vlan") || |
2733 | g_str_equal(nd->model, "ibmveth")) { | |
d601fac4 | 2734 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2735 | } else { |
29b358f9 | 2736 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2737 | } |
2738 | } | |
2739 | ||
6e270446 | 2740 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2741 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2742 | } |
2743 | ||
f28359d8 | 2744 | /* Graphics */ |
14c6a894 | 2745 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2746 | spapr->has_graphics = true; |
c6e76503 | 2747 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2748 | } |
2749 | ||
4ee9ced9 | 2750 | if (machine->usb) { |
57040d45 TH |
2751 | if (smc->use_ohci_by_default) { |
2752 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2753 | } else { | |
2754 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2755 | } | |
c86580b8 | 2756 | |
35139a59 | 2757 | if (spapr->has_graphics) { |
c86580b8 MA |
2758 | USBBus *usb_bus = usb_bus_find(-1); |
2759 | ||
2760 | usb_create_simple(usb_bus, "usb-kbd"); | |
2761 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2762 | } |
2763 | } | |
2764 | ||
7f763a5d | 2765 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2766 | error_report( |
2767 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2768 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2769 | exit(1); |
2770 | } | |
2771 | ||
9fdf0c29 DG |
2772 | if (kernel_filename) { |
2773 | uint64_t lowaddr = 0; | |
2774 | ||
a19f7fb0 DG |
2775 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2776 | NULL, NULL, &lowaddr, NULL, 1, | |
2777 | PPC_ELF_MACHINE, 0, 0); | |
2778 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2779 | spapr->kernel_size = load_elf(kernel_filename, | |
2780 | translate_kernel_address, NULL, NULL, | |
2781 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2782 | 0, 0); | |
2783 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2784 | } |
a19f7fb0 DG |
2785 | if (spapr->kernel_size < 0) { |
2786 | error_report("error loading %s: %s", kernel_filename, | |
2787 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2788 | exit(1); |
2789 | } | |
2790 | ||
2791 | /* load initrd */ | |
2792 | if (initrd_filename) { | |
4d8d5467 BH |
2793 | /* Try to locate the initrd in the gap between the kernel |
2794 | * and the firmware. Add a bit of space just in case | |
2795 | */ | |
a19f7fb0 DG |
2796 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2797 | + 0x1ffff) & ~0xffff; | |
2798 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2799 | spapr->initrd_base, | |
2800 | load_limit | |
2801 | - spapr->initrd_base); | |
2802 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2803 | error_report("could not load initial ram disk '%s'", |
2804 | initrd_filename); | |
9fdf0c29 DG |
2805 | exit(1); |
2806 | } | |
9fdf0c29 | 2807 | } |
4d8d5467 | 2808 | } |
a3467baa | 2809 | |
8e7ea787 AF |
2810 | if (bios_name == NULL) { |
2811 | bios_name = FW_FILE_NAME; | |
2812 | } | |
2813 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2814 | if (!filename) { |
68fea5a0 | 2815 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2816 | exit(1); |
2817 | } | |
4d8d5467 | 2818 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2819 | if (fw_size <= 0) { |
2820 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2821 | exit(1); |
2822 | } | |
2823 | g_free(filename); | |
4d8d5467 | 2824 | |
28e02042 DG |
2825 | /* FIXME: Should register things through the MachineState's qdev |
2826 | * interface, this is a legacy from the sPAPREnvironment structure | |
2827 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2828 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2829 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2830 | &savevm_htab_handlers, spapr); | |
2831 | ||
5b2128d2 | 2832 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2833 | |
42043e4f | 2834 | if (kvm_enabled()) { |
3dc410ae | 2835 | /* to stop and start vmclock */ |
42043e4f LV |
2836 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2837 | &spapr->tb); | |
3dc410ae AK |
2838 | |
2839 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2840 | } |
9fdf0c29 DG |
2841 | } |
2842 | ||
135a129a AK |
2843 | static int spapr_kvm_type(const char *vm_type) |
2844 | { | |
2845 | if (!vm_type) { | |
2846 | return 0; | |
2847 | } | |
2848 | ||
2849 | if (!strcmp(vm_type, "HV")) { | |
2850 | return 1; | |
2851 | } | |
2852 | ||
2853 | if (!strcmp(vm_type, "PR")) { | |
2854 | return 2; | |
2855 | } | |
2856 | ||
2857 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2858 | exit(1); | |
2859 | } | |
2860 | ||
71461b0f | 2861 | /* |
627b84f4 | 2862 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2863 | * for the bootindex property handling. |
2864 | */ | |
2865 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2866 | DeviceState *dev) | |
2867 | { | |
2868 | #define CAST(type, obj, name) \ | |
2869 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2870 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2871 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2872 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2873 | |
2874 | if (d) { | |
2875 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2876 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2877 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2878 | ||
2879 | if (spapr) { | |
2880 | /* | |
2881 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2882 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2883 | * in the top 16 bits of the 64-bit LUN | |
2884 | */ | |
2885 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2886 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2887 | (uint64_t)id << 48); | |
2888 | } else if (virtio) { | |
2889 | /* | |
2890 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2891 | * in the top 32 bits of the 64-bit LUN | |
2892 | * Note: the quote above is from SLOF and it is wrong, | |
2893 | * the actual binding is: | |
2894 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2895 | */ | |
2896 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
2897 | if (d->lun >= 256) { |
2898 | /* Use the LUN "flat space addressing method" */ | |
2899 | id |= 0x4000; | |
2900 | } | |
71461b0f AK |
2901 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
2902 | (uint64_t)id << 32); | |
2903 | } else if (usb) { | |
2904 | /* | |
2905 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2906 | * in the top 32 bits of the 64-bit LUN | |
2907 | */ | |
2908 | unsigned usb_port = atoi(usb->port->path); | |
2909 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2910 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2911 | (uint64_t)id << 32); | |
2912 | } | |
2913 | } | |
2914 | ||
b99260eb TH |
2915 | /* |
2916 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2917 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2918 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2919 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2920 | */ | |
2921 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2922 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2923 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2924 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2925 | } | |
2926 | } | |
2927 | ||
71461b0f AK |
2928 | if (phb) { |
2929 | /* Replace "pci" with "pci@800000020000000" */ | |
2930 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2931 | } | |
2932 | ||
c4e13492 FF |
2933 | if (vsc) { |
2934 | /* Same logic as virtio above */ | |
2935 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2936 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2937 | } | |
2938 | ||
4871dd4c TH |
2939 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2940 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2941 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2942 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2943 | } | |
2944 | ||
71461b0f AK |
2945 | return NULL; |
2946 | } | |
2947 | ||
23825581 EH |
2948 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2949 | { | |
28e02042 | 2950 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2951 | |
28e02042 | 2952 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2953 | } |
2954 | ||
2955 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2956 | { | |
28e02042 | 2957 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2958 | |
28e02042 DG |
2959 | g_free(spapr->kvm_type); |
2960 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2961 | } |
2962 | ||
f6229214 MR |
2963 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2964 | { | |
2965 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2966 | ||
2967 | return spapr->use_hotplug_event_source; | |
2968 | } | |
2969 | ||
2970 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2971 | Error **errp) | |
2972 | { | |
2973 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2974 | ||
2975 | spapr->use_hotplug_event_source = value; | |
2976 | } | |
2977 | ||
fcad0d21 AK |
2978 | static bool spapr_get_msix_emulation(Object *obj, Error **errp) |
2979 | { | |
2980 | return true; | |
2981 | } | |
2982 | ||
30f4b05b DG |
2983 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2984 | { | |
2985 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2986 | ||
2987 | switch (spapr->resize_hpt) { | |
2988 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2989 | return g_strdup("default"); | |
2990 | case SPAPR_RESIZE_HPT_DISABLED: | |
2991 | return g_strdup("disabled"); | |
2992 | case SPAPR_RESIZE_HPT_ENABLED: | |
2993 | return g_strdup("enabled"); | |
2994 | case SPAPR_RESIZE_HPT_REQUIRED: | |
2995 | return g_strdup("required"); | |
2996 | } | |
2997 | g_assert_not_reached(); | |
2998 | } | |
2999 | ||
3000 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
3001 | { | |
3002 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
3003 | ||
3004 | if (strcmp(value, "default") == 0) { | |
3005 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
3006 | } else if (strcmp(value, "disabled") == 0) { | |
3007 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
3008 | } else if (strcmp(value, "enabled") == 0) { | |
3009 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
3010 | } else if (strcmp(value, "required") == 0) { | |
3011 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
3012 | } else { | |
3013 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
3014 | } | |
3015 | } | |
3016 | ||
fa98fbfc SB |
3017 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
3018 | void *opaque, Error **errp) | |
3019 | { | |
3020 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
3021 | } | |
3022 | ||
3023 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, | |
3024 | void *opaque, Error **errp) | |
3025 | { | |
3026 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
3027 | } | |
3028 | ||
bcb5ce08 | 3029 | static void spapr_instance_init(Object *obj) |
23825581 | 3030 | { |
715c5407 DG |
3031 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
3032 | ||
3033 | spapr->htab_fd = -1; | |
f6229214 | 3034 | spapr->use_hotplug_event_source = true; |
23825581 EH |
3035 | object_property_add_str(obj, "kvm-type", |
3036 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
3037 | object_property_set_description(obj, "kvm-type", |
3038 | "Specifies the KVM virtualization mode (HV, PR)", | |
3039 | NULL); | |
f6229214 MR |
3040 | object_property_add_bool(obj, "modern-hotplug-events", |
3041 | spapr_get_modern_hotplug_events, | |
3042 | spapr_set_modern_hotplug_events, | |
3043 | NULL); | |
3044 | object_property_set_description(obj, "modern-hotplug-events", | |
3045 | "Use dedicated hotplug event mechanism in" | |
3046 | " place of standard EPOW events when possible" | |
3047 | " (required for memory hot-unplug support)", | |
3048 | NULL); | |
7843c0d6 DG |
3049 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, |
3050 | "Maximum permitted CPU compatibility mode", | |
3051 | &error_fatal); | |
30f4b05b DG |
3052 | |
3053 | object_property_add_str(obj, "resize-hpt", | |
3054 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
3055 | object_property_set_description(obj, "resize-hpt", | |
3056 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
3057 | NULL); | |
fa98fbfc SB |
3058 | object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, |
3059 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); | |
3060 | object_property_set_description(obj, "vsmt", | |
3061 | "Virtual SMT: KVM behaves as if this were" | |
3062 | " the host's SMT mode", &error_abort); | |
fcad0d21 AK |
3063 | object_property_add_bool(obj, "vfio-no-msix-emulation", |
3064 | spapr_get_msix_emulation, NULL, NULL); | |
23825581 EH |
3065 | } |
3066 | ||
87bbdd9c DG |
3067 | static void spapr_machine_finalizefn(Object *obj) |
3068 | { | |
3069 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
3070 | ||
3071 | g_free(spapr->kvm_type); | |
3072 | } | |
3073 | ||
1c7ad77e | 3074 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 3075 | { |
34316482 AK |
3076 | cpu_synchronize_state(cs); |
3077 | ppc_cpu_do_system_reset(cs); | |
3078 | } | |
3079 | ||
3080 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
3081 | { | |
3082 | CPUState *cs; | |
3083 | ||
3084 | CPU_FOREACH(cs) { | |
1c7ad77e | 3085 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
3086 | } |
3087 | } | |
3088 | ||
79b78a6b MR |
3089 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
3090 | uint32_t node, bool dedicated_hp_event_source, | |
3091 | Error **errp) | |
c20d332a BR |
3092 | { |
3093 | sPAPRDRConnector *drc; | |
c20d332a BR |
3094 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
3095 | int i, fdt_offset, fdt_size; | |
3096 | void *fdt; | |
79b78a6b | 3097 | uint64_t addr = addr_start; |
94fd9cba | 3098 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 3099 | Error *local_err = NULL; |
c20d332a | 3100 | |
c20d332a | 3101 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
3102 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3103 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
3104 | g_assert(drc); |
3105 | ||
3106 | fdt = create_device_tree(&fdt_size); | |
3107 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
3108 | SPAPR_MEMORY_BLOCK_SIZE); | |
3109 | ||
160bb678 GK |
3110 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
3111 | if (local_err) { | |
3112 | while (addr > addr_start) { | |
3113 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
3114 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
3115 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 3116 | spapr_drc_detach(drc); |
160bb678 GK |
3117 | } |
3118 | g_free(fdt); | |
3119 | error_propagate(errp, local_err); | |
3120 | return; | |
3121 | } | |
94fd9cba LV |
3122 | if (!hotplugged) { |
3123 | spapr_drc_reset(drc); | |
3124 | } | |
c20d332a BR |
3125 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3126 | } | |
5dd5238c JD |
3127 | /* send hotplug notification to the |
3128 | * guest only in case of hotplugged memory | |
3129 | */ | |
94fd9cba | 3130 | if (hotplugged) { |
79b78a6b | 3131 | if (dedicated_hp_event_source) { |
fbf55397 DG |
3132 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3133 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
3134 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3135 | nr_lmbs, | |
0b55aa91 | 3136 | spapr_drc_index(drc)); |
79b78a6b MR |
3137 | } else { |
3138 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
3139 | nr_lmbs); | |
3140 | } | |
5dd5238c | 3141 | } |
c20d332a BR |
3142 | } |
3143 | ||
3144 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
81985f3b | 3145 | Error **errp) |
c20d332a BR |
3146 | { |
3147 | Error *local_err = NULL; | |
3148 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
3149 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3150 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3151 | MemoryRegion *mr; |
3152 | uint64_t align, size, addr; | |
81985f3b | 3153 | uint32_t node; |
04790978 TH |
3154 | |
3155 | mr = ddc->get_memory_region(dimm, &local_err); | |
3156 | if (local_err) { | |
3157 | goto out; | |
3158 | } | |
3159 | align = memory_region_get_alignment(mr); | |
3160 | size = memory_region_size(mr); | |
df587133 | 3161 | |
bd6c3e4a | 3162 | pc_dimm_memory_plug(dev, MACHINE(ms), align, &local_err); |
c20d332a BR |
3163 | if (local_err) { |
3164 | goto out; | |
3165 | } | |
3166 | ||
9ed442b8 MAL |
3167 | addr = object_property_get_uint(OBJECT(dimm), |
3168 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 3169 | if (local_err) { |
160bb678 | 3170 | goto out_unplug; |
c20d332a BR |
3171 | } |
3172 | ||
81985f3b DH |
3173 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, |
3174 | &error_abort); | |
79b78a6b MR |
3175 | spapr_add_lmbs(dev, addr, size, node, |
3176 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
3177 | &local_err); |
3178 | if (local_err) { | |
3179 | goto out_unplug; | |
3180 | } | |
3181 | ||
3182 | return; | |
c20d332a | 3183 | |
160bb678 | 3184 | out_unplug: |
bd6c3e4a | 3185 | pc_dimm_memory_unplug(dev, MACHINE(ms)); |
c20d332a BR |
3186 | out: |
3187 | error_propagate(errp, local_err); | |
3188 | } | |
3189 | ||
c871bc70 LV |
3190 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3191 | Error **errp) | |
3192 | { | |
4e8a01bd | 3193 | const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); |
c871bc70 LV |
3194 | PCDIMMDevice *dimm = PC_DIMM(dev); |
3195 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3196 | MemoryRegion *mr; |
3197 | uint64_t size; | |
c871bc70 LV |
3198 | char *mem_dev; |
3199 | ||
4e8a01bd DH |
3200 | if (!smc->dr_lmb_enabled) { |
3201 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3202 | return; | |
3203 | } | |
3204 | ||
04790978 TH |
3205 | mr = ddc->get_memory_region(dimm, errp); |
3206 | if (!mr) { | |
3207 | return; | |
3208 | } | |
3209 | size = memory_region_size(mr); | |
3210 | ||
c871bc70 LV |
3211 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3212 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
3213 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
3214 | return; | |
3215 | } | |
3216 | ||
3217 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
3218 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
3219 | error_setg(errp, "Memory backend has bad page size. " | |
3220 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 3221 | goto out; |
c871bc70 | 3222 | } |
8a9e0e7b GK |
3223 | |
3224 | out: | |
3225 | g_free(mem_dev); | |
c871bc70 LV |
3226 | } |
3227 | ||
0cffce56 DG |
3228 | struct sPAPRDIMMState { |
3229 | PCDIMMDevice *dimm; | |
cf632463 | 3230 | uint32_t nr_lmbs; |
0cffce56 DG |
3231 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
3232 | }; | |
3233 | ||
3234 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
3235 | PCDIMMDevice *dimm) | |
3236 | { | |
3237 | sPAPRDIMMState *dimm_state = NULL; | |
3238 | ||
3239 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3240 | if (dimm_state->dimm == dimm) { | |
3241 | break; | |
3242 | } | |
3243 | } | |
3244 | return dimm_state; | |
3245 | } | |
3246 | ||
8d5981c4 BR |
3247 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, |
3248 | uint32_t nr_lmbs, | |
3249 | PCDIMMDevice *dimm) | |
0cffce56 | 3250 | { |
8d5981c4 BR |
3251 | sPAPRDIMMState *ds = NULL; |
3252 | ||
3253 | /* | |
3254 | * If this request is for a DIMM whose removal had failed earlier | |
3255 | * (due to guest's refusal to remove the LMBs), we would have this | |
3256 | * dimm already in the pending_dimm_unplugs list. In that | |
3257 | * case don't add again. | |
3258 | */ | |
3259 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3260 | if (!ds) { | |
3261 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
3262 | ds->nr_lmbs = nr_lmbs; | |
3263 | ds->dimm = dimm; | |
3264 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3265 | } | |
3266 | return ds; | |
0cffce56 DG |
3267 | } |
3268 | ||
3269 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
3270 | sPAPRDIMMState *dimm_state) | |
3271 | { | |
3272 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3273 | g_free(dimm_state); | |
3274 | } | |
cf632463 | 3275 | |
16ee9980 DHB |
3276 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
3277 | PCDIMMDevice *dimm) | |
3278 | { | |
3279 | sPAPRDRConnector *drc; | |
3280 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3281 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
16ee9980 DHB |
3282 | uint64_t size = memory_region_size(mr); |
3283 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3284 | uint32_t avail_lmbs = 0; | |
3285 | uint64_t addr_start, addr; | |
3286 | int i; | |
16ee9980 DHB |
3287 | |
3288 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3289 | &error_abort); | |
3290 | ||
3291 | addr = addr_start; | |
3292 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3293 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3294 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3295 | g_assert(drc); |
454b580a | 3296 | if (drc->dev) { |
16ee9980 DHB |
3297 | avail_lmbs++; |
3298 | } | |
3299 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3300 | } | |
3301 | ||
8d5981c4 | 3302 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3303 | } |
3304 | ||
31834723 DHB |
3305 | /* Callback to be called during DRC release. */ |
3306 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3307 | { |
3ec71474 DH |
3308 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3309 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); | |
0cffce56 | 3310 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 3311 | |
16ee9980 DHB |
3312 | /* This information will get lost if a migration occurs |
3313 | * during the unplug process. In this case recover it. */ | |
3314 | if (ds == NULL) { | |
3315 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3316 | g_assert(ds); |
454b580a DG |
3317 | /* The DRC being examined by the caller at least must be counted */ |
3318 | g_assert(ds->nr_lmbs); | |
3319 | } | |
3320 | ||
3321 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3322 | return; |
3323 | } | |
3324 | ||
cf632463 BR |
3325 | /* |
3326 | * Now that all the LMBs have been removed by the guest, call the | |
3ec71474 | 3327 | * unplug handler chain. This can never fail. |
cf632463 | 3328 | */ |
3ec71474 DH |
3329 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
3330 | } | |
3331 | ||
3332 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3333 | { | |
3334 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); | |
3335 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); | |
3336 | ||
3337 | pc_dimm_memory_unplug(dev, MACHINE(hotplug_dev)); | |
cf632463 | 3338 | object_unparent(OBJECT(dev)); |
2a129767 | 3339 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3340 | } |
3341 | ||
3342 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3343 | DeviceState *dev, Error **errp) | |
3344 | { | |
0cffce56 | 3345 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3346 | Error *local_err = NULL; |
3347 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3348 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3349 | MemoryRegion *mr; |
3350 | uint32_t nr_lmbs; | |
3351 | uint64_t size, addr_start, addr; | |
0cffce56 DG |
3352 | int i; |
3353 | sPAPRDRConnector *drc; | |
04790978 TH |
3354 | |
3355 | mr = ddc->get_memory_region(dimm, &local_err); | |
3356 | if (local_err) { | |
3357 | goto out; | |
3358 | } | |
3359 | size = memory_region_size(mr); | |
3360 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3361 | ||
9ed442b8 | 3362 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3363 | &local_err); |
cf632463 BR |
3364 | if (local_err) { |
3365 | goto out; | |
3366 | } | |
3367 | ||
2a129767 DHB |
3368 | /* |
3369 | * An existing pending dimm state for this DIMM means that there is an | |
3370 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3371 | * callback to complete the job (BQL can't cover that far). In this case, | |
3372 | * bail out to avoid detaching DRCs that were already released. | |
3373 | */ | |
3374 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3375 | error_setg(&local_err, | |
3376 | "Memory unplug already in progress for device %s", | |
3377 | dev->id); | |
3378 | goto out; | |
3379 | } | |
3380 | ||
8d5981c4 | 3381 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3382 | |
3383 | addr = addr_start; | |
3384 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3385 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3386 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3387 | g_assert(drc); |
3388 | ||
a8dc47fd | 3389 | spapr_drc_detach(drc); |
0cffce56 DG |
3390 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3391 | } | |
3392 | ||
fbf55397 DG |
3393 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3394 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3395 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3396 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3397 | out: |
3398 | error_propagate(errp, local_err); | |
3399 | } | |
3400 | ||
04d0ffbd GK |
3401 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
3402 | sPAPRMachineState *spapr) | |
af81cf32 BR |
3403 | { |
3404 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3405 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 3406 | int id = spapr_get_vcpu_id(cpu); |
af81cf32 BR |
3407 | void *fdt; |
3408 | int offset, fdt_size; | |
3409 | char *nodename; | |
3410 | ||
3411 | fdt = create_device_tree(&fdt_size); | |
3412 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3413 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3414 | ||
3415 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
3416 | g_free(nodename); | |
3417 | ||
3418 | *fdt_offset = offset; | |
3419 | return fdt; | |
3420 | } | |
3421 | ||
765d1bdd DG |
3422 | /* Callback to be called during DRC release. */ |
3423 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3424 | { |
a4261be1 DH |
3425 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3426 | ||
3427 | /* Call the unplug handler chain. This can never fail. */ | |
3428 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
3429 | } | |
3430 | ||
3431 | static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3432 | { | |
3433 | MachineState *ms = MACHINE(hotplug_dev); | |
46f7afa3 | 3434 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3435 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3436 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3437 | |
46f7afa3 GK |
3438 | if (smc->pre_2_10_has_unused_icps) { |
3439 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
46f7afa3 GK |
3440 | int i; |
3441 | ||
3442 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3443 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3444 | |
3445 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3446 | } | |
3447 | } | |
3448 | ||
07572c06 | 3449 | assert(core_slot); |
535455fd | 3450 | core_slot->cpu = NULL; |
ff9006dd IM |
3451 | object_unparent(OBJECT(dev)); |
3452 | } | |
3453 | ||
115debf2 IM |
3454 | static |
3455 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3456 | Error **errp) | |
ff9006dd | 3457 | { |
72194664 | 3458 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
535455fd IM |
3459 | int index; |
3460 | sPAPRDRConnector *drc; | |
535455fd | 3461 | CPUCore *cc = CPU_CORE(dev); |
ff9006dd | 3462 | |
535455fd IM |
3463 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3464 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3465 | cc->core_id); | |
3466 | return; | |
3467 | } | |
ff9006dd IM |
3468 | if (index == 0) { |
3469 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3470 | return; | |
3471 | } | |
3472 | ||
5d0fb150 GK |
3473 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3474 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd IM |
3475 | g_assert(drc); |
3476 | ||
a8dc47fd | 3477 | spapr_drc_detach(drc); |
ff9006dd IM |
3478 | |
3479 | spapr_hotplug_req_remove_by_index(drc); | |
3480 | } | |
3481 | ||
3482 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3483 | Error **errp) | |
3484 | { | |
3485 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3486 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3487 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3488 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3489 | CPUCore *cc = CPU_CORE(dev); | |
94ad93bd | 3490 | CPUState *cs = CPU(core->threads[0]); |
ff9006dd IM |
3491 | sPAPRDRConnector *drc; |
3492 | Error *local_err = NULL; | |
535455fd IM |
3493 | CPUArchId *core_slot; |
3494 | int index; | |
94fd9cba | 3495 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3496 | |
535455fd IM |
3497 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3498 | if (!core_slot) { | |
3499 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3500 | cc->core_id); | |
3501 | return; | |
3502 | } | |
5d0fb150 GK |
3503 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3504 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd | 3505 | |
c5514d0e | 3506 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3507 | |
ff9006dd | 3508 | if (drc) { |
e49c63d5 GK |
3509 | void *fdt; |
3510 | int fdt_offset; | |
3511 | ||
3512 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3513 | ||
5c1da812 | 3514 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3515 | if (local_err) { |
3516 | g_free(fdt); | |
ff9006dd IM |
3517 | error_propagate(errp, local_err); |
3518 | return; | |
3519 | } | |
ff9006dd | 3520 | |
94fd9cba LV |
3521 | if (hotplugged) { |
3522 | /* | |
3523 | * Send hotplug notification interrupt to the guest only | |
3524 | * in case of hotplugged CPUs. | |
3525 | */ | |
3526 | spapr_hotplug_req_add_by_index(drc); | |
3527 | } else { | |
3528 | spapr_drc_reset(drc); | |
3529 | } | |
ff9006dd | 3530 | } |
94fd9cba | 3531 | |
535455fd | 3532 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3533 | |
3534 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 GK |
3535 | int i; |
3536 | ||
3537 | for (i = 0; i < cc->nr_threads; i++) { | |
bc877283 | 3538 | cs = CPU(core->threads[i]); |
46f7afa3 GK |
3539 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3540 | } | |
3541 | } | |
ff9006dd IM |
3542 | } |
3543 | ||
3544 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3545 | Error **errp) | |
3546 | { | |
3547 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3548 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3549 | Error *local_err = NULL; |
3550 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3551 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3552 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3553 | CPUArchId *core_slot; |
3554 | int index; | |
ff9006dd | 3555 | |
c5514d0e | 3556 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3557 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3558 | goto out; | |
3559 | } | |
3560 | ||
3561 | if (strcmp(base_core_type, type)) { | |
3562 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3563 | goto out; | |
3564 | } | |
3565 | ||
3566 | if (cc->core_id % smp_threads) { | |
3567 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3568 | goto out; | |
3569 | } | |
3570 | ||
459264ef DG |
3571 | /* |
3572 | * In general we should have homogeneous threads-per-core, but old | |
3573 | * (pre hotplug support) machine types allow the last core to have | |
3574 | * reduced threads as a compatibility hack for when we allowed | |
3575 | * total vcpus not a multiple of threads-per-core. | |
3576 | */ | |
3577 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3578 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3579 | cc->nr_threads, smp_threads); |
df8658de | 3580 | goto out; |
8149e299 DG |
3581 | } |
3582 | ||
535455fd IM |
3583 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3584 | if (!core_slot) { | |
ff9006dd IM |
3585 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3586 | goto out; | |
3587 | } | |
3588 | ||
535455fd | 3589 | if (core_slot->cpu) { |
ff9006dd IM |
3590 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3591 | goto out; | |
3592 | } | |
3593 | ||
a0ceb640 | 3594 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3595 | |
ff9006dd | 3596 | out: |
ff9006dd IM |
3597 | error_propagate(errp, local_err); |
3598 | } | |
3599 | ||
c20d332a BR |
3600 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3601 | DeviceState *dev, Error **errp) | |
3602 | { | |
c20d332a | 3603 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
81985f3b | 3604 | spapr_memory_plug(hotplug_dev, dev, errp); |
af81cf32 BR |
3605 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3606 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3607 | } |
3608 | } | |
3609 | ||
88432f44 DH |
3610 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, |
3611 | DeviceState *dev, Error **errp) | |
3612 | { | |
3ec71474 DH |
3613 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3614 | spapr_memory_unplug(hotplug_dev, dev); | |
a4261be1 DH |
3615 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3616 | spapr_core_unplug(hotplug_dev, dev); | |
3ec71474 | 3617 | } |
88432f44 DH |
3618 | } |
3619 | ||
cf632463 BR |
3620 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3621 | DeviceState *dev, Error **errp) | |
3622 | { | |
c86c1aff DHB |
3623 | sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3624 | MachineClass *mc = MACHINE_GET_CLASS(sms); | |
cf632463 BR |
3625 | |
3626 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3627 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3628 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3629 | } else { | |
3630 | /* NOTE: this means there is a window after guest reset, prior to | |
3631 | * CAS negotiation, where unplug requests will fail due to the | |
3632 | * capability not being detected yet. This is a bit different than | |
3633 | * the case with PCI unplug, where the events will be queued and | |
3634 | * eventually handled by the guest after boot | |
3635 | */ | |
3636 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3637 | } | |
6f4b5c3e | 3638 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3639 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3640 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3641 | return; | |
3642 | } | |
115debf2 | 3643 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3644 | } |
3645 | } | |
3646 | ||
94a94e4c BR |
3647 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3648 | DeviceState *dev, Error **errp) | |
3649 | { | |
c871bc70 LV |
3650 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3651 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3652 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3653 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3654 | } | |
3655 | } | |
3656 | ||
7ebaf795 BR |
3657 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3658 | DeviceState *dev) | |
c20d332a | 3659 | { |
94a94e4c BR |
3660 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3661 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3662 | return HOTPLUG_HANDLER(machine); |
3663 | } | |
3664 | return NULL; | |
3665 | } | |
3666 | ||
ea089eeb IM |
3667 | static CpuInstanceProperties |
3668 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3669 | { |
ea089eeb IM |
3670 | CPUArchId *core_slot; |
3671 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3672 | ||
3673 | /* make sure possible_cpu are intialized */ | |
3674 | mc->possible_cpu_arch_ids(machine); | |
3675 | /* get CPU core slot containing thread that matches cpu_index */ | |
3676 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3677 | assert(core_slot); | |
3678 | return core_slot->props; | |
20bb648d DG |
3679 | } |
3680 | ||
79e07936 IM |
3681 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
3682 | { | |
3683 | return idx / smp_cores % nb_numa_nodes; | |
3684 | } | |
3685 | ||
535455fd IM |
3686 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3687 | { | |
3688 | int i; | |
d342eb76 | 3689 | const char *core_type; |
535455fd IM |
3690 | int spapr_max_cores = max_cpus / smp_threads; |
3691 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3692 | ||
c5514d0e | 3693 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3694 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3695 | } | |
3696 | if (machine->possible_cpus) { | |
3697 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3698 | return machine->possible_cpus; | |
3699 | } | |
3700 | ||
d342eb76 IM |
3701 | core_type = spapr_get_cpu_core_type(machine->cpu_type); |
3702 | if (!core_type) { | |
3703 | error_report("Unable to find sPAPR CPU Core definition"); | |
3704 | exit(1); | |
3705 | } | |
3706 | ||
535455fd IM |
3707 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
3708 | sizeof(CPUArchId) * spapr_max_cores); | |
3709 | machine->possible_cpus->len = spapr_max_cores; | |
3710 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3711 | int core_id = i * smp_threads; | |
3712 | ||
d342eb76 | 3713 | machine->possible_cpus->cpus[i].type = core_type; |
f2d672c2 | 3714 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3715 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3716 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3717 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
3718 | } |
3719 | return machine->possible_cpus; | |
3720 | } | |
3721 | ||
6737d9ad | 3722 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3723 | uint64_t *buid, hwaddr *pio, |
3724 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3725 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3726 | { | |
357d1e3b DG |
3727 | /* |
3728 | * New-style PHB window placement. | |
3729 | * | |
3730 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3731 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3732 | * windows. | |
3733 | * | |
3734 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3735 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3736 | * | |
3737 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3738 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3739 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3740 | * 1TiB 64-bit MMIO windows for each PHB. | |
3741 | */ | |
6737d9ad | 3742 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3743 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3744 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3745 | int i; |
3746 | ||
357d1e3b DG |
3747 | /* Sanity check natural alignments */ |
3748 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3749 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3750 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3751 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3752 | /* Sanity check bounds */ | |
25e6a118 MT |
3753 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3754 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3755 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3756 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3757 | ||
3758 | if (index >= SPAPR_MAX_PHBS) { | |
3759 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3760 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3761 | return; |
3762 | } | |
3763 | ||
3764 | *buid = base_buid + index; | |
3765 | for (i = 0; i < n_dma; ++i) { | |
3766 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3767 | } | |
3768 | ||
357d1e3b DG |
3769 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3770 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3771 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3772 | } |
3773 | ||
7844e12b CLG |
3774 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3775 | { | |
3776 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3777 | ||
3778 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3779 | } | |
3780 | ||
3781 | static void spapr_ics_resend(XICSFabric *dev) | |
3782 | { | |
3783 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3784 | ||
3785 | ics_resend(spapr->ics); | |
3786 | } | |
3787 | ||
81210c20 | 3788 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 3789 | { |
2e886fb3 | 3790 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 3791 | |
5bc8d26d | 3792 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3793 | } |
3794 | ||
60c6823b CLG |
3795 | #define ICS_IRQ_FREE(ics, srcno) \ |
3796 | (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) | |
3797 | ||
3798 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) | |
3799 | { | |
3800 | int first, i; | |
3801 | ||
3802 | for (first = 0; first < ics->nr_irqs; first += alignnum) { | |
3803 | if (num > (ics->nr_irqs - first)) { | |
3804 | return -1; | |
3805 | } | |
3806 | for (i = first; i < first + num; ++i) { | |
3807 | if (!ICS_IRQ_FREE(ics, i)) { | |
3808 | break; | |
3809 | } | |
3810 | } | |
3811 | if (i == (first + num)) { | |
3812 | return first; | |
3813 | } | |
3814 | } | |
3815 | ||
3816 | return -1; | |
3817 | } | |
3818 | ||
9e7dc5fc CLG |
3819 | /* |
3820 | * Allocate the IRQ number and set the IRQ type, LSI or MSI | |
3821 | */ | |
3822 | static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) | |
3823 | { | |
3824 | ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); | |
3825 | } | |
3826 | ||
60c6823b CLG |
3827 | int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, |
3828 | Error **errp) | |
3829 | { | |
3830 | ICSState *ics = spapr->ics; | |
3831 | int irq; | |
3832 | ||
1d36c75a GK |
3833 | assert(ics); |
3834 | ||
60c6823b CLG |
3835 | if (irq_hint) { |
3836 | if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { | |
3837 | error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); | |
3838 | return -1; | |
3839 | } | |
3840 | irq = irq_hint; | |
3841 | } else { | |
3842 | irq = ics_find_free_block(ics, 1, 1); | |
3843 | if (irq < 0) { | |
3844 | error_setg(errp, "can't allocate IRQ: no IRQ left"); | |
3845 | return -1; | |
3846 | } | |
3847 | irq += ics->offset; | |
3848 | } | |
3849 | ||
9e7dc5fc | 3850 | spapr_irq_set_lsi(spapr, irq, lsi); |
60c6823b CLG |
3851 | trace_spapr_irq_alloc(irq); |
3852 | ||
3853 | return irq; | |
3854 | } | |
3855 | ||
3856 | /* | |
3857 | * Allocate block of consecutive IRQs, and return the number of the first IRQ in | |
3858 | * the block. If align==true, aligns the first IRQ number to num. | |
3859 | */ | |
3860 | int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, | |
3861 | bool align, Error **errp) | |
3862 | { | |
3863 | ICSState *ics = spapr->ics; | |
3864 | int i, first = -1; | |
3865 | ||
1d36c75a | 3866 | assert(ics); |
60c6823b CLG |
3867 | |
3868 | /* | |
3869 | * MSIMesage::data is used for storing VIRQ so | |
3870 | * it has to be aligned to num to support multiple | |
3871 | * MSI vectors. MSI-X is not affected by this. | |
3872 | * The hint is used for the first IRQ, the rest should | |
3873 | * be allocated continuously. | |
3874 | */ | |
3875 | if (align) { | |
3876 | assert((num == 1) || (num == 2) || (num == 4) || | |
3877 | (num == 8) || (num == 16) || (num == 32)); | |
3878 | first = ics_find_free_block(ics, num, num); | |
3879 | } else { | |
3880 | first = ics_find_free_block(ics, num, 1); | |
3881 | } | |
3882 | if (first < 0) { | |
3883 | error_setg(errp, "can't find a free %d-IRQ block", num); | |
3884 | return -1; | |
3885 | } | |
3886 | ||
9e7dc5fc | 3887 | first += ics->offset; |
60c6823b | 3888 | for (i = first; i < first + num; ++i) { |
9e7dc5fc | 3889 | spapr_irq_set_lsi(spapr, i, lsi); |
60c6823b | 3890 | } |
60c6823b CLG |
3891 | |
3892 | trace_spapr_irq_alloc_block(first, num, lsi, align); | |
3893 | ||
3894 | return first; | |
3895 | } | |
3896 | ||
3897 | void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) | |
3898 | { | |
3899 | ICSState *ics = spapr->ics; | |
3900 | int srcno = irq - ics->offset; | |
3901 | int i; | |
3902 | ||
3903 | if (ics_valid_irq(ics, irq)) { | |
3904 | trace_spapr_irq_free(0, irq, num); | |
3905 | for (i = srcno; i < srcno + num; ++i) { | |
3906 | if (ICS_IRQ_FREE(ics, i)) { | |
3907 | trace_spapr_irq_free_warn(0, i + ics->offset); | |
3908 | } | |
3909 | memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); | |
3910 | } | |
3911 | } | |
3912 | } | |
3913 | ||
77183755 CLG |
3914 | qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) |
3915 | { | |
3916 | ICSState *ics = spapr->ics; | |
3917 | ||
3918 | if (ics_valid_irq(ics, irq)) { | |
3919 | return ics->qirqs[irq - ics->offset]; | |
3920 | } | |
3921 | ||
3922 | return NULL; | |
3923 | } | |
3924 | ||
6449da45 CLG |
3925 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3926 | Monitor *mon) | |
3927 | { | |
3928 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3929 | CPUState *cs; |
3930 | ||
3931 | CPU_FOREACH(cs) { | |
3932 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3933 | |
5bc8d26d | 3934 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3935 | } |
3936 | ||
3937 | ics_pic_print_info(spapr->ics, mon); | |
3938 | } | |
3939 | ||
14bb4486 | 3940 | int spapr_get_vcpu_id(PowerPCCPU *cpu) |
2e886fb3 | 3941 | { |
b1a568c1 | 3942 | return cpu->vcpu_id; |
2e886fb3 SB |
3943 | } |
3944 | ||
648edb64 GK |
3945 | void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) |
3946 | { | |
3947 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
3948 | int vcpu_id; | |
3949 | ||
5d0fb150 | 3950 | vcpu_id = spapr_vcpu_id(spapr, cpu_index); |
648edb64 GK |
3951 | |
3952 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { | |
3953 | error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); | |
3954 | error_append_hint(errp, "Adjust the number of cpus to %d " | |
3955 | "or try to raise the number of threads per core\n", | |
3956 | vcpu_id * smp_threads / spapr->vsmt); | |
3957 | return; | |
3958 | } | |
3959 | ||
3960 | cpu->vcpu_id = vcpu_id; | |
3961 | } | |
3962 | ||
2e886fb3 SB |
3963 | PowerPCCPU *spapr_find_cpu(int vcpu_id) |
3964 | { | |
3965 | CPUState *cs; | |
3966 | ||
3967 | CPU_FOREACH(cs) { | |
3968 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3969 | ||
14bb4486 | 3970 | if (spapr_get_vcpu_id(cpu) == vcpu_id) { |
2e886fb3 SB |
3971 | return cpu; |
3972 | } | |
3973 | } | |
3974 | ||
3975 | return NULL; | |
3976 | } | |
3977 | ||
29ee3247 AK |
3978 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3979 | { | |
3980 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3981 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3982 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3983 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3984 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3985 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3986 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3987 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3988 | |
0eb9054c | 3989 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3990 | |
3991 | /* | |
3992 | * We set up the default / latest behaviour here. The class_init | |
3993 | * functions for the specific versioned machine types can override | |
3994 | * these details for backwards compatibility | |
3995 | */ | |
bcb5ce08 DG |
3996 | mc->init = spapr_machine_init; |
3997 | mc->reset = spapr_machine_reset; | |
958db90c | 3998 | mc->block_default_type = IF_SCSI; |
6244bb7e | 3999 | mc->max_cpus = 1024; |
958db90c | 4000 | mc->no_parallel = 1; |
5b2128d2 | 4001 | mc->default_boot_order = ""; |
a34944fe | 4002 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 4003 | mc->kvm_type = spapr_kvm_type; |
7da79a16 | 4004 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); |
e4024630 | 4005 | mc->pci_allow_0_address = true; |
debbdc00 | 4006 | assert(!mc->get_hotplug_handler); |
7ebaf795 | 4007 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 4008 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 4009 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 4010 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 4011 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 4012 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 4013 | hc->unplug_request = spapr_machine_device_unplug_request; |
88432f44 | 4014 | hc->unplug = spapr_machine_device_unplug; |
00b4fbe2 | 4015 | |
fc9f38c3 | 4016 | smc->dr_lmb_enabled = true; |
2e9c10eb | 4017 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
c5514d0e | 4018 | mc->has_hotpluggable_cpus = true; |
52b81ab5 | 4019 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 4020 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 4021 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 4022 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 4023 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
4024 | vhc->hpt_mask = spapr_hpt_mask; |
4025 | vhc->map_hptes = spapr_map_hptes; | |
4026 | vhc->unmap_hptes = spapr_unmap_hptes; | |
4027 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 4028 | vhc->get_patbe = spapr_get_patbe; |
1ec26c75 | 4029 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
7844e12b CLG |
4030 | xic->ics_get = spapr_ics_get; |
4031 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 4032 | xic->icp_get = spapr_icp_get; |
6449da45 | 4033 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
4034 | /* Force NUMA node memory size to be a multiple of |
4035 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
4036 | * in which LMBs are represented and hot-added | |
4037 | */ | |
4038 | mc->numa_mem_align_shift = 28; | |
33face6b | 4039 | |
4e5fe368 SJS |
4040 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
4041 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; | |
4042 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; | |
8f38eaf8 | 4043 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
09114fd8 | 4044 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; |
4be8d4e7 | 4045 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; |
33face6b | 4046 | spapr_caps_add_properties(smc, &error_abort); |
29ee3247 AK |
4047 | } |
4048 | ||
4049 | static const TypeInfo spapr_machine_info = { | |
4050 | .name = TYPE_SPAPR_MACHINE, | |
4051 | .parent = TYPE_MACHINE, | |
4aee7362 | 4052 | .abstract = true, |
6ca1502e | 4053 | .instance_size = sizeof(sPAPRMachineState), |
bcb5ce08 | 4054 | .instance_init = spapr_instance_init, |
87bbdd9c | 4055 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 4056 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 4057 | .class_init = spapr_machine_class_init, |
71461b0f AK |
4058 | .interfaces = (InterfaceInfo[]) { |
4059 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 4060 | { TYPE_NMI }, |
c20d332a | 4061 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 4062 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 4063 | { TYPE_XICS_FABRIC }, |
6449da45 | 4064 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
4065 | { } |
4066 | }, | |
29ee3247 AK |
4067 | }; |
4068 | ||
fccbc785 | 4069 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
4070 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
4071 | void *data) \ | |
4072 | { \ | |
4073 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
4074 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
4075 | if (latest) { \ |
4076 | mc->alias = "pseries"; \ | |
4077 | mc->is_default = 1; \ | |
4078 | } \ | |
5013c547 DG |
4079 | } \ |
4080 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
4081 | { \ | |
4082 | MachineState *machine = MACHINE(obj); \ | |
4083 | spapr_machine_##suffix##_instance_options(machine); \ | |
4084 | } \ | |
4085 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
4086 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
4087 | .parent = TYPE_SPAPR_MACHINE, \ | |
4088 | .class_init = spapr_machine_##suffix##_class_init, \ | |
4089 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
4090 | }; \ | |
4091 | static void spapr_machine_register_##suffix(void) \ | |
4092 | { \ | |
4093 | type_register(&spapr_machine_##suffix##_info); \ | |
4094 | } \ | |
0e6aac87 | 4095 | type_init(spapr_machine_register_##suffix) |
5013c547 | 4096 | |
8a4fd427 | 4097 | /* |
d8c0c7af | 4098 | * pseries-3.0 |
8a4fd427 | 4099 | */ |
d8c0c7af | 4100 | static void spapr_machine_3_0_instance_options(MachineState *machine) |
8a4fd427 DG |
4101 | { |
4102 | } | |
4103 | ||
d8c0c7af | 4104 | static void spapr_machine_3_0_class_options(MachineClass *mc) |
8a4fd427 DG |
4105 | { |
4106 | /* Defaults for the latest behaviour inherited from the base class */ | |
4107 | } | |
4108 | ||
d8c0c7af | 4109 | DEFINE_SPAPR_MACHINE(3_0, "3.0", true); |
8a4fd427 | 4110 | |
2b615412 DG |
4111 | /* |
4112 | * pseries-2.12 | |
4113 | */ | |
8a4fd427 | 4114 | #define SPAPR_COMPAT_2_12 \ |
67d7d66f DG |
4115 | HW_COMPAT_2_12 \ |
4116 | { \ | |
4117 | .driver = TYPE_POWERPC_CPU, \ | |
b9402026 GK |
4118 | .property = "pre-3.0-migration", \ |
4119 | .value = "on", \ | |
4120 | }, \ | |
4121 | { \ | |
4122 | .driver = TYPE_SPAPR_CPU_CORE, \ | |
4123 | .property = "pre-3.0-migration", \ | |
67d7d66f DG |
4124 | .value = "on", \ |
4125 | }, | |
8a4fd427 | 4126 | |
2b615412 DG |
4127 | static void spapr_machine_2_12_instance_options(MachineState *machine) |
4128 | { | |
d8c0c7af | 4129 | spapr_machine_3_0_instance_options(machine); |
2b615412 DG |
4130 | } |
4131 | ||
4132 | static void spapr_machine_2_12_class_options(MachineClass *mc) | |
4133 | { | |
d8c0c7af | 4134 | spapr_machine_3_0_class_options(mc); |
8a4fd427 | 4135 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); |
2b615412 DG |
4136 | } |
4137 | ||
8a4fd427 | 4138 | DEFINE_SPAPR_MACHINE(2_12, "2.12", false); |
2b615412 | 4139 | |
813f3cf6 SJS |
4140 | static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) |
4141 | { | |
4142 | spapr_machine_2_12_instance_options(machine); | |
4143 | } | |
4144 | ||
4145 | static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) | |
4146 | { | |
4147 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); | |
4148 | ||
4149 | spapr_machine_2_12_class_options(mc); | |
4150 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; | |
4151 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; | |
4152 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; | |
4153 | } | |
4154 | ||
4155 | DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); | |
4156 | ||
e2676b16 GK |
4157 | /* |
4158 | * pseries-2.11 | |
4159 | */ | |
2b615412 DG |
4160 | #define SPAPR_COMPAT_2_11 \ |
4161 | HW_COMPAT_2_11 | |
4162 | ||
e2676b16 GK |
4163 | static void spapr_machine_2_11_instance_options(MachineState *machine) |
4164 | { | |
2b615412 | 4165 | spapr_machine_2_12_instance_options(machine); |
e2676b16 GK |
4166 | } |
4167 | ||
4168 | static void spapr_machine_2_11_class_options(MachineClass *mc) | |
4169 | { | |
ee76a09f DG |
4170 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4171 | ||
2b615412 | 4172 | spapr_machine_2_12_class_options(mc); |
4e5fe368 | 4173 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
2b615412 | 4174 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); |
e2676b16 GK |
4175 | } |
4176 | ||
2b615412 | 4177 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 4178 | |
3fa14fbe DG |
4179 | /* |
4180 | * pseries-2.10 | |
4181 | */ | |
e2676b16 | 4182 | #define SPAPR_COMPAT_2_10 \ |
2b615412 | 4183 | HW_COMPAT_2_10 |
e2676b16 | 4184 | |
3fa14fbe DG |
4185 | static void spapr_machine_2_10_instance_options(MachineState *machine) |
4186 | { | |
2b615412 | 4187 | spapr_machine_2_11_instance_options(machine); |
3fa14fbe DG |
4188 | } |
4189 | ||
4190 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
4191 | { | |
e2676b16 GK |
4192 | spapr_machine_2_11_class_options(mc); |
4193 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); | |
3fa14fbe DG |
4194 | } |
4195 | ||
e2676b16 | 4196 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 4197 | |
fa325e6c DG |
4198 | /* |
4199 | * pseries-2.9 | |
4200 | */ | |
3fa14fbe | 4201 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
4202 | HW_COMPAT_2_9 \ |
4203 | { \ | |
4204 | .driver = TYPE_POWERPC_CPU, \ | |
4205 | .property = "pre-2.10-migration", \ | |
4206 | .value = "on", \ | |
4207 | }, \ | |
3fa14fbe | 4208 | |
fa325e6c DG |
4209 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
4210 | { | |
3fa14fbe | 4211 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
4212 | } |
4213 | ||
4214 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
4215 | { | |
46f7afa3 GK |
4216 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4217 | ||
3fa14fbe DG |
4218 | spapr_machine_2_10_class_options(mc); |
4219 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 4220 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 4221 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 4222 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
4223 | } |
4224 | ||
3fa14fbe | 4225 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 4226 | |
db800b21 DG |
4227 | /* |
4228 | * pseries-2.8 | |
4229 | */ | |
82516263 DG |
4230 | #define SPAPR_COMPAT_2_8 \ |
4231 | HW_COMPAT_2_8 \ | |
4232 | { \ | |
4233 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4234 | .property = "pcie-extended-configuration-space", \ | |
4235 | .value = "off", \ | |
4236 | }, | |
fa325e6c | 4237 | |
db800b21 DG |
4238 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
4239 | { | |
fa325e6c | 4240 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
4241 | } |
4242 | ||
4243 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
4244 | { | |
fa325e6c DG |
4245 | spapr_machine_2_9_class_options(mc); |
4246 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 4247 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
4248 | } |
4249 | ||
fa325e6c | 4250 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 4251 | |
1ea1eefc BR |
4252 | /* |
4253 | * pseries-2.7 | |
4254 | */ | |
357d1e3b DG |
4255 | #define SPAPR_COMPAT_2_7 \ |
4256 | HW_COMPAT_2_7 \ | |
4257 | { \ | |
4258 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4259 | .property = "mem_win_size", \ | |
4260 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
4261 | }, \ | |
4262 | { \ | |
4263 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4264 | .property = "mem64_win_size", \ | |
4265 | .value = "0", \ | |
146c11f1 DG |
4266 | }, \ |
4267 | { \ | |
4268 | .driver = TYPE_POWERPC_CPU, \ | |
4269 | .property = "pre-2.8-migration", \ | |
4270 | .value = "on", \ | |
5c4537bd DG |
4271 | }, \ |
4272 | { \ | |
4273 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4274 | .property = "pre-2.8-migration", \ | |
4275 | .value = "on", \ | |
357d1e3b DG |
4276 | }, |
4277 | ||
4278 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
4279 | uint64_t *buid, hwaddr *pio, | |
4280 | hwaddr *mmio32, hwaddr *mmio64, | |
4281 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
4282 | { | |
4283 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4284 | const uint64_t base_buid = 0x800000020000000ULL; | |
4285 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4286 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4287 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4288 | const uint32_t max_index = 255; | |
4289 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4290 | ||
4291 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4292 | hwaddr phb0_base, phb_base; | |
4293 | int i; | |
4294 | ||
0c9269a5 | 4295 | /* Do we have device memory? */ |
357d1e3b DG |
4296 | if (MACHINE(spapr)->maxram_size > ram_top) { |
4297 | /* Can't just use maxram_size, because there may be an | |
0c9269a5 DH |
4298 | * alignment gap between normal and device memory regions |
4299 | */ | |
b0c14ec4 DH |
4300 | ram_top = MACHINE(spapr)->device_memory->base + |
4301 | memory_region_size(&MACHINE(spapr)->device_memory->mr); | |
357d1e3b DG |
4302 | } |
4303 | ||
4304 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4305 | ||
4306 | if (index > max_index) { | |
4307 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4308 | max_index); | |
4309 | return; | |
4310 | } | |
4311 | ||
4312 | *buid = base_buid + index; | |
4313 | for (i = 0; i < n_dma; ++i) { | |
4314 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4315 | } | |
4316 | ||
4317 | phb_base = phb0_base + index * phb_spacing; | |
4318 | *pio = phb_base + pio_offset; | |
4319 | *mmio32 = phb_base + mmio_offset; | |
4320 | /* | |
4321 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4322 | * fallback behaviour of automatically splitting a large "32-bit" | |
4323 | * window into contiguous 32-bit and 64-bit windows | |
4324 | */ | |
4325 | } | |
db800b21 | 4326 | |
1ea1eefc BR |
4327 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
4328 | { | |
f6229214 MR |
4329 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
4330 | ||
672de881 | 4331 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 4332 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
4333 | } |
4334 | ||
4335 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
4336 | { | |
3daa4a9f TH |
4337 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4338 | ||
db800b21 | 4339 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4340 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
db800b21 | 4341 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 4342 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4343 | } |
4344 | ||
db800b21 | 4345 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4346 | |
4b23699c DG |
4347 | /* |
4348 | * pseries-2.6 | |
4349 | */ | |
1ea1eefc | 4350 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
4351 | HW_COMPAT_2_6 \ |
4352 | { \ | |
4353 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4354 | .property = "ddw",\ | |
4355 | .value = stringify(off),\ | |
4356 | }, | |
1ea1eefc | 4357 | |
4b23699c DG |
4358 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
4359 | { | |
672de881 | 4360 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
4361 | } |
4362 | ||
4363 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
4364 | { | |
1ea1eefc | 4365 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4366 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 4367 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
4368 | } |
4369 | ||
1ea1eefc | 4370 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4371 | |
1c5f29bb DG |
4372 | /* |
4373 | * pseries-2.5 | |
4374 | */ | |
4b23699c | 4375 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
4376 | HW_COMPAT_2_5 \ |
4377 | { \ | |
4378 | .driver = "spapr-vlan", \ | |
4379 | .property = "use-rx-buffer-pools", \ | |
4380 | .value = "off", \ | |
4381 | }, | |
4b23699c | 4382 | |
5013c547 | 4383 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 4384 | { |
672de881 | 4385 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
4386 | } |
4387 | ||
4388 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
4389 | { | |
57040d45 TH |
4390 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4391 | ||
4b23699c | 4392 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4393 | smc->use_ohci_by_default = true; |
4b23699c | 4394 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
4395 | } |
4396 | ||
4b23699c | 4397 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4398 | |
4399 | /* | |
4400 | * pseries-2.4 | |
4401 | */ | |
80fd50f9 CH |
4402 | #define SPAPR_COMPAT_2_4 \ |
4403 | HW_COMPAT_2_4 | |
4404 | ||
5013c547 | 4405 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 4406 | { |
5013c547 DG |
4407 | spapr_machine_2_5_instance_options(machine); |
4408 | } | |
1c5f29bb | 4409 | |
5013c547 DG |
4410 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4411 | { | |
fc9f38c3 DG |
4412 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4413 | ||
4414 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4415 | smc->dr_lmb_enabled = false; |
f949b4e5 | 4416 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
4417 | } |
4418 | ||
fccbc785 | 4419 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4420 | |
4421 | /* | |
4422 | * pseries-2.3 | |
4423 | */ | |
38ff32c6 | 4424 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
4425 | HW_COMPAT_2_3 \ |
4426 | {\ | |
4427 | .driver = "spapr-pci-host-bridge",\ | |
4428 | .property = "dynamic-reconfiguration",\ | |
4429 | .value = "off",\ | |
4430 | }, | |
38ff32c6 | 4431 | |
5013c547 | 4432 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 4433 | { |
5013c547 | 4434 | spapr_machine_2_4_instance_options(machine); |
d25228e7 JW |
4435 | } |
4436 | ||
5013c547 | 4437 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4438 | { |
fc9f38c3 | 4439 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 4440 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 4441 | } |
fccbc785 | 4442 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4443 | |
1c5f29bb DG |
4444 | /* |
4445 | * pseries-2.2 | |
4446 | */ | |
4447 | ||
4448 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
4449 | HW_COMPAT_2_2 \ |
4450 | {\ | |
4451 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4452 | .property = "mem_win_size",\ | |
4453 | .value = "0x20000000",\ | |
4454 | }, | |
4455 | ||
5013c547 | 4456 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 4457 | { |
5013c547 | 4458 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 4459 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
4460 | } |
4461 | ||
5013c547 | 4462 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4463 | { |
fc9f38c3 | 4464 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 4465 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 4466 | } |
fccbc785 | 4467 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4468 | |
1c5f29bb DG |
4469 | /* |
4470 | * pseries-2.1 | |
4471 | */ | |
4472 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 4473 | HW_COMPAT_2_1 |
3dab0244 | 4474 | |
5013c547 | 4475 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 4476 | { |
5013c547 | 4477 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 4478 | } |
d25228e7 | 4479 | |
5013c547 | 4480 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4481 | { |
fc9f38c3 | 4482 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 4483 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 4484 | } |
fccbc785 | 4485 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4486 | |
29ee3247 | 4487 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4488 | { |
29ee3247 | 4489 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4490 | } |
4491 | ||
29ee3247 | 4492 | type_init(spapr_machine_register_types) |